JPH06132311A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To provide the manufacturing method of semiconductor device capable of forming a gate electrode in effective length not exceeding 0.5mum at excellent throughput using an inexpensive device. CONSTITUTION:A gate electrode 2, a source electrode 3 and a drain electrode 4 are formed on the surface of an n type operating layer 1a using ordinary photolithography. Next, the whole surface excluding the exposed n type operating layer 1a and nearby parts only is covered with a photoresist film 5. Next, the n type operating layer 1a is ion-implanted with isolation impurities downward from the gate electrode 2 so that the impurities may be diffused in the parts beneath the ends of the gate electrode 2 to form isolation layers 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. Specifically, the present invention relates to a method of manufacturing a field effect semiconductor device such as MESFET.

[0002]

BACKGROUND ART FIG. 3 is a sectional view showing a conventional MESFET (Schottky type field effect transistor) 30. The MESFET 30 has a semi-insulating substrate 31 with a surface layer
The type operation layer 31a is formed, the source electrode 33 and the drain electrode 34 are formed in ohmic contact with the surface of the n type operation layer 31a, and the gate electrode 32 is formed in Schottky contact.

[0003]

[Problems to be Solved by the Invention] Such MESFE
In the T30, generally but higher frequency characteristics gate length L _g is small to improve, by the electrode forming method using a normal photolithography method, the gate length L _g is 0.
It is difficult to form the gate electrode 32 having a thickness of 5 μm or less.

If the electron beam direct writing exposure method is used, a fine gate electrode 3 having a gate length L _g of 0.5 μm or less is obtained.
2 can be formed, but the device becomes expensive and the throughput becomes poor.

The present invention has been made in view of the above-mentioned drawbacks of the conventional examples, and an object thereof is to form a gate electrode having an effective gate length of 0.5 μm or less with an inexpensive device and at a high throughput. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be manufactured.

[0006]

According to a method of manufacturing a semiconductor device of the present invention, a gate electrode, a source electrode and a drain electrode are formed on the surface of an operating layer, and then the gate electrode is used as a mask for isolation of the operating layer. It is characterized in that an impurity is ion-implanted and the impurity is diffused below the end portion of the gate electrode to form an isolation layer.

Further, the operation layer may be formed deeper in the region where the isolation layer is formed than in other regions.

[0008]

According to the method of manufacturing a semiconductor device of the present invention, isolation impurities are ion-implanted into the operating layer using the gate electrode as a mask, and the impurities are diffused below the end portion of the gate electrode. Therefore, the contact width (effective gate length) between the gate electrode and the operating layer can be made smaller than the width of the gate electrode by the amount of diffusion of the isolation layer below the gate electrode. Therefore, for example, if a gate electrode having a width of 0.5 μm is formed by using a photolithography method and impurities are ion-implanted and diffused below the end portion of the gate electrode, the effective gate length is 0.5 μm.
The following gate electrodes can be formed with a low cost exposure apparatus and high throughput.

Further, if the operating layer is formed deeper in the region where the isolation layer is formed than in the other regions, it is possible to prevent the operating layer from being thinned by the isolation layer and increasing the parasitic resistance. be able to.

[0010]

1 (a) to 1 (d) show a method of manufacturing a MESFET 10 according to an embodiment of the present invention. This MES
In the method of manufacturing the FET 10, as shown in FIG. 1A, after the n-type operating layer 1a is formed on the surface layer portion of the semi-insulating semiconductor substrate 1 by the ion implantation method or the epitaxial growth method, the ordinary photolithography is performed. By pattern formation by a method, an electrode material is vapor-deposited to form the gate electrode 2, the source electrode 3 and the drain electrode 4. At this time, the width L _{g of the} gate electrode is 0.5 μm, which is the lower limit that can be formed with good reproducibility by, for example, the photolithography method.
I will keep it.

Next, as shown in FIG. 1B, only the gate electrode 2 and the n-type operating layer 1a in the vicinity thereof are exposed, and the other regions are covered with a photoresist film 5, and isolation impurities [eg, Semi-insulating semiconductor substrate 1 is GaAs
In the case of being formed of, boron (B), oxygen (O), etc.]
Is implanted from above the gate electrode 2 with a predetermined implantation energy and a predetermined dose amount.

At this time, the isolation impurities are as shown in FIG.
As shown in (c), the n-type operating layer 1a in the portion exposed from the photoresist film 5 is implanted from the surface thereof to a depth d _i , and is also laterally formed, that is, the gate electrode 2 is formed.
Δ from the end of the gate electrode 2 to the bottom of the gate electrode 2 and from the opening end of the photoresist film 5 to the bottom of the photoresist film 5.
Spread L only.

As a result, the isolation layer 6 is formed from below both end portions of the gate electrode 2 to below the opening end of the photoresist film 5, and the isolation layer 6 makes contact between the gate electrode 2 and the n-type operating layer 1a. The width (effective gate length) L _e is reduced by twice the width L _g of the gate electrode 2 by ΔL, and the effective gate length L _e is represented by the formula L _e = L _g −2ΔL. Since the width L _g of the gate electrode is set to 0.5 μm, the effective gate length L _e is 0.5 μm or less. Finally, the resist film 5 is removed to remove the MESFET 10
Is completed [Fig. 1 (d)].

As described above, in this embodiment, the photolithography method using a simple exposure apparatus is used to reduce
After forming the gate electrode 2 of 5μm wide, isolation impurity ions are implanted, the isolation impurity is diffused laterally gate electrode 2 and the n-type active layer 1a of the contact width (effective gate length) L _e Reduce to 0.5 μm or less. Therefore, the gate electrode 2 having an effective gate length L _e of 0.5 μm or less can be formed with a low-cost exposure apparatus and high throughput.

Incidentally, the p-type isolation layer may be formed by using the impurity for isolation as an impurity having a conductivity type opposite to that of the operating layer, that is, a p-type impurity.

Next, a MESF according to another embodiment of the present invention will be described.
A method for manufacturing the ET20 will be described. First, similarly to the embodiment of FIG. 1, a gate electrode 2, a source electrode 3 and a drain electrode 4 are formed, the gate electrode 2 and its vicinity are exposed and covered with a photoresist film 5 [see FIG. 1 (b)]. ]. Next, n-type impurities are deeply implanted into the region of the semi-insulating semiconductor substrate 1 where the isolation layer 6 is to be formed, and the bottom of the n-type operating layer 1a in that region is formed deeper than the other regions. After that, neutral impurities are ion-implanted into the same region to form the isolation layer 6.

In this embodiment, as shown in FIG.
Since the bottom of the n-type operating layer 1a is formed deeper than the other regions under the isolation layer 6, the thickness of the n-type operating layer 1a is reduced by the isolation layer 6, and the source / drain electrodes 3, 4 are formed. It is possible to prevent the parasitic resistance of the current flowing between them from increasing.

[0018]

According to the method of manufacturing a semiconductor device of the present invention, an impurity for isolation is ion-implanted into the operating layer by using the gate electrode as a mask, and the impurity is diffused below the end portion of the gate electrode. The contact width (effective gate length) of the operating layer can be smaller than the width of the gate electrode. Therefore, for example, if a gate electrode having a width of 0.5 μm is formed by using a photolithography method and impurities are ion-implanted to reduce the contact width between the gate electrode and the operating layer, the effective gate length is 0.5 μm or less. The gate electrode can be formed with good throughput by an inexpensive and simple exposure apparatus.

Further, if the operating layer is formed deeper in the region where the isolation layer is formed than in the other regions, it is possible to prevent the operating layer from being thinned by the isolation film and increasing the parasitic resistance. Therefore, the high frequency characteristics can be improved.

[Brief description of drawings]

1A, 1B, 1C and 1D are cross-sectional views showing a method for manufacturing a MESFET according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a MESFET according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a MESFET according to a conventional example.

[Explanation of symbols]

 1 semi-insulating semiconductor substrate 1a n-type operating layer 2 gate electrode 3 source electrode 4 drain electrode 5 photoresist film 6 isolation layer

Claims (2)

[Claims] 1. A gate electrode, a source electrode and a drain electrode are formed on the surface of the operating layer, and then an impurity for isolation is ion-implanted into the operating layer using the gate electrode as a mask, and the impurity is applied to an end portion of the gate electrode. A method for manufacturing a semiconductor device, comprising: forming an isolation layer by diffusing underneath. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the bottom of the operating layer is formed deeper in the region where the isolation layer is formed than in the other regions.