JPH06125297A - Selective call radio receiver - Google Patents

Abstract

PURPOSE:To increase a synchronism restoration ratio without lowering the efficiency of battery saving by increasing a detection ratio for bit rate detection only for a certain period of time after step out of the synchronism, and suppressing the detection ratio to a low level afterwards. CONSTITUTION:A radio part 2 performs intermittent reception by a battery saving signal supplied from a decoder 3. The decoder 3 performs synchronous control by utilizing a reference clock 3 and detecting a bit rate. An MPU increases the bit rate detection ratio of the decoder 3 for a certain period of time after the step out of the synchronism corresponding to the change (synchronization, asynchronization) of synchronous monitor output representing a synchronism securing state outputted by the synchronous control of the decoder 3, and afterwards, suppresses it to the low level. The MPU utilizes an EEPROM 6, a RAM 7 as external memory, and supplies message output to a driver 9, and outputs it to a speaker 10, a LED 11, and a vibrator 12, and also, displays it on an LCD 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio selective call receiver, and more particularly to a radio selective call receiver which ensures an improvement in synchronization recovery rate without reducing the efficiency of battery saving of a power source.

[0002]

2. Description of the Related Art There are various types of radio selective call receivers, and there are various selective call signals used for calling, but the basic configuration is almost the same.

FIG. 10 shows an example of a basic format of a selective calling signal used in this radio selective calling receiver.
This selective call signal is based on the document "STANDARD MES".
SAGE FORMATS FOR DIGITAL
RADIO PAGING ”(Post Office
Code Standardization Adv
isory Group (POCSAG), Autumn
n. 1980).

POCSAG is a time division system,
On the radio selective calling receiver side, the so-called "battery saving operation" is performed in which the receiving circuit is turned on only in the time slot group to which the wireless selective calling receiver belongs, and turned off in other cases, in order to reduce current consumption.

10A shows the batch stream, FIG. 10B shows the batch shown in FIG. 10A, and FIG. 10C shows the codeword shown in FIG. 10B.

In FIG. 10A, in the preamble signal, 1010 ...
C) is a 32-bit signal for synchronizing codewords.

Further, in each of the groups 1 to 8 shown in FIG. 10B, each radio selective calling receiver is
Only the signal of the group to which it belongs is intermittently received.

The selective calling signal shown in FIG. 10 (a) is a selective calling number unique to each radio selective calling receiver is BC.
It is H-coded and is set to MSB = 0 of the codeword.

The message signal is a BCH coded version of the message to be transmitted.
B = 1 is set.

In the POCSAG format shown in FIG. 10, since the preamble signal is transmitted only once in one batch stream, if the electric field is weakened due to fading or the like and the synchronization is lost during the signal reception, the subsequent Data cannot be received.

Therefore, in the conventional selective call receiver, P
To enable synchronization recovery with signals other than the preamble signal at the beginning of the batch stream with the OCSAG code,
It detects the bit rate of the received signal, cancels the battery saving operation, and shifts to the sync signal search mode.

[0012]

However, in the conventional radio selective calling receiver, if the detection rate of bit rate detection is increased, the false detection rate due to noise is also increased, which is why There is a problem in that the side effect that leads to a reduction in battery saving efficiency and a shortened battery life cannot be avoided.

The object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a radio selective call receiver capable of ensuring an improvement in synchronization recovery rate without lowering battery saving efficiency.

[0014]

SUMMARY OF THE INVENTION A radio selective call receiver according to the present invention performs intermittent reception for battery saving, receives a radio selective call signal, and receives and processes a message. And a bit rate detecting means for detecting a specific bit rate of the received signal and controlling the synchronization by the synchronizing control means. Bit rate detection rate control means for controlling the detection rate by the rate detection means in correspondence with the synchronization secured state of the synchronization control means to improve the synchronization recovery rate without reducing the efficiency of battery saving.

Further, in the radio selective calling receiver of the present invention, the bit rate detection rate control means increases the bit rate detection rate for a predetermined fixed time after loss of synchronization in the synchronization control means, and thereafter the bit rate detection rate. Is suppressed to ensure a high synchronization recovery rate.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment shown in FIG. 1 demodulates the antenna 1, the received modulated wave acquired by the antenna 1, and the decoder 3
A radio unit 2 for performing a battery saving reception operation under the control of the above, a decoder 3 including a synchronization control unit and a bit rate detection unit for decoding and outputting a message, and a message including a bit rate detection rate control unit for the decoder 3. Is sent to the driver 9 and the LCD (Liquid
d Crystal Display) 5 displayable M
PU (Micro Processor Unit) 4
An LCD 5, an EEPROM 6 and a RAM 7 used as an external memory of the MPU 4, a driver 9, a function switch 8 for setting a display pattern, a speaker 10 for receiving an output of the driver 9 and displaying to a wearer, an LED. (Light Emitt
ing Diode) 11 and vibrator 12,
It has a configuration including a reference clock 13 and an MPU operation clock 14.

Next, the operation of this embodiment will be described.

The received modulated wave obtained by the antenna 1 is demodulated by the radio section 2 and the demodulated signal c is sent to the decoder 3.

The radio section 2 performs an intermittent reception operation for suppressing the consumption of the battery under the control of the battery saving control signal 6 supplied from the decoder 3.

The MPU 4 reads out the selective calling number of its own receiver set in the EEPROM 6 and sets it in the decoder 3 via the address bus e.

The decoder 3 collates the selective call number of its own receiver with the demodulation number c supplied from the radio section 2, and if they match, an interrupt signal d for notifying that the selective call number has been detected and the address bus e. And MP using data bus f
Output to U4. After that, the interrupt signal d and the address bus e
And the data bus f are collectively MPU interface w
Call. The decoder 3 then performs error correction on the data sent following the selective call signal, and sends only the information bits to the MPU 4 using the MPU interface w for each codeword shown in FIG.

The MPU 4 receives the selective calling number detection information from the decoder 3 and receives RA from the MPU 4 built-in or the external RA.
M, in this embodiment, it is stored in the external RAM 7. If data is subsequently sent from the decoder 3, it is judged whether the data is message information or selective call code, and if it is message information, it is stored in the buffer area of the RAM 7. The MPU 4 processes this processing using the reference clock signal g sent by the reference clock 13 as the operation clock.
In this case, if the data is the selective call code, the reception of the data is stopped at that time and the MPU operation clock 14
Is started, and the data stored in the buffer area of the RAM 7 until then is processed by the clock of the MPU operation clock 14 to generate a message (character data) in the RAM 7
Stored in the message memory area of.

FIG. 2 is a timing chart of the message receiving operation of the decoder 3 and MPU.

FIG. 2A shows the timing of the battery saving control signal b when the POCSAG received signal does not include the selective call signal addressed to the own receiver.
2 is the timing of the battery saving control signal b when the selective call signal A is addressed to the own receiver, (3) of FIG. 2 is the timing of the interrupt signal d after the self receiver receives the selective call signal, and further of FIG. 4) shows the oscillation timing of the MPU operation clock, which indicates that the clock is oscillating at the high level. At this timing, the MPU 4 uses the MPU operation clock 14 as an operation clock to process the data in the buffer memory of the RAM 7 and store it in the message memory as character data.

After the reception of the message signal, the MPU 4 drives the speaker 10, the LED 11 and the vibrator 12 through the driver 9 to notify the wearer and the LCD.
The content of the received message is displayed in 5.

Which one of the speaker 10, the LED 11 and the vibrator 12 is used for the notification is E.
It is preset in the EPROM 6, and is determined based on this setting information and the setting combination of the function switch 8. The message stored in the RAM 7 can be displayed on the LCD 5 again by the function switch 8.

FIG. 3 is a block diagram showing a detailed structure of the decoder 3 shown in FIG.

The decoder 3 includes a bit synchronization circuit 301 for detecting bit synchronization and a synchronization control circuit 302 for performing synchronization control necessary for intermittent reception for battery saving.
And a preamble / SC detection circuit 303 for detecting a preamble and a synchronization signal of the input POCSAG signal, and a BCH error correction circuit 30 for correcting an error of a codeword.
4, and a selective call code detection circuit 3 for detecting the selective call code
05, a bit rate detection circuit 306 for detecting a bit rate, and an MPU for interfacing with the MPU 4.
An interface circuit 307, an interrupt control circuit 308 that outputs an interrupt signal d to the MPU 4, and an oscillation circuit 309 that generates a reference clock signal are provided, and the reference clock 13 is also shown in FIG.

The bit synchronization circuit 301 includes an oscillator circuit 309.
From the radio section 2 to the demodulation signal c
To generate a reproduction clock signal m.

The preamble / SC detection circuit 303 samples the demodulated signal c by the reproduced clock signal m, detects the preamble signal shown in FIG. 10, generates the preamble detection signal i, and also detects the SC (synchronization signal). Generates an SC detection signal j.

The sync control circuit 302 outputs a battery saving control signal b for controlling intermittent reception for battery saving.

When the POCSAG signal is not received, the battery saving control signal b is sent to the radio section 2 to perform the battery saving operation (preamble search mode). After receiving the bit rate detection signal k from the bit rate detection circuit 306, the continuous reception state is entered. When the SC detection signal j is received, the state becomes synchronous and the battery saving operation is resumed (selective call code search mode).
Then, the selective call code is received at the timing of the group (time slot) to which the own receiver belongs. Further, it receives the selective call code coincidence detection signal o output from the selective call code detection circuit 305, which will be described later, and continuously holds the wireless unit 2 in the receiving state for receiving the subsequent message signal.

A BCH error correction circuit 304, which will be described later, is also provided.
When the out-of-synchronization request signal q output by is received, the synchronization state is released and the battery saving operation of the preamble search mode is started.

From the synchronization control circuit 302, the synchronization state monitor signal r is supplied to the MPU interface circuit 307 and further transmitted to the MPU 4.

Further, the synchronization control circuit 302 outputs an own group signal h designating the group to which the own receiver belongs to the selective call code detection circuit 305.

From the synchronization control circuit 302, the word timing signal 1 is supplied to the BCH error correction circuit 304 and the bit rate detection circuit 306.

The selective call code detection circuit 305 collates the selective call code shown in FIG. 10 at the timing of its own group signal h provided from the synchronization control circuit 302, and if they match, synchronizes the selective call code match detection signal o. Control circuit 302
To the MPU interface circuit 307. MPU
The interface circuit 307 is an MPU interface w
Further, it is sent to the MPU 4 via.

The BCH error correction circuit 304 performs error correction of the demodulation signal c transmitted from the radio section 2 at the timing of the word timing signal 1 provided from the synchronization control circuit 302, and supplies the message data p to the MPU interface circuit 307. Then, the message data p is further supplied to the MPU 4 via the interface w.

If uncorrectable errors in the code received in the synchronized state continue for a certain number of times, the synchronization control circuit 30
The out-of-synchronization request signal q is transmitted to 2.

The bit rate detection circuit 306 compares the reproduced clock signal m provided from the bit synchronization circuit 301 with the demodulated signal c, and the POCSAG to be received by the own receiver.
Determine whether the bit rate of the signal, POCSA
When the bit rate is the G signal, the bit rate detection signal k is output. This bit rate detection signal k is PO
It is used as an activation from the battery saving operation in the state where the CSAG signal is not received to the operation for searching for the synchronization signal SC, and is also used for canceling the battery saving operation other than the preamble signal. The bit rate detection circuit 306 will be described later in detail.

The MPU interface circuit 307 is
Performs interface processing for controlling input / output of data with PU4.

The interrupt control circuit 308 is a circuit for controlling the transmission of the interrupt signal d to the MPU4.
When the data to be sent to or the state change occurs, the interrupt signal d is sent to the MPU 4 by the interrupt request signal n supplied from the MPU interface circuit 307.

FIG. 4 shows the bit rate detection circuit 30 of FIG.
6 is a block diagram showing a detailed configuration of No. 6.

4, the window frame generation circuit 61 uses the reference clock signal g from the reference clock 13 and the reproduced clock signal m from the bit synchronization circuit 301,
The window frame signal s as shown in FIG.

The edge position judgment circuit 62 outputs the judgment signal t shown in FIG. 5 using the demodulated signal c from the radio section 2 and the window frame signal s. As shown in FIG. 5, the determination signal t determines whether or not the change point of the demodulation signal c is included in the range of the window frame signal s, and is output when it is included.

The counter 63 is reset by the word timing signal 1 provided from the synchronization control circuit 302 shown in FIG. 5, and counts the judgment signal t for each word.

The edge counter value setting unit 65 receives the edge counter setting signal u from the MPU 4 via the MPU interface circuit 307 and sets the edge counter value.

The comparator 64 compares the output count value of the counter 63 with the edge counter value set in the edge counter value setting section 65, and if they match, the bit rate detection signal k shown in FIG. It is sent to 302.

FIG. 6 is a block diagram showing the detailed structure of the synchronization control circuit 302 of FIG.

The 32-bit bit counter 21 of FIG. 6 counts the reproduced clock signal m provided from the bit synchronization circuit 301 and determines the reference timing of 1 word.
The word timing signal 1 shown in (1) is generated and sent to the 17-ary word counter 22, the BCH error correction circuit 304 and the bit rate detection circuit 306.

The 17-adic word counter 22 generates the timing of 1 word (1 batch), and the self-group comparison unit 2
Send to 4.

The own group comparison unit 24 compares the output value of the 17-ary word counter to see if it is the own group, and if it is the own group, the own group signal h at the timing of the own group.
To occur.

The synchronization state control unit 23 uses the preamble / S
The preamble detection signal i and the SC detection signal j from the C detection circuit 303, the out-of-sync request signal q from the BCH error correction circuit 304, the selective call code match detection signal o from the selective call code detection circuit 305, and further bits The simultaneous state is controlled by using the bit rate detection signals k and the like from the rate detection circuit 306 as start signals, and the synchronization state monitor signal r
And a battery saving control signal b are generated.

FIG. 7 shows the contents of operation state transition of the synchronization state control unit 23.

FIG. 8 is a flowchart of the bit detection rate control operation of the MPU 4 of FIG.

When an out-of-sync interrupt occurs (step 1
01), the number of edge counters for bit rate detection is reduced, and this is continued for a fixed time (steps 102, 10).
3) Increase the bit rate detection rate, and then increase the number of edge counters for bit rate detection (step 104)
The bit rate detection rate is kept low, and the sync recovery rate is increased without reducing the battery saving efficiency.

This will be specifically described as follows.

In the normal state, the bit rate detection circuit 306
The edge counter setting value set in the edge counter value setting unit 65 is set to N.

When the MPU 4 receives, via the MPU interface circuit 307, an event in which the synchronous monitor signal r provided from the synchronous state control unit 23 of the synchronous control circuit 302 changes from the synchronous state to the asynchronous state, the bit rate detection circuit 306 Set the edge counter setting value N to MP
The bit rate detection rate is increased by subtracting M (N> M) by the edge counter setting signal u via the U interface circuit 307. After that, the device waits for a certain period of time, and the bit rate detection rate is lowered by returning the edge counter setting value of the edge counter value setting unit 65 of the bit rate detecting circuit 306 to N after a certain period of time.

FIG. 9 shows the MP when controlling the bit rate detection rate.
7 is a timing chart of operations of U4 and the decoder 3.

FIG. 9 (1) shows the timing of the battery saving control signal when the transmission signal ends and the receiver goes out of synchronization. (2) of FIG. 9 shows the timing of the interrupt signal d when the synchronization is lost. In this case, an interrupt occurs when the synchronous state monitor signal r output from the synchronous control circuit 302 changes from the synchronous state to the asynchronous state. In addition, (3) of FIG.
Is the operation timing. The MPU 4 decrements the edge counter setting value set in the edge counter value setting unit 65 of the bit rate detection circuit 306 of the decoder 3 at this timing.

In this way, the bit rate detection rate is increased for a certain period of time after the reception synchronization is lost, and thereafter kept low to ensure the increase in the synchronization recovery rate without deteriorating the efficiency of battery saving. be able to.

[0065]

As described above, according to the present invention, if the conventional radio selective calling receiver increases the detection rate of bit rate detection to facilitate synchronization recovery, the false detection rate of false detection due to noise also increases. This has the side effect of reducing the battery saving efficiency and shortening the battery life. On the other hand, increase the bit rate detection rate for a certain period of time after synchronization is lost, and then keep the detection rate low. This has the effect of ensuring an improved synchronization recovery rate without degrading the efficiency of battery saving.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of a message receiving operation of the decoder 3 and MPU 4 of FIG.

3 is a block diagram showing a detailed configuration of a decoder 3 in FIG.

4 is a block diagram showing a detailed configuration of a bit rate circuit 306 in FIG.

5 is a timing chart of the operation of the bit rate circuit 306 of FIG.

6 is a block diagram showing a detailed configuration of a synchronization control circuit 302 in FIG.

7 is an explanatory diagram of operation state transition of the synchronization state control unit 23 of FIG.

8 is a flowchart of a bit rate detection rate control operation of the MPU 4 of FIG.

9 is a timing chart of the operations of the decoder 3 and the MPU 4 of FIG. 1 when controlling the bit rate detection rate.

FIG. 10 is a signal format of POCSAG as a basic format example of a selective call signal used for calling a selective call receiver.

[Explanation of symbols]

 1 Antenna 2 Radio Section 3 Decoder 4 MPU 5 LCD 6 EEPROM 7 RAM 8 Function Switch 9 Driver 10 Speaker 11 LED 12 Vibrator

Claims (2)

[Claims] 1. A radio selective call receiver that performs intermittent reception for battery saving and receives and processes a message by receiving a selective call signal by radio, and controls to secure a synchronization state between the input received signal and the receiver. Synchronization control means for performing, a bit rate detecting means for detecting a specific bit rate of the received signal and subjecting the synchronization control means to control for ensuring synchronization, and a detection rate by the bit rate detecting means for ensuring synchronization of the synchronization control means. A radio selective calling receiver, comprising: a bit rate detection rate control means for controlling according to a state and improving a sync recovery rate without lowering battery saving efficiency. 2. The bit rate detection rate control means increases the bit rate detection rate for a predetermined fixed time after loss of synchronization in the synchronization control means, and thereafter suppresses the bit rate detection rate to a low level to reduce the synchronization recovery rate. 2. The radio selective call receiver according to claim 1, wherein the improvement is ensured.