JPH11234718A - Radio call receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a reception ratio in intermittent reception and to reduce power consumption by realizing the non-operation state of a synchronizing code detecting part after establishment of synchronization and immediately stopping the operation of a radio demodulating part at the time of judging the absence of the address of its own frame or the absence of pull-out during a code word receiving operation. SOLUTION: When judgement information indicating transition to a pre-ample detection mode is transmitted from a mode judging part 22, an intermittent receiving timing generating part 23 outputs a power source ON/OFF signal (b) for turning ON the power source of an RF part during 16 bits with the point of time as start. Then, when information indicating transition to a synchronizing code detection mode is communicated from the mode judging part 22, the power source of the RF part is turned ON during the maximum 576 bits from the point of time as start. When a synchronizing code is detected, transition to the synchronizing mode is realized, and when any condition of pull-out is not established, and its own address is not present, the power source of the RF part is turned OFF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery saving technique for a paging receiver, and more particularly to an improvement in an intermittent reception method for reducing power consumption of a paging receiver in a POCSAG system.

[0002]

2. Description of the Related Art For miniaturization of a portable mobile device, a battery saving technology for realizing a small battery and a long service life by reducing the power consumption of a circuit by reducing the power consumption of a circuit and realizing the battery is very important technology. It is.

At present, POCSAG (Post O.P.) has been widely used in radio paging systems in foreign countries and Japan.
ffice Code Standardization Advisory Group) method is 280 MHz band, channel interval is 25 kHz, modulation method is NRZ-FSK, signal speed is 512 b / s or 1
200 b / s, a signal system using a BCH code as an error detection / correction code. A radio paging system using this method transmits radio waves only when calling, and transmits a preamble signal followed by an address signal (corresponding to a call number) and a message signal in a specific frame. When a receiver (terminal) belongs to any frame and detects a preamble signal in the intermittent reception operation, the receiver (terminal) is configured to start an operation of capturing an address signal of the frame to which the receiver belongs.

FIG. 3 shows an example of a code structure of a transmission signal transmitted from the above-described POCSAG base station. As for the transmission code, a plurality of batches (one batch is 544 bits) are transmitted following a 576-bit preamble. The batch is composed of a leading sync code (SC) of 32 bits, followed by eight frames (64 bits), and one of the frames is assigned as its own frame. The frame is two 32bi
t Code word (CW), that is, two address signals or message signals or idle signals.

FIG. 4 is a block diagram of a radio paging receiver to which the present invention is applied. In the figure, reference numeral 1 denotes an antenna, 2 denotes a radio demodulation unit (RF unit) which includes an LNA (low noise amplifier) and a demodulation unit and outputs demodulated data a, 3 denotes a logic unit, 4 denotes a battery, and 5 denotes an RF unit 2. Turn on the power supply /
RF is turned on / off by the off control signal b.
An RF unit power control unit that causes the unit 2 to perform intermittent reception operation, 6 a logic unit power control unit, 7 a decoder unit, and 8 a central processing unit (CPU) that controls the operation of the receiver.

FIG. 5 shows a decoder section 7 of the receiver shown in FIG.
3 is a detailed block diagram of the present invention, and is a main part to which the present invention is applied. In the figure, 12 is a bit synchronization correction unit, 13 is a preamble detection unit, 14 is a synchronization code detection unit, 15 is a codeword reception unit, 16 is an address a to n comparison unit, 17 is an own address determination unit, and 18 is all 0 'detector, 19 is all' 1 'detector, 20 is a BCH error detector, 21 is a reception data buffer, 22 is a mode determination unit, and 23 is an intermittent reception timing generator.

The demodulated data a output from the RF unit 2 is
After passing through the bit synchronization correction unit 12, a preamble detection unit 13, a synchronization code detection unit 14, and a code word reception unit 15
, And a preamble detection mode by an enable control signal from the intermittent reception timing generator 23.
In the three modes of the synchronous code detection mode and the synchronous mode, each of them becomes an operation state or a non-operation state.

When a preamble is detected in the preamble detection mode, the mode transits to a synchronous code detection mode,
When the synchronization code is detected, the mode transits to the synchronization mode and the codeword receiving unit 15 starts operating. The demodulated data input to the codeword receiving unit 15 includes addresses a, b,
.., N comparing unit 16 and own address judging unit 17 judge whether the address is the own address, and all '0' detecting units 18 and all '1' detecting units 19 continue monitoring, and Make a detection. When the determination of the own address is notified to the BCH error detection unit 20, the 32-bit codeword (CW) received by the codeword reception unit 15 is detected by the BCH error detection unit 20 to detect a BCH error, If the error is equal to or less than the number, it is stored in the reception data buffer 21 as reception data addressed to the own station.

The detection information of each detection section and the result of the determination section are sent to a mode determination section 22 to determine the mode. The mode signal indicating the mode determination result is sent to the intermittent reception timing generation unit 23, and the power is turned on / off to the RF unit power control unit 5 at a timing based on the mode signal.
The F signal b is output to control intermittent reception by turning on / off the power of the RF unit 2, and at the same time, the preamble detection unit 13, the synchronization code detection unit 14, and the codeword reception unit 1
5 to control the operation / non-operation by providing an enable control signal.

FIGS. 6 and 7 are time charts for explaining the intermittent reception operation of the receiver, and are explanatory diagrams of a signal detection mode in which the RF unit 2 performs the intermittent reception operation. 6 (A) and 7 (A) show a transmission code, and FIG. 6 (B) shows a preamble detection mode. The preamble detector 13 performs a 16-bit intermittent reception operation in a 544-bit cycle until a preamble is detected. . FIG. 6C shows a synchronization code (SC) detection mode after the detection of the preamble. When the preamble is detected, the synchronization code detection unit 14 detects the synchronization code over a maximum of 576 bits after the end of the preamble. This example shows a state in which the mode returns to the preamble detection mode again without detecting a synchronization code.

FIG. 7 (D) is a time chart showing an example in which a synchronous code is detected and a transition is made to a synchronous mode when synchronization is achieved. When synchronization is established, an enable control signal is provided to the codeword receiving unit 15 of FIG. 5 to receive demodulated data. Whether the received content is the address of the own frame is compared by the address a to n comparing unit 16, the result is judged by the own address judging unit 17, and when it is judged that it is addressed to the own frame, the BCH error detecting unit 20 That fact is notified, and an error in the output of the codeword receiving unit 15 is detected. If the error is 2 bits or less, it is stored in the reception data buffer 21 as reception data addressed to the own station. FIG. 7D shows that the power of the RF unit 2 is immediately turned off when it is determined that each of the two codewords (CW) of 32 bits of the own frame, for example, the first 10 bits is not an address addressed to the own station. In this example, the reception is interrupted.

In such a conventional paging receiver of the POCSAG system, there are the following two methods (intermittent reception method) as means for determining whether to maintain or lose synchronization in the synchronization mode after synchronization has been established. [I] means for continuously monitoring the detection / non-detection of the synchronization code while detecting the data of the own frame in the synchronous mode; [II] BCH error of the code word of the own frame without detecting the synchronous code in the synchronous mode Means for judging synchronization by non-detection / detection of these two methods. Both of these means intermittently receive only a necessary data stream to reduce battery power consumption.

FIG. 8 is a flowchart of the conventional intermittent reception operation, and shows a method of continuing the detection of the synchronization code as the means for determining whether to maintain or lose synchronization after the establishment of the synchronization [I].
In the figure, 31 to 39 are step numbers. Step 31 is a preamble detection mode, and the intermittent reception of the preamble detection mode in FIG. 6B is continued until the preamble detection unit 13 detects a preamble signal (step 32). When the preamble is detected, the mode shifts to the synchronous code detection mode in step 33 according to the judgment of the mode judging unit 22, and the synchronous code detecting unit 14 searches for a synchronous code up to 576 bits after the end of the preamble. However, if no synchronization code is detected during that time, the process returns to the preamble detection mode again as shown in FIG. 6C (step 35). If the synchronization code is detected before 576 bits, the mode is shifted to the synchronization mode in step 36 by the judgment of the mode judgment unit 22. Step 3
Numerals 7, 38 and 39 are means for judging whether to maintain or lose synchronization after the synchronization is established. In step 37, detection of the synchronization code is continued.

FIG. 9 is a flowchart of a conventional intermittent reception operation, and shows a method of continuing detection of a BCH error in a code word of its own frame as means for determining the maintenance / loss of synchronization after the establishment of the synchronization in [II]. In the figure, step 3
Steps 31 to 35 leading to the synchronous mode 6 are the same as those in FIG. The step in the synchronous mode is the synchronous code detection in step 37 in FIG. Instead, in step 40, the detection of the BCH error of the own frame is continued, and the determination of the maintenance / loss of synchronization is performed.

[0015]

In the case of the above [I],
Since the BCH error detection of the code word of the own frame is not used as the means for determining the loss of synchronization after the synchronization is established,
At the time of receiving the own frame, if it is determined that the data is not addressed to the own station, the power of the RF unit can be turned off in the middle of the code word of the own frame to interrupt the reception, but it is necessary to continue detecting the synchronization code. .

In the case of [II], since the BCH error detection of the code word of the own frame is used as the out-of-synchronization determining means after the synchronization is established without detecting the synchronization code, Even if it can be determined that the data is not addressed to the own station, the reception cannot be interrupted, and it is necessary to continue error detection for all two codewords (32 bits) of the own frame.

That is, in both the cases [I] and [II], there is still room for measures as to the rate of intermittent reception for reducing power consumption (battery saving).

An object of the present invention is to solve the problem of "consumption of power for continuing to detect a synchronization code even after synchronization is established" in the case of the conventional [I], and the problem of "addressing to the own station" in the case of [II]. Power consumption for receiving all 32 bits of the code word of the own frame, even if it is not data, and testing for errors ", the ratio of intermittent reception rather than [I] and [II] It is an object of the present invention to provide a radio paging receiver with reduced power consumption.

[0019]

According to the radio call receiver of the present invention, a POCSAG system in which a signal modulated by a code configuration in which a batch consisting of a synchronization code and a plurality of frames is transmitted a plurality of times after a preamble is transmitted. A radio demodulation unit that receives and demodulates the radio signal and outputs demodulated data; and a preamble detection mode, a synchronization code detection mode, and a synchronization mode that receive the demodulated data as input and are set according to the code configuration of the demodulated data. A decoder section for outputting a radio demodulation section power on / off signal for causing the radio demodulation section to perform an intermittent reception operation in any one of the intermittent reception modes and outputting reception data addressed to its own station; A radio demodulation unit power control unit for turning on / off the power of the radio demodulation unit in accordance with an off signal and performing an intermittent reception operation; A mode determination unit that determines and outputs a mode signal that specifies any of the preamble detection mode, the synchronization code detection mode, and the intermittent reception mode of the synchronization mode by a detection signal from a detection unit corresponding to the code configuration, and Outputting a power on / off signal of the wireless demodulation unit according to the mode signal, and performing first, second and third enable control on a detection unit corresponding to the code configuration in response to the mode signal, respectively. An intermittent reception timing generator for outputting a signal; a preamble detector for detecting a preamble from the demodulated data by the first enable control signal; and a second enable control signal for detecting the preamble from the demodulated data when the preamble is detected. A synchronization code detection unit for detecting a synchronization code, and synchronization when the synchronization code is detected. A codeword receiving unit that receives a codeword of the own frame of the plurality of frames from the demodulated data by the third enable control signal when the codeword is set, and determines whether the received codeword is an address of the own frame Own address determining means, and when information indicating that the received codeword is the address of the own frame is output from the own address determining means,
A BCH error detection unit that monitors a CH error and outputs the data as reception data addressed to the own station when a BCH error is not detected. The radio demodulation unit performs an intermittent reception operation of the preamble detection mode by reset, and detects a preamble. When the preamble detection is completed, the intermittent reception operation of the synchronization code detection mode is performed, and when the synchronization code is detected and the synchronization is established, the radio paging receiver is configured to perform the intermittent reception operation of the synchronization mode. The intermittent reception timing generation section sets the synchronization mode after the synchronization is established, deactivates the operation of the synchronization code detection section, and stops the operation during the code word reception operation by the code word reception section and the own address determination means. The operation of the radio demodulation unit is immediately performed when it is determined that the synchronization is not the frame address but the synchronization loss. The is characterized in that it has configured to output the radio demodulating portion power on / off signal for stopping.

[0020]

FIG. 1 is a flowchart for explaining the operation of the present invention. In the figure, reference numerals 31 to 39 denote step numbers, and the same steps as those in the conventional flowcharts of FIGS. 8 and 9 are denoted by the same step numbers. In the present invention shown in FIG. 1, there is no step 37 (synchronous code detection?) In FIG. 8 and step 40 (BCH error detection of own frame) in FIG.

FIG. 2 is a time chart showing the intermittent receiving operation of the receiver according to the present invention, and shows a comparison between the present invention and the conventional intermittent receiving operation in the synchronous mode. (A) is a transmission code, (B) is a reception operation of the present invention, (C) is a reception operation for continuing detection of the synchronization code of the conventional [I], and (D) is all bits of the own frame of the conventional [II]. And (E) shows a mode transition.

The operation of the present invention will be described in detail with reference to FIGS. 1, 2, 5 and 6. As shown in FIG. 1, the reset causes the preamble detection mode (step 3).
In 1), the decoding operation is started. When the determination information that the mode has shifted to the preamble detection mode is sent from the mode determination unit 22 to the intermittent reception timing generation unit 23, the time is started and the intermittent reception timing generation unit 2 is started.
544 as shown in FIG.
In a bit cycle, for example, for 16 bits, a power ON / OFF signal b for turning on the reception is output to the RF unit power control unit 5, and the power of the RF unit 2 is turned ON / OFF. At the same time, an enable signal is sent to the preamble detector 13, and the preamble detector 13 performs a preamble detection operation (step 32). If the preamble is not detected during reception of 16 bits, the mode remains in the preamble detection mode 31 and the preamble detection operation is continued at the timing shown in FIG.

Next, when the preamble is detected, as shown in FIG. 6 (C), the process shifts to the synchronous code detection mode of step 33 after the end of the preamble. FIG.
(C) is a time chart when a synchronous code cannot be detected in the synchronous code detection mode. Mode determination unit 2
2, when the mode information indicating that the mode has shifted to the synchronous code detection mode is notified to the intermittent reception timing generation unit 23, starting from that time, the internal counter of the intermittent reception timing generation unit 23 uses the internal counter of FIG. like,
Power ON / O that keeps ON for up to 576 bits
The FF signal b is output to the RF unit power control unit 5. At the same time, an enable signal is sent to the synchronization code detection unit 14, and the synchronization code detection unit 14 performs a synchronization code detection operation. FIG.
If the synchronization code cannot be detected during 576 bits as in (C), the process returns to the preamble detection mode (step 31). When a synchronization code is detected,
As described above, even in the middle of 576 bits, the mode shifts to the synchronous mode at step 36 at that time.

The conditions for the loss of synchronization in the synchronous mode are as follows in the present invention. (A) In step 38, the code word 32bi of the own frame
During t, when a preamble is detected with an error of 2 bits or less, the mode shifts to a synchronous code detection mode (step 33). (B) In step 39, the code word 32bi of the own frame
When t is all '0', the flow shifts to the preamble detection mode (step 31). (C) In step 39, the code word 32bi of the own frame
When t is all "1", the process shifts to the preamble detection mode (step 31).

As a result, the own frame is sequentially received every bit, and it is assumed that the current frame is received up to n bits.
The four conditions that the received data stream of bit (a) differs from the preamble by 3 bits or more, (b) is not all '0', (c) is not all '1', and (d) differs from the own address by 3 bit or more Are satisfied, even if all 32 bits have not been received, it is determined at this point that synchronization is not lost (the conditions (a) to (c) are not met) and that the address is not its own address. Then, the receiving operation is interrupted by turning off the power supply of No. 2 and the operation in the synchronous mode is continued as it is.

When any one of the above four conditions (a) to (d) is not satisfied, the receiving operation for each bit is continued. The determination of (a) is performed by the preamble detection unit 13,
The determination of (b) is performed by all '0' detectors 18, the determination of (c) is performed by all '1' detectors 19, and the determination of (d) is performed for addresses a to
This is performed by the n comparison unit 16 and the own address determination unit 17.

When receiving 32 bits without interrupting reception,
Either the out-of-synchronization conditions (a) to (c) are satisfied or the own address.
The BCH error is tested by the CH error detection unit 20, and if the error is 2 bits or less, the error is passed to the reception data buffer 21 as reception data.

As described above, the out-of-synchronization condition in the present invention does not include neither the detection of the synchronization code nor the detection of the BCH error of the own frame codeword. Also,
The BCH error detector detects the BCH only in the case of detecting the BCH error of the own address, and does not use it for the condition of loss of synchronization.

As a result, as shown in FIG. 2B, in the synchronous mode, the synchronous code detecting operation is not performed, and only the own frame receiving operation is performed.
When it is determined that the receiving operation is unnecessary, the receiving operation can be interrupted.

According to the present invention, in the synchronization mode after the synchronization is established, the synchronization is not lost unless the data is either all '0', all '1' or the preamble. However, the preamble is detected without fail. After the completion of one data, when receiving the next data, the synchronization can be reliably performed. Even after the synchronization is established, the conventional system in which the synchronization is lost due to the detection of the synchronization code or the BCH error is not performed in the system in which the synchronization code is not re-pulled until the preamble is detected. No less.

[0031]

By implementing the present invention, after the synchronization is established, no synchronization code is received, and even when the own frame is not called even if the own frame is received, 32.
It is possible to turn off the reception halfway without receiving all the bits.
Power consumption can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the present invention.

FIG. 3 shows a code configuration of the POCSAG system.

FIG. 4 is a block diagram of a paging receiver to which the present invention is applied.

FIG. 5 is a detailed block diagram of a main decoder section to which the present invention is applied.

FIG. 6 is a time chart for explaining an intermittent reception operation of the radio pager.

FIG. 7 is an explanatory diagram of a mode of a receiving operation of the receiver.

FIG. 8 is a flowchart of a conventional intermittent reception operation.

FIG. 9 is a flowchart of a conventional intermittent reception operation.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 RF section 3 logic section 4 battery 5 RF section power control section 6 logic section power control section 7 decoder section 8 CPU 12 bit synchronization correction section 13 preamble detection section 14 synchronization code detection section 15 codeword reception section 16 address comparison section 17 Own address determination unit 18 All 0 'detection unit 19 All 1' detection unit 20 BCH error detection unit 21 Receive data buffer 22 Mode determination unit 23 Intermittent reception timing generation unit 31-40 Step number

Claims (1)

[Claims] 1. A POCSAG wireless signal, in which a signal modulated by a code configuration in which a batch consisting of a synchronization code and a plurality of frames is transmitted a plurality of times following a preamble is received and demodulated, and demodulated data is output. A wireless demodulation unit that receives the demodulated data as input and intermittently intermittently operates the radio demodulation unit in an intermittent reception mode of any of a preamble detection mode, a synchronization code detection mode, and a synchronization mode set according to the code configuration of the demodulation data. A decoder for outputting a power on / off signal of a radio demodulation unit for receiving operation and outputting reception data addressed to the own station; and turning on / off the power of the radio demodulation unit in accordance with the power on / off signal of the radio demodulation unit. And a radio demodulation unit power control unit for performing an intermittent reception operation, and wherein the decoder unit performs detection from a detection unit according to the code configuration. A mode determination unit that determines and outputs a mode signal designating any one of the intermittent reception mode of the preamble detection mode, the synchronization code detection mode, and the synchronization mode, and a power supply of the radio demodulation unit according to the mode signal. An intermittent reception timing generator that outputs an on / off signal and outputs first, second, and third enable control signals to a detector corresponding to the code configuration in response to the mode signal; A preamble detection unit that detects a preamble from the demodulated data by a first enable control signal; and a synchronization code detection unit that detects a synchronization code from the demodulated data by the second enable control signal when the preamble is detected.
When the synchronization code is detected and synchronization is established, the third
A code word receiving unit for receiving a code word of the own frame of the plurality of frames from the demodulated data by the enable control signal, and own address determining means for determining whether the received code word is an address of the own frame. When information indicating that the received codeword is the address of the own frame is output from the own address determination means, the BCH of the output of the codeword receiving unit is output.
A BCH error detection unit that monitors an error and outputs the data as reception data addressed to the own station when a BCH error is not detected. The radio demodulation unit performs an intermittent reception operation of the preamble detection mode by reset, and detects a preamble. After the end of the preamble detection, performs the intermittent reception operation of the synchronization code detection mode, in the radio paging receiver configured to perform the intermittent reception operation of the synchronization mode when the synchronization is established by detecting the synchronization code, The intermittent reception timing generation section sets the synchronization mode after the establishment of synchronization to disable the operation of the synchronization code detection section, and to control the own frame during the codeword reception operation by the codeword reception section and the own address determination means. The operation of the radio demodulation unit immediately when it is determined that the Radio paging receiver characterized by being configured to output the radio demodulating portion power on / off signal for stopping.