JP2773583B2 - Automatic adjustment of bit rate detection rate of selective call receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically adjusting a bit rate detection rate of a selective call receiver, and more particularly to an automatic adjustment method of a bit rate detection rate of a selective call receiver having a battery saving circuit and receiving and processing a selective call signal. The present invention relates to a method for automatically adjusting a bit rate detection rate of a selective calling receiver.

[0002]

2. Description of the Related Art Various types of selective paging receivers are provided, and a wide variety of selective paging signals are used for paging, but the basic configuration is almost the same.

FIG. 11 shows a typical example of a signal format used in a selective call receiver.

This selective calling signal is described in the document "STANDA".
RD MESSAGE FORMATS FOR DI
GITAL RADIO PAGING "(Post
Office Code Standarddisati
on Advisory Group (POCSA
G), Autumn. 1980).

[0005] This POCSAG is a time-division system in which the selective calling receiver turns on the receiving circuit only in the time slot group to which it belongs, and turns off the receiving circuit in other time zones. And reduce current consumption.

In the POCSAG format, since there is only one preamble signal in one batch stream,
If the electric field is weakened due to fading or the like and synchronization is lost during signal reception, subsequent data cannot be received.

For this reason, the conventional selective call receiver has a PO
The bit rate of the received signal is detected so that the battery saving operation is canceled and the mode is shifted to the synchronous signal search mode so that the synchronization can be recovered even with the CSAG code other than the preamble signal that comes at the beginning of the batch stream.

[0008]

However, as the detection rate of the bit rate detection is increased, the erroneous detection rate of erroneous detection due to noise also increases, thereby lowering the battery saving efficiency and shortening the battery life. With side effects.

In addition, since the erroneous detection rate of the bit rate detection greatly varies depending on the system side (transmission system), parameters for determining the detection rate are set in advance, but cannot be changed unless the receiver is collected, so that many systems are not available. There is a problem that it is difficult to respond to the problem or to replace the system.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a bit rate detection rate automatic adjustment method for a selective calling receiver that does not exceed a certain false detection rate regardless of the system.

[0011]

An automatic bit rate detection rate adjusting method for a selective call receiver according to the present invention has a battery saving circuit, and receives the selective call signal by receiving the selective call signal. Synchronization control means for performing control for matching the synchronization state of the devices, bit rate detection means for detecting a specific bit rate of a received signal, and a failure rate of synchronization establishment by the synchronization control means suppressed to a predetermined fixed value or less. The bit rate detection rate control means for controlling the detection rate of the bit rate detection means as described above.

Further, in the automatic bit rate detection rate adjusting method for a selective call receiver according to the present invention, the detection rate control by the bit rate detection rate control means may include a false detection rate set with a certain width based on an operation purpose. The control is performed while monitoring the erroneous detection rate so that the error detection rate is included in the allowable range.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

The embodiment shown in FIG. 1 comprises an antenna 1, a radio unit 2 for demodulating a received signal captured by the antenna, a decoder 3 for decoding the demodulated signal and sending it to the MPU 4, a decoder for controlling the whole receiver, and (MPU) that processes and displays the information provided by
(Unit) 4 and EEPR as an external memory of the MPU 4
OM 6 and RAM 7, a function switch 8 for setting a display mode, a driver 9 for making display information output by the MPU 4 suitable for display, a speaker 10 as a display terminal, an LED (Light Emittin)
g Diode) 11, vibrator 12, and LCD
(Liquid Crystal Display) 5
In addition, the reference clock 13 and the MPU operation clock 1
4 is provided.

Next, the operation of this embodiment will be described.

The modulated signal a input via the antenna 1 is demodulated by the radio unit 2.

The radio section 2 performs an intermittent reception operation under the control of the battery saving control signal b of the decoder 3.

The MPU 4 reads out the selective call number of the own receiver set in the EEPROM 6 in advance and sets it in the decoder 3 via the address bus e.

The decoder 3 checks the selective calling number of its own receiver against the demodulated signal c demodulated by the radio section 2 and, if they match, detects the selective calling number, and outputs an interrupt signal d, an address bus e and a data bus. f (hereinafter referred to as d, e, f
Output to the MPU 4 using a PU interface.

Thereafter, error correction is performed on the data sent following the selective calling signal, and only the information bits are read using the MPU interface for each codeword shown in FIG.
Transfer to PU4.

The MPU 4 receives the detection information of the selected call number from the decoder 3 and stores it in the RAM in the MPU 4 or the external RAM 7. Thereafter, when data is continuously transmitted from the decoder, it is determined whether the data is message information or a selective call code.
It is stored in the buffer area of the AM or the external RAM 7.
The MPU 4 processes this process using the coclock signal output from the reference clock 13 as the operation clock.

If the data is a selective call code, the reception of the data is stopped at that time and the MPU operation clock 14 is started, and the data stored in the buffer is processed using the MPU operation clock 14, It is stored in the message memory area of the RAM 7 as a message (character data).

FIG. 2 is a timing chart showing the message receiving operation of the decoder 3 and the MPU 4 in FIG.

(1) In the POCSAG received signal,
This is the timing of the battery saving control signal b when there is no selective calling signal A of the own receiver.

(2) is the timing of the battery saving control signal b when the selective calling signal is addressed to the own receiver.

(3) is the timing of the interrupt signal d after receiving the selective calling signal A of the own receiver. MPU4 is
At this timing, the message data is read from the decoder 3 and stored in the buffer memory.

(4) is the oscillation timing of the MPU operation clock 14. It indicates that the clock is oscillating at the high level in the time chart. At this timing, the MPU 4 uses the MPU operation clock 14 as an operation clock, processes data in the buffer memory, and stores it in the message memory as character data.

After receiving the message signal, the MPU 4 drives the speaker 10, the LED 11 and the vibrator 12 through the driver 9 to notify the wearer of the message and to output a signal L.
The contents of the received message are displayed on CD5.

Which of the speaker 10, LED 11 and vibrator 12 to use at the time of notification is set in the EEPROM 6 in advance, and is determined by a combination of this information and the setting of the function switch 8.

The message stored in the RAM of the MPU 4 or the external RAM 7 can be displayed on the LCD 5 again by the function switch 8.

FIG. 3 is a block diagram showing a detailed configuration of the decoder 3 of the selective call receiver according to the present invention.

The bit synchronization circuit 301 includes an oscillation circuit 309
A reproduced clock signal m is generated by using the reference clock signal g and the demodulated signal c from.

The preamble / SC detection circuit 303 generates a preamble detection signal i when the demodulated signal c is sampled by the reproduced clock signal m to detect a preamble signal, and an SC detection circuit j when a subsequent SC (synchronous signal) is detected. Occurs.

The synchronization control circuit 302 is a circuit for controlling battery saving (intermittent reception). POCSA
When the G signal is not received, a battery saving operation (preamble search mode) is being performed, and a continuous reception state is received upon receiving the preamble detection signal i or the bit rate detection signal k. The synchronization state is established by the SC detection signal j, the battery saving operation (selective call code search mode) is started again, and the selective call code is received at the timing of the group to which the own receiver belongs.
Further, in response to the selective calling code coincidence detection signal o, the radio unit 2 is kept in the receiving state for receiving the subsequent message signal.

In response to an out-of-synchronization request signal q output from the BCH error correction circuit 304, the synchronization state is released and the mode shifts to the preamble search mode. Synchronization state monitor signals r and v are transmitted through MPU interface circuit 307 to M
Sent to PU4.

The selective call code detecting circuit 305 checks the selective call code at the timing of the own group signal h output from the synchronous control circuit 302, and if they match, outputs the selective call code match detection signal o to the synchronous control circuit 302 and The signal is supplied to the MPU interface circuit 307, and further output to the MPU4.

The BCH error correction circuit 304 corrects the error of the demodulated signal c at the timing of the word timing signal 1 output from the synchronization control circuit 302, and outputs the message data p
Is output to the MPU 4 through the MPU interface circuit 307.

When an uncorrectable error continues in the received code in the synchronization state for a fixed number of times, the synchronization control circuit 3
For example, an out-of-synchronization request signal q is output.

The bit rate monitoring circuit 306 compares the reproduced clock signal m with the demodulated signal c to determine the P to be received.
This is a circuit for determining whether or not the bit rate is the OCSAG signal. It is used as a start-up from a battery saving operation in a state where the POCSAG signal is not received to an operation of searching for an SC, and is used to cancel the battery saving operation other than the preamble signal.

The MPU interface circuit 307 controls the MP
A circuit that controls the signal of the U interface.
4 controls the input and output of data.

The interrupt control circuit 308 is a circuit for controlling a signal (interrupt signal d) of the MPU interface, and an interrupt request signal n output from the MPU interface circuit 307 when data to be sent to the MPU 4 or a change in state occurs. Outputs an interrupt signal to the MPU 4.

FIG. 4 shows the bit rate detection circuit 30 of FIG.
6 is a block diagram showing a detailed configuration of No. 6.

The window frame generation circuit 61 outputs the reproduced clock signal m
And a window frame signal s is generated from the reference clock signal g.

The edge position judging circuit 62 judges whether or not the changing point of the demodulated signal c is within the range of the window frame signal s, and if so, generates a judgment signal t.

The counter 63 outputs the word timing signal l
And the determination signal is counted for each word.

When receiving the edge counter value setting signal u from the MPU 4 through the MPU interface, the edge counter value setting section 65 sets the edge counter value.

The comparator 64 compares the value of the counter 63 with the value of the counter value setting section 65, and when they match, generates a bit rate detection signal f.

FIG. 5 shows the bit rate detection circuit 30 of FIG.
6 is a timing chart showing the operation of Example No. 6.

FIG. 6 is a block diagram showing a detailed configuration of the synchronization control circuit 302 of FIG.

The 32-bit bit counter 21 counts the reproduction clock signal m and generates a word timing signal 1 for determining the reference timing of one word.

The 17-word word counter 22 generates a timing of 17 words (1 batch) (see FIG. 11).

The own group comparing section 24 compares whether the value of the word counter 23 is the own group or not, and if it is the own group, generates the own group signal h at the timing of the own group.

The synchronization state control unit 23 uses the preamble detection signal i, the bit rate detection signal k, the SC (synchronization signal) detection signal j, the out-of-synchronization request signal q, and the selective calling code coincidence detection signal o as a start signal to change the synchronization state. And generates a battery saving signal b together with the own group signal h. It also outputs synchronization state monitor signals r and v to notify the MPU 4 of a change in the synchronization state via the MPU interface. FIG. 7 shows the outline of the operation state transition of the synchronization state control unit 23.

FIG. 8 is a flowchart showing the operation of the first example of the bit rate detection rate control in this embodiment.
This operation is performed under the control of the MPU 4 software.

In the normal state, the set value of the edge counter value setting circuit 65 of the bit rate detection circuit 306 in FIG.
And

The MPU 4 receives, via the MPU interface circuit 307 of FIG. 3, an event that the synchronization state monitor signal v output from the synchronization control circuit of FIG. Signal r = 0
When the synchronous monitor signal v changes from 1 to 0 without detecting SC (step S2), the erroneous detection counter is incremented by +1 (step S3).

The MPU 4 checks the value of the detection counter once every predetermined time to obtain an erroneous detection rate r (step S4).
S5) If the erroneous detection rate r exceeds the erroneous detection rate α set in advance (step S6), the edge counter set value of the edge counter value setting section 65 of the bit rate detection circuit 306 is changed from the MPU 4 to the MPU interface circuit 30.
7 (step S7), the erroneous detection rate of the bit rate detection circuit 306 is reduced, and the erroneous detection counter is reset (step S8). .

In order to suppress the erroneous detection rate and not to lower the detection rate, it is necessary to control the erroneous detection rate with a certain width.

In this case, two erroneous detection rates α and β are set in advance as widths of the above-mentioned erroneous detection rates, and α> β.

If the detection rate is equal to or less than the false detection rate β, the edge counter value to be set in the edge counter value setting circuit 65 of the bit rate detection circuit 306 is increased by one to N + 1 as shown in FIG. Is added (steps S9 and S10).

FIG. 10 is a timing chart of the operation of the decoder 3 and the MPU during the bit rate detection rate control.

FIG. 10A is a timing chart of the battery saving control signal b when the receiver incorrectly detects the bit rate due to noise when the signal to be transmitted is absent.

FIG. 10B shows the timing of the interrupt signal d. 4 illustrates a state in which an interrupt occurs due to a change in the synchronization state monitor signal v of the synchronization control circuit 302 in FIG.

FIG. 10C shows the operation timing of the MPU 4. The MPU 4 subtracts the edge counter set value of the edge counter value setting unit 65 of the bit rate detection circuit 306 of the decoder 3 at the timing of * 1 in FIG. At the timing of * 2 in FIG. 10, the control of the bit rate detection rate and the reset of the erroneous detection counter are performed.

(4) in FIG. 10 is the timing of * 2, that is, the timing of a predetermined fixed time.
4 is used.

As described above, by dynamically controlling the detection rate by giving a range to the error detection rate in the bit rate detection, a constant error detection rate can be secured in any system. .

[0068]

As described above, according to the present invention, since the conventional selective call receiver does not dynamically control the detection rate of the bit rate detection, the expected false detection rate cannot be obtained due to the difference in the system. In some cases, the battery saving efficiency is reduced and the battery life must be shortened, but if the receiver cannot be changed without changing the set value, the change rate cannot be changed. Dynamic control while monitoring with a wide range of detection rates, it is possible to maintain a constant false detection rate in any system, and it is possible to flexibly respond to changes due to system side replacement etc. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of a message receiving operation of the decoder 3 and the MPU 4 of FIG.

FIG. 3 is a block diagram showing a detailed configuration of a decoder 3 of FIG.

FIG. 4 is a block diagram illustrating a detailed configuration of a bit rate detection circuit 306 in FIG. 3;

FIG. 5 is a timing chart showing an operation of the bit rate detection circuit 306 in FIG.

FIG. 6 is a block diagram showing a detailed configuration of a synchronization control circuit 302 in FIG. 3;

7 is an explanatory diagram of an operation state transition of the synchronization state control unit 23 in FIG.

FIG. 8 is a flowchart of an operation of a first example of bit rate detection rate control according to one embodiment of the present invention.

FIG. 9 is a flowchart of an operation of a second example of the bit rate detection rate control according to one embodiment of the present invention.

FIG. 10 shows decoders 3 and M during bit rate detection rate control.
6 is a timing chart of the operation of PU4.

FIG. 11 is a diagram showing a typical POCSAG signal format of a selective call signal used for calling a selective call receiver.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 wireless unit 3 decoder 4 MPU 5 LCD 6 EEPROM 7 RAM 8 function switch 9 driver 10 speaker 11 LED 12 vibrator 13 reference clock 14 MPU operation clock

Claims (2)

(57) [Claims] 1. A synchronization control means having a battery saving circuit, performing control for matching the synchronization state of the receiver with a reception signal of a selective call receiver for receiving and processing a selective call signal, and a specific bit of the received signal. Bit rate detection means for detecting a rate, and bit rate detection rate control means for controlling a detection rate of the bit rate detection means so as to suppress a failure rate of synchronization establishment by the synchronization control means to a predetermined constant value or less. A method for automatically adjusting a bit rate detection rate of a selective call receiver, comprising: 2. The method according to claim 1, wherein the control of the detection rate by the bit rate detection rate control means is performed while monitoring the error detection rate so as to fall within an allowable range of the error rate set with a certain width based on the operation purpose. 2. A method for automatically adjusting a bit rate detection rate of a selective call receiver according to claim 1, wherein the control is performed.