JPH09247729A - Radio calling receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the period of intermittent reception depending on the propriety of a reception state without providing a detection circuit for a reception electric field strength. SOLUTION: A reception section 1 received power from a batter 6 via power switch 5 and is activated and receives a signal S1 sent by a base station via an antenna. The power switch 5 is switched on/off depending on a power supply control signal Sc. A synchronization case detection section 2 detects a synchronous code from an output signal S2 of the reception section 1 and outputs a synchronous code Ss and a signal St indicating a timing of the synchronous code. A bit error detection section 3 detects a bit error in the synchronous code Ss and outputs a signal Se denoting an error bit number. A reception power supply control section 4 receives the signal St denoting a timing of the synchronous code and the signal Se indication the member of error bits and generates the power supply control signal Sc to extend the period of the intermittent reception in response to the error bit number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio paging receiver, and more particularly to a radio paging receiver that performs intermittent reception according to a reception state to save battery power consumption.

[0002]

2. Description of the Related Art A conventional radio paging receiver controls the intermittent reception cycle in accordance with the received electric field strength, as disclosed in Japanese Patent Laid-Open No. 3-239024. That is, when a sufficient electric field strength cannot be obtained, the period of intermittent reception is lengthened to suppress wasteful power consumption of the battery.

[0003]

The conventional radio paging receiver described above requires a circuit for detecting the received electric field strength, which not only increases the circuit scale but also increases the power consumption. Have

It is an object of the present invention to provide a radio paging receiver that saves battery power consumption by controlling the intermittent reception cycle according to the quality of the reception state without providing a reception electric field strength detection circuit. It is in.

[0005]

A radio paging receiver according to the present invention detects a bit error in a received synchronization code, judges the quality of the reception state based on the number of error bits, and determines the intermittent reception according to the number of error bits. Control the cycle. Specifically, a power switch that is turned on / off according to a power control signal, a receiver that is intermittently supplied with power via the power switch, and a receiver are included in the reception signal output by the receiver. A sync code detecting section that detects a sync code that is present, a bit error detecting section that detects the number of error bits of the sync code detected by this sync code detecting section, and the intermittent reception cycle changes according to the number of error bits. And a reception power control unit that generates the power control signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the receiving unit 1 is operated by the power supply from the battery 6 which is intermittently supplied via the power switch 5, receives the signal S1 transmitted from the base station via the antenna, and demodulates it. The signal S1 is, as shown in FIG.
It is a signal in which information consisting of a synchronization code and data is continuous.

The sync code detector 2 detects the sync code included in the demodulation output signal S2 of the receiver 1, and outputs a sync code Ss and a signal St indicating the timing of the sync code. The bit error detector 3 detects a bit error of the synchronization code Ss and outputs a signal Se indicating the number of error bits.

The reception power control unit 4 receives the signal St indicating the timing of the synchronization code and the signal Se indicating the number of error bits.
Generating a power control signal Sc based on the
Send to The power switch 5 is turned on / off in response to the power control signal Sc to intermittently supply power to the receiver 1.

Next, the operation of the reception power control unit 4 will be described.

FIG. 2 shows an example of the power supply control signal Sc at the time of intermittent reception. Here, the power supply control signal Sc is "H".
When the level is set, the power switch 5 is turned on, and the receiving unit 1 is supplied with power from the battery to operate. Also,
At the “L” level, the power switch 5 is turned off and the power supply to the receiver 1 is stopped.

By the way, the reception power control unit 4 receives the signal Se.
The intermittent reception cycle is controlled according to the number of error bits indicated by. That is, the power supply control signal Sc is generated such that the intermittent reception cycle becomes longer as the number of error bits increases. For example, if the number of error bits is 10% to 20% of the total number of bits of the synchronization code, as shown in FIG.
20% to 3 as the cycle of receiving every other synchronization code
At 0%, every two cycles are set as shown in FIG. 2B, and at 30% to 40%, the cycle is made longer as shown in FIG. 2C.

In this way, when there are many error bits and correct reception is not possible, the intermittent reception interval is lengthened to suppress unnecessary power consumption of the battery.

[0014]

As described above, according to the present invention, the bit error of the sync code detected from the received signal is detected,
By controlling the intermittent reception cycle according to the occurrence status of bit errors, it is possible to perform appropriate intermittent reception and save battery power consumption without providing a circuit for detecting the received electric field strength as in the conventional example. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of the power supply control signal Sc shown in FIG.

[Explanation of symbols]

 1 receiver 2 sync code detector 3 bit error detector 4 reception power controller 5 power switch S1 receive signal Sc power control signal Se signal indicating the number of error bits Ss sync code

Claims (2)

[Claims] 1. A radio paging receiver that performs intermittent reception to save battery power consumption, detects an error bit of a synchronization code included in a received signal, and determines the error bit according to the occurrence status of the error bit. A radio paging receiver having means for controlling a reception cycle. 2. A radio paging receiver that performs intermittent reception to reduce power consumption of a battery, wherein a power switch that is turned on / off according to a power control signal and power is intermittently supplied through the power switch. A receiving unit that operates, a synchronization code detection unit that detects the synchronization code included in the reception signal output by this reception unit, and a bit error that detects the number of error bits of the synchronization code detected by this synchronization code detection unit A radio paging receiver comprising: a detection unit; and a reception power supply control unit that generates the power supply control signal so that the intermittent reception cycle changes according to the number of error bits.