JPH1188932A - Selective calling signal reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain synchronization by setting a start timing for a synchronizing signal retrieval period faster than a timing set based on a preceding frame synchronizing signal and setting an end timing for the synchronizing signal retrieval period slower than a timing setting based on a frame synchronizing signal to detect surely the frame synchronizing signal. SOLUTION: In the case that a time of 512-bit of a selective calling signal received by a timing generator in a decoder 3 is counted, a level of a signal outputted to a power amplifier 6 and an internal state storage device 7 is set to '1'. A power control circuit 6 sets an output signal to a radio wave reception circuit 2 to '1' to activate it and the internal state storage device 7 sets the decoder 3 itself to a preamble retrieval state and retrieves a preamble for a 32-bit period only from the received selective calling signal to receive a frame synchronizing signal SC succession to a preamble. The synchronizing signal SC is received, frame synchronization is established in the decoder 3 and intermittent reception is again started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selective call signal receiving method for receiving a self-frame of a received selective call signal and recognizing that the self is selected when a self-address is present therein. The present invention relates to a selective paging signal receiving method in which the influence of a bit shift is prevented.

[0002]

2. Description of the Related Art For example, a selective calling signal for calling a selective calling signal receiver such as a pager is usually POCSAG.
(PostOffice Code standardization Advisory Group)
It is transmitted and received according to a digital signal protocol called. This selective calling signal is described in the document "POCSAG wireless paging system RCR STD-42" (Radio System Development Center, formulated on November 10, 1994).

FIG. 4 shows a format of a transmission signal of the POCSAG system. In this POCSAG system, before transmitting an information signal, repetitive data of "0" and "1" of at least 576 bits at a transmission bit rate is transmitted for bit synchronization. This is called a preamble. Following this preamble, a plurality of batches are transmitted as information signals. One batch is 544 bits, and the first 32 bits of a synchronization code word SC (Synchronizatio
n Codeword) followed by the 0th to 7th of each 64 bits
Consists of eight frames.

[0004] The synchronization codeword SC is used for frame synchronization, and is, for example, data transmitted in order from the MSB to the LSB as shown in FIG. Further, each 64-bit frame is further forward and backward by 3
It is divided into two bits (called a code word). The total of eight frames is 512 bits.

[0005] The eight frames described above are frames that carry information. One or more frames carry address information, and the other portions carry other information (such as messages). The address information is for specifying a receiver to which the information is to be transmitted, and as shown in FIG. 5B, a flag bit (MSB) indicating that the first bit (MSB) is the address information. "0"), and subsequent bit numbers 2 to 19 become actual address bits. Two bits of function bits carry arbitrary information, and ten bits of BHC check bits are for error correction, and the last bit (LSB) is an even parity bit. The codeword shown in FIG. 5B is called an address codeword.

On the other hand, the selective call signal receiver has a 21-bit self address, and the lower 3 bits of the self address are represented by the frame number of the transmission signal. For example, when the lower 3 bits of the self address are "010 = 2", the receiver decodes the address codeword received in the section of the second frame of the received signal sequence. Then, when it is detected that it is its own address, it recognizes that its own receiver has been selected.

When it is necessary to transmit information other than the call, a code word having the contents shown in FIG. 5C is transmitted following the address code word. This is called a message code word. The first bit (MSB) is a flag bit ("1") indicating that the message is a message, and the following bit numbers 2 to 21 are actual message bits. After that, B for error correction
A CH check bit and an even parity bit follow.

The above-mentioned message code word is transmitted until the next address code word is transmitted or an idle code word (blank area) as shown in FIG.
Continue until is sent.

When the selective calling signal receiver is not synchronized with the received signal of the format, a power control circuit built in the receiver as shown in FIG. An operation control signal (“1” is received, “0” is sleep) is output intermittently to the radio wave reception circuit, and a transmission signal in the above-described format is intermittently received. This means that the radio receiver circuit, which consumes the most power, usually notifies the receiver of the section in which the signal should be received and processed by the operation control signal, and does not perform the operation of receiving the transmitted signal in other sections. Thereby, power consumption is reduced. Normally, intermittent reception is performed in which a signal is received for only 32 bits at 512 bit intervals.

In the selective call signal receiver, when a preamble is detected in the 32-bit reception period, bit synchronization is established. When the bit synchronization is established, the reception period is extended to 32 bits or more to search for a synchronization code word SC. When this is detected, frame synchronization is performed. Thereafter, the synchronization code word SC and a specific frame in which the data of the self address may exist (hereinafter, referred to as a self frame).
Only intermittent reception is performed to save power. This is because the unique self-address is determined for each of the receivers as described above, so that after the synchronization codeword SC is detected and the frame is synchronized, only the reception of the own frame is performed. This is because it is possible to determine the reception timing by using. As described above, the receiver performs the intermittent reception for receiving only the section of the own frame and the section of the synchronization codeword SC for monitoring the frame synchronization, thereby saving power.

By the way, in the above-mentioned receiver, even after the frame synchronization in the receiver is obtained by receiving the synchronization code word SC, in addition to the reception of the own frame in each batch, the synchronization code word SC for monitoring the synchronization is also provided.
Had to be received. Therefore, this S
The operation time of the radio wave reception circuit becomes longer only in the reception section of C,
The power saving effect was poor.

Therefore, once the frame synchronization signal SC is once received and synchronized, the frame synchronization signal S
Even if the reception timing of C arrives, as shown in FIG.
During a period until the number of arrivals of the reception timing reaches a preset number N, the receiver is controlled so as not to receive the frame synchronization signal SC (ignore the SC), thereby reducing power consumption. The self-frame is detected at each timing of the self-frame by the operation of the timing generator in the receiver so that the self-address can be received (FIG. 7), and the self-frame is not received at all for several batches. There are cases.

[0013]

However, such N
When the power saving control of ignoring the SC is performed twice, a bit shift easily occurs during the reception suspension period, and the next frame synchronization signal S
Even when the reception timing of C is reached, a situation may occur in which the synchronization signal SC cannot be detected. In addition, such a problem occurs even when the SC is not ignored at all.
There is a possibility that this may occur, and measures have been desired.

An object of the present invention is to solve such a problem and to reliably detect the frame synchronization signal SC so as to achieve frame synchronization.

[0015]

For this purpose, a first aspect of the present invention receives a frame sequence consisting of a frame synchronization signal which is periodically transmitted and a plurality of frame signals following the frame synchronization signal, and based on the reception of the frame synchronization signal. Receiving a self-frame among the plurality of frame signals, and, when a self-address is present in the self-frame, recognizing that the self is selected, and a synchronization signal search period for receiving the frame synchronization signal. And a selective call signal receiving method for receiving only the self address search period for receiving the self address, wherein the start timing of the synchronization signal search period is earlier than the timing set based on the previous frame synchronization signal. And / or the end timing of the synchronization signal search period is determined based on the frame synchronization signal. It was set to timing later than the timing that you set have. A second invention receives a frame sequence transmitted periodically and a signal sequence composed of a plurality of frame signals following the frame sequence, and based on the reception of the frame synchronization signal, identifies a self-frame in the plurality of frame signals. Receiving, when the own address is present in the own frame, recognizing that the self is selected, and receiving only one of a plurality of synchronization signal search periods for receiving the frame synchronization signal, In the selective call signal receiving method for receiving the self address search period for receiving the self address every time or once among a plurality of times, a start timing of the synchronization signal search period is set based on the previous frame synchronization signal. And / or set the end timing of the synchronization signal search period to the frame synchronization. It was set to timing later than the timing set on the basis of the issue.

[0016]

FIG. 1 is a block diagram showing an internal configuration of a selective calling signal receiver according to an embodiment of the present invention. In this receiver, a signal received by the radio wave receiving circuit 2 through the antenna 1 is sent to the decoder 3 as a digital signal.
The decoder 3 decodes the received signal according to the POCSAG protocol. The CPU 4 makes various settings of the decoder 3, receives the signal decoded by the decoder 3, and performs an appropriate process according to the content. For example, when receiving the address data of the receiver, in the case of call information, a buzzer sounds to notify that there is a call, and when there is other message information, a liquid crystal display. Processing such as displaying the information on a display or the like is performed. 5 is a crystal for generating the system clock of the decoder 3.

Reference numeral 6 denotes a power control circuit provided in the decoder 3, which sends a control signal for turning on / sleep the operation state to the radio wave receiving circuit 2 which consumes the most power. Reference numeral 7 denotes an internal state storage device provided in the decoder 3. The output of the internal state storage device 7 determines the operation content of the decoder 3 at that time.

FIG. 2 is a block diagram showing a main part inside the decoder 3. As shown in FIG. Reference numeral 8 denotes a timing generator that updates and outputs a timing signal when a reset signal (generated by turning on the power) is input, and 9 sets timing data (count value) of start and end of a frame synchronization signal (synchronization code word) SC. The timing setting device 10 compares the current timing signal of the timing generator 8 with the timing data set in the timing setting device 9, and outputs a signal for starting or ending the SC search when they match. is there. In the initial state, the SC search start timing data is set in the timing setting unit 9, the SC search end timing data is set when the SC search start is completed, and the SC start timing data is set again when the SC search ends. Thus, the SC search start timing data and the SC search end timing data are set alternately.

Next, the operation will be described. When the reset signal is generated, the decoder 3 is not synchronized with the received signal. At this time, only the timing generator 8 operates. When the timing generator 8 counts the time of 512 bits at the bit rate of the received selective call signal, the signal A output to the power control circuit 6 and the internal state detecting device 7 rises to "1". .

As a result, the power control circuit 6 switches the output signal to the radio wave receiving circuit 2 to "1" (operation ON signal). The “1” signal is output at a timing somewhat earlier than the start timing of the section to be received in consideration of the initial state (rise time) of the radio wave receiving circuit 2. When the output signal of the power control circuit 6 becomes “1” as described above, the radio wave receiving circuit 2 operates during the period of “1” to perform a process of receiving a radio wave from the antenna 1.

Further, the internal state storage device 7 sets the decoder 3 itself to the preamble search state, whereby the decoder 3 converts the received pre-call signal into a preamble of 32.
Search only for the period of the bit. When the preamble is not detected from the received signal, the above operation is repeated. As described above, until the preamble is detected, the preamble search operation of receiving a signal of only 32 bits at an interval of 512 bits is performed intermittently.

Next, when a preamble is detected from the received signal, the decoder 3 controls the power control circuit 6 to
The output signal is temporarily fixed at "1", the operation of the radio wave receiving circuit 2 is continued, and the frame synchronization signal SC following the preamble is received. When the synchronization signal SC is received, frame synchronization is established in the decoder 3 and intermittent reception is started again. After this,
Unlike the operation before the synchronization is established, when the self address search timing comes, the timing signal A from the timing generator 8 rises to “1” during that period, and the power control circuit 6 and the internal state storage device 7 operate. Then, the self address is searched for from the received signal. After the synchronization is established, the timing generator 8 generates a timing signal synchronized with the synchronization state.

In the self address search, when the output A of the timing generator 8 becomes a signal indicating the timing of the self frame, the power control circuit 6 is controlled only during the timing period to set the output signal to "1", Only during the period, the radio wave receiving circuit 2 is operated to receive the own frame in the selective calling signal, and to search for the own address in the frame. For example, as shown in FIG. 7, when the own frame is “2”, it is received only during the second frame,
During that period, it is determined whether or not the own address and the address bits in the received second frame match one by one.

If the self address is not detected in the self address search, the power control circuit 6 outputs the output signal again.
The radio wave receiving circuit 2 is switched from “1” to “0” to put it in the sleep state.
The information is received by receiving a predetermined frame, but the description is omitted because it is not related to the present invention.

Then, when a search timing of the frame synchronization signal SC is generated in the timing generator 8 thereafter,
Although the signal A does not change from "0", the internal state storage device 7 controls the inside of the decoder 3 to S by the output signal B of the comparator 10.
The power control circuit 6 is controlled to set the output signal to the C search state and output the signal during the SC search timing period.
1 "to operate the radio wave receiving circuit 2.

That is, immediately before the start timing of the SC search, the search timing signal (actually the count value) obtained by the timing generator 8 is compared with the SC search start timing data set by the timing setting unit 9 and the comparator 10. , And when they match, the SC search starts. The start timing t1 is slightly earlier than the timing t2 output from the timing generator 8 and indicating the start of the SC search (see FIG. 3).

Also, the end of the SC search is compared with the SC search end timing data set by the timing setting unit 9 by the comparator 10, and if they match, the SC search ends. This end timing t4 is a timing slightly later than the timing t3 output from the timing generator 8 and indicating the end of the SC search. Thus, the previous SC
The SC search period “t2 to t3” generated by the timing generator 8 based on the signal is extended by the timing setter 9 and the comparator 10 to the period “t1 to t4”.

As described above, after the synchronization of the decoder 3 is established by receiving the synchronization signal SC, the whole circuit operates in the synchronization state until the next synchronization signal SC is received (however, the radio wave receiving circuit 2 Operates only during the period of its own frame.) However, during this period, the bit synchronization between the received signal and the decoder 3 is shifted, and S
Before the C search start timing, the frame synchronization signal SC
May be received. For the same reason, the frame synchronization signal SC may be received after the SC search end timing generated by the timing generator 8.

As described above, the internal synchronization state of the decoder 3 may deviate from the received signal. In such a case, however, in this embodiment, the SC search period is extended back and forth. The frame synchronization signal SC can be reliably received, and the decoder 3 can be synchronized with the received latest signal SC.

The above description is based on the case where the synchronization signal SC described in FIG.
Is received, but as shown in FIG.
When the SC search is performed only once every N times (SC is ignored),
As described above, the above problem becomes remarkable. However, even in this case, by extending the SC search period determined by the previously received SC signal back and forth, a more secure SC search period can be obtained.
Search becomes possible.

The SC ignoring process is performed as follows. When the search timing of the frame synchronization signal SC is generated in the timing generator 8 based on the previously received SC signal, the signal indicating the search timing does not affect the output signal A and ignores the frame synchronization signal SC. The exponent N is input to a preset SC ignore counter (not shown), and the counter is counted at each SC search timing. When the SC ignoring counter is counted by the set number N, the SC ignoring at the time of counting N is canceled and reset to the set value N. Therefore,
The SC search operation is performed every N times of the reception timing of the signal SC. That is, the SC search operation is omitted by the number N-1 set in the SC ignore counter,
Power can be reduced by that much. Then, at the time of the SC search once every N times, the timing signal from the timing generator 8 is compared with the setting data set in the timing setting unit 9, so that the start timing of the actual SC search is advanced, and the end timing. Is slowed down. That is, t2 in FIG.
The SC search period is extended from the period of t3 to the period of t1 to t4.

[0032]

As described above, according to the present invention, the synchronization signal search period is longer than the synchronization signal search period determined based on the synchronization signal received in the previous synchronization signal search period. Even when there is a bit shift during the period, frame synchronization can be reliably achieved. This can be applied to all transmission signals (for example, the FLEX-TD system) including a plurality of information signals divided into a plurality of sections including a synchronization signal and a selective call signal transmitted periodically.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a selective calling signal receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of a decoder of the receiver.

FIG. 3 is an explanatory diagram of SC search timing of the receiver.

FIG. 4 is an explanatory diagram of a format of a transmission signal of a POCSAG protocol.

FIG. 5 is an explanatory diagram of a format of each codeword of the same protocol.

FIG. 6 is a time chart of intermittent reception.

FIG. 7 is a time chart of intermittent reception in which a power saving effect is further enhanced.

Claims (2)

[Claims] 1. A signal sequence comprising a periodically transmitted frame synchronization signal and a plurality of subsequent frame signals, and receiving a self-frame in the plurality of frame signals based on the reception of the frame synchronization signal. When a self-address is present in the self-frame, a self-selection is recognized, and a synchronization signal search period for receiving the frame synchronization signal and a self-address search period for receiving the self address In the selective call signal receiving method for receiving only the synchronization signal search period, the start timing of the synchronization signal search period is set to a timing earlier than the timing set based on the previous frame synchronization signal, and / or the synchronization signal search period Timing is later than the timing set based on the frame synchronization signal. A selective call signal receiving method characterized by being set to ringing. 2. Receiving a signal sequence consisting of a frame synchronization signal transmitted periodically and a plurality of frame signals following the frame synchronization signal, and receiving a self-frame in the plurality of frame signals based on the reception of the frame synchronization signal When the self address is present in the self frame, the self frame is recognized as being selected, and a synchronization signal search period for receiving the frame synchronization signal is received only once out of a plurality of times, and In a selective call signal receiving method for receiving a self address search period for receiving a self address every time or once among a plurality of times, a start timing of the synchronization signal search period is set based on the frame synchronization signal before that. And / or setting the end timing of the synchronization signal search period to the frame synchronization signal. A selective calling signal receiving method, wherein the timing is set later than the timing set based on the signal.