JPH08251645A - Device and method for detecting synchronism in pager - Google Patents

Abstract

PURPOSE: To reduce the power consumption of a receiver and to improve signal detection capacity. CONSTITUTION: A preamble code detecting part 21 detects a bit synchronizing preamble code at the whole timing of bit synchronizing timing, synchronizing code timing and frame timing and sends a preamble code detection signal S21 to a battery control part 24, which turns on the receiver for a prescribed time. A synchronizing code detecting part 22 detects a synchronizing code at the bit synchronizing timing and the synchronizing code timing and sends a synchronizing code detection signal S22 to the control part 24, which turns on the receiver for the prescribed period. If an error exists in received data S4 received by the receiver, the error is corrected by an error correcting part 25, output data from the error correcting part 25 are compared with user's inherent number data by a data comparing part 26, and when both data coincide with each other, the data are converted into CPU transfer data by a data processing part 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to POCSAG (Post O
Pager (pager) that receives a wireless signal such as the ffice Code Stardardization Advisory Group) system, detects the user's unique number in the wireless signal, and performs predetermined processing
The present invention relates to a synchronization detection device and a synchronization detection method thereof.

[0002]

2. Description of the Related Art Conventionally, as a technology related to a pager,
For example, some documents were described in the following documents. Reference: Japanese Unexamined Patent Publication No. 6-224827 As described in the above reference, the pager receives a radio signal transmitted from a base station by a receiver through an antenna and is included in the reception signal. After the user's unique number of the pager owner who is present is detected by the decoder and the central processing unit (hereinafter, CPU), the CP
Under the control of U, it is a device that performs a reception process such as informing the pager holder of the reception by a speaker and displaying the received data on a display device. The POCSAG code method is one of the code methods of the radio signal transmitted from the pager system. This POC
In the SAG code system, a 576-bit (bit) preamble code (also referred to as a bit code) that serves to synchronize bits is transmitted first, and then a synchronization code that synchronizes bytes is transmitted in 32 bits. Next, a plurality of frames of 64 bits are transmitted from the first frame to the eighth frame, and thereafter, a batch including a synchronization code and 8 frames is repeatedly transmitted. 1st frame to 8th in each batch
The user unique number of the pager owner is assigned to any one of the frames. Such P
In the OCSAG code wireless signal, when the transmission of the preamble code starts before the transmission of eight frames, there is no time to adapt to the new frame synchronization, and the synchronization may fail or the detection of the transmitted signal may be missed. To do. Therefore, in the conventional sync detection method, by detecting the preamble code before detecting the sync code, the receiver part which consumes a lot of power is turned on only for a necessary time, and the battery power is reasonably saved. Is adopted.

[0003]

However, the conventional pager synchronization detection apparatus and its conventional synchronization detection method have the following problems (a) and (b), and it is difficult to solve them. It was (A) In the prior art, since the preamble code is detected before the synchronization code is detected, it is necessary to turn on the receiver in a frame that does not belong to the user unique number, and the receiver still consumes unnecessary power. are doing. (B) If synchronization is lost due to noise or the like during frame transmission, the next preamble code must be transmitted.
Since the frames cannot be synchronized, it cannot adapt to the frames in between. SUMMARY OF THE INVENTION It is an object of the present invention to provide a pager synchronization detection apparatus and a synchronization detection method for the pager, which solves the problems of the above-mentioned conventional techniques and has low power consumption of a receiver and high signal detection capability.

[0004]

In order to solve the above problems, the first invention comprises a bit code for bit synchronization, a synchronization code for byte synchronization, and a plurality of frames for transmitting a user unique number. In the synchronization detecting device of the pager, which receives a wireless signal to be received by a receiver that is turned on for a predetermined time by a switch means, detects a user unique number in the received wireless signal, and performs a predetermined process. Bit code detecting means for detecting a bit code in a radio signal received by a receiver and outputting a bit code detection signal, and a sync code in the radio signal received by the receiver for outputting a sync code detection signal Synchronous code detecting means and a frame timing control signal output at a frame timing subsequent to the synchronous code by being controlled by the synchronous code detecting signal. A frame timing control means comprises. Further, when any one of the bit code detection signal, the synchronization code detection signal or the frame timing control signal is input, the switch control means controls the switch means to turn on the receiver for a predetermined time. , At the frame timing subsequent to the synchronization code controlled by the synchronization code detection signal, if there is an error in the wireless signal received by the receiver, correct it and output it; if there is no error, output the wireless signal. There are provided an error correction unit that outputs the data as it is and a data processing unit that detects the user unique number from the output signal of the error correction unit and performs a predetermined process.

In the second invention, n bi for bit synchronization is used.
A bit code consisting of t (where n is a positive integer), a synchronization code consisting of i bit (where i is a positive integer) for byte synchronization, and a total m bi for transmitting the user unique number
A radio signal composed of a plurality of frames of t (where m is a positive integer) is received by a receiver that is turned on for a predetermined time by the switch means, and the user unique number in the received radio signal. In a pager synchronization detection device that detects a bit code in a radio signal received by the receiver and outputs a bit code detection signal; A synchronous code detecting means for detecting a synchronous code in the wireless signal and outputting a synchronous code detecting signal; a first counting means for outputting a first count signal in an n bit cycle; and a first counting means in an (i + m) bit cycle. Second count means for outputting 2 count signals, and select and output the first count signal of the first count means until the synchronization code detection signal is input. And a selection unit that selects and outputs the second count signal of the second count unit when the synchronization code detection signal is input. Further, frame timing control means for outputting a frame timing control signal at a frame timing subsequent to the synchronization code under the control of the synchronization code detection signal, and the bit code detection signal, the output signal of the selection means or the frame timing. When any one of the control signals is input, switch control means for controlling the switch means to turn on the receiver for a predetermined time, and following the sync code by being controlled by the sync code detection signal At the frame timing, if there is an error in the radio signal received by the receiver, the error is corrected and output, and if there is no error, an error correction unit that outputs the radio signal as it is, and an output signal from the error correction unit Data processing means for detecting the user unique number and performing a predetermined process are provided. To have.

According to the third aspect of the invention, a wireless signal composed of a bit code for bit synchronization, a synchronization code for byte synchronization, and a plurality of frames for transmitting a user unique number is turned on by a switch means for a predetermined time. In a pager synchronization detection method for receiving a receiver by a receiver, detecting a user unique number in the received wireless signal and performing a predetermined process,
The following first to fifth processes are executed. In the first process, when the timing of bit synchronization is reached, the switch means is controlled to turn on the receiver for a predetermined time, and the bit code and the synchronization code in the radio signal received by the receiver are simultaneously detected, If neither the bit code nor the sync code is detected, the process returns to the first process and waits for the timing of the next bit sync.
In the second process, when the bit code is detected in the first process, the switch means is controlled by the detection result to turn on the receiver for a predetermined time. Third
In the processing of (1), when the synchronization code is detected in the first processing, the switch means is controlled by the detection result, and the receiver is turned on at the next subsequent frame timing and synchronization code timing. The bit code is detected at each timing. In the fourth process,
When the bit code is detected at the frame timing of the third processing, the processing returns to the second processing,
If the bit code is not detected, the user unique number in the frame in the radio signal received by the receiver is detected and a predetermined process is performed, and then the process returns to the third process to return to the next frame. Wait for the timing. Further, in the fifth process, when the bit code is detected at the synchronous code timing of the third process, the process returns to the second process, and when the bit code is not detected,
If the sync code is detected and the sync code is detected, the process returns to the third processing to wait for the next sync code timing, and if the sync code is not detected a plurality of times consecutively, the first code is detected. Then, the process returns to the step (1) and waits for the next timing for bit synchronization.

In the fourth invention, n bi for bit synchronization is used.
Bit code consisting of t and i bit for byte synchronization
And a total of m for sending the user unique number
A radio signal composed of a plurality of bits made up of bits is received by a receiver that is turned on for a predetermined time by a switch means, and a user unique number in the received radio signal is detected to perform a predetermined process. In the pager synchronization detection method, the following first to fifth processes are executed. In the first process, at the timing of bit synchronization, the switch means is controlled at an n-bit cycle to turn on the receiver for a predetermined time, and the bit code and the synchronization code in the radio signal received by the receiver are set. If they are detected at the same time and neither the bit code nor the synchronization code is detected, the process returns to the first process and waits for the timing of the next bit synchronization. In the second processing, the first
When the bit code is detected by the processing of step 1, the switch means is controlled by the detection result to turn on the receiver for a predetermined time. In the third processing, when the synchronization code is detected in the first processing, the switch means is controlled in the (i + m) bit cycle according to the detection result, and the reception is performed in the next subsequent frame timing and synchronization code timing. The machine is turned on, and the bit code is detected at each of these timings. In the fourth process, if the bit code is detected at the frame timing of the third process, the process returns to the second process, and if the bit code is not detected, it is received by the receiver. The user unique number in the frame in the radio signal is detected and a predetermined process is performed, and the process returns to the third process to wait for the next frame timing. Furthermore, in the fifth processing, at the synchronization code timing of the third processing,
When the bit code is detected, the process returns to the second process, when the bit code is not detected, the sync code is detected, and when the sync code is detected, the process goes to the third process. The process returns and waits for the next sync code timing, and if the sync code is not detected a plurality of times in succession, the process returns to the first process and waits for the next bit synchronization timing in the n-bit cycle.

[0008]

According to the first aspect of the present invention, since the pager synchronization detecting device is configured as described above, the bit code detecting means detects the radio signal in all the timings of bit synchronization, synchronization code timing and frame timing. Of the bit code for bit synchronization is detected, the bit code detection signal is sent to the switch control means, and the switch control means turns on the receiver for a predetermined time. Further, at the timing of bit synchronization and the timing of synchronization code, the synchronization code detection means detects the synchronization code in the radio signal, the synchronization code detection signal is sent to the switch control means, and the switch control means causes the receiver to operate. It is turned on for a predetermined time. If there is an error in the radio signal received by the receiver due to noise or the like while the receiver is in the ON state for a predetermined time, the error correction means corrects the error, and then the predetermined data is processed by the data processing means. Processing is performed. According to the second aspect of the present invention, until the synchronization code is detected by the synchronization code detecting means, the first
The first count signal of the counting means is selected by the selection means and sent to the switch control means, and the switch control means turns on the receiver for a predetermined time. When the sync code is detected by the sync code detecting means, the second count signal of the second counting means is selected by the selecting means and sent to the switch control means, and the switch control means turns on the receiver for a predetermined time. Becomes In this way, since the cycle of the bit synchronization timing and the cycle of the synchronization code timing are switched by the selection means, it is possible to detect the synchronization code which does not require the bit code for bit synchronization. According to the third aspect of the invention, the bit code for bit synchronization is detected in each of the first, fourth and fifth processes.
Further, in the first and fifth processes, the synchronization code is detected at the timing of bit synchronization and the synchronization code timing. According to the fourth aspect of the invention, in the first and second processes, the same process as in the third aspect of the invention is performed in an n bit cycle, and in the third to fifth processes, (i + m) bi.
The same processing as in the third aspect of the invention is performed in t cycles. Therefore,
The above problems can be solved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 2 is a schematic block diagram of a pager showing an embodiment of the present invention. This pager includes a battery 1 that supplies a power supply voltage, a power switch 2 that turns the power supply voltage of the battery 1 on and off, and a POC sent from a base station or the like.
And an antenna 3 for receiving a SAG wireless signal,
A receiver 4 is connected to the antenna 3. Receiver 4
Is a receiver main body 4a which receives the high frequency signal from the antenna 3, amplifies and demodulates it to generate reception data S4, and turns on and off the power supply voltage supplied from the battery 1 to the receiver main body 4a. And switch means 4b. The switch means 4b operates the receiver main body 4a having a large amount of power consumption only when necessary to save battery power, and is composed of elements such as transistors and gate circuits. A decoder 5 is connected to the receiver 4, the decoder 5 is connected to a CPU 7 and a DC / DC converter (hereinafter referred to as a DC / DC converter) 8, and the DC / DC converter 8 further includes the CPU 7 and a memory. 6 is connected. The decoder 5 outputs the control output signal S5 based on a predetermined logic to output the switch means 4
b is turned on and off, the data stored in the memory 6 loaded by the CPU 7 is compared with the received data S4 from the receiver body 4a, and the comparison result is notified to the CPU 7. The CPU 7 loads the data in the memory 6 into the decoder 5, controls the program of the entire pager, and receives the received data S4 sent from the decoder 5.
It has a function to perform various data processing for. D
The C / DC converter 8 has a function of converting the power supply voltage from the battery 1 into a DC voltage of a level suitable for the decoder 5, the memory 6, the CPU 7, and the like. The CPU 7 includes a display device (display) 9 and a speaker 1 as peripheral devices.
0, the vibrator 11, the light emitting element 12, etc. are connected.

In such a pager, the P
When the radio signal of the OCSAG system is sent, it is received by the receiver body 4a in the receiver 4 via the antenna 3, amplified, demodulated, and the received data S4 is sent to the decoder 5. The decoder 5 compares the user unique number stored in the memory 6 with the received data S4 from the receiver main body 4a, and notifies the CPU 7 whether or not they match.
When the user unique number stored in the memory 6 and the received data S4 match, the CPU 7 operates the speaker 10 and the vibrator 11 to emit a warning sound, display the light emitting element 12 in a lighted state, or Various control operations such as displaying received data on the display device 9 are performed.
In such a reception process, the decoder 5 outputs a control output signal S5 to turn on / off the switch means 4b in the receiver 4 according to a predetermined program or logic, as described below. As a result, the battery 1 operates so as to minimize power consumption. Figure 1
2 shows a first embodiment of the present invention, and the decoder 5 of FIG.
It is a schematic block diagram of a synchronization detection device provided inside. This synchronization detection device detects a preamble code (bit code) in the reception data S4 sent from the receiver body 4a and outputs a preamble code detection signal (bit code detection signal) S21. A preamble code detection unit 21 which is a means and a synchronization code detection unit which is a synchronization code detection means for detecting the synchronization code in the reception data S4 sent from the receiver body 4a and outputting a synchronization code detection signal S22. Part 2
And 2. The sync code detection unit 22 is connected to the preamble code detection unit 21 and also serves as a frame timing control unit 23 which is a frame timing control unit.
And the battery control unit 24, which is a switch control unit, and the preamble code detection unit 21 and the frame timing control unit 7 are connected to the battery control unit 24.

The frame timing control unit 23 outputs the sync code detection signal S2 output from the sync code detection unit 22.
2 has a function of outputting the frame timing control signal S23 to the battery control unit 24 at the frame timing subsequent to the synchronization code. The battery control unit 24 outputs the preamble code detection signal S21 output from the preamble code detection unit 21, the synchronization code detection signal S22 output from the synchronization code detection unit 22, or the frame timing control signal output from the frame timing control unit 23. When any one signal of S23 is input, the switch means 4b in the receiver 4 is turned on,
It has a function of turning off and turning on the receiver body 4a for a predetermined time. Further, this synchronization detecting device is provided with an error correction section 25 which is an error correction means which is connected to the synchronization code detection section 22 and receives the reception data S4 from the receiver 4, and the output side of the error correction section 25 is provided. , Data comparison unit 2
6 and the data processing unit 27 are connected in cascade. The error correction unit 25 is controlled by the sync code detection signal S22 output from the sync code detection unit 22, and the received data S4 sent from the receiver 4 is erroneous due to noise or the like at the frame timing subsequent to the sync code. If there is any, it has the function of performing the correction and outputting the corrected data to the data comparing section 26, and if there is no error, outputting the received data S4 as it is to the data comparing section 26. The data comparison unit 26 outputs the output data of the error correction unit 25 and the memory 6
It has a function of comparing with the user unique number data S6 stored in advance and outputting the comparison result to the data processing unit 27. When the data processing unit 27 inputs the comparison result of “match” sent from the data comparison unit 26, the CP
It has a function of converting to U transfer data (that is, converting the data into a format that the CPU 7 accepts), and sending the converted data to the CPU 7. The data comparison unit 26 and the data processing unit 27 constitute data processing means for detecting the user unique number from the output data of the error correction unit 25 and performing a predetermined process.

Next, a synchronization detecting method using the above-described pager synchronization detecting device will be described with reference to FIGS. FIG. 3 is a timing diagram of FIG. In FIG. 3, the horizontal direction represents time, and the vertical direction represents the ON / OFF state of the switch means 4b by the control output signal S5 (that is, the ON / OFF state of the receiver 4).
The “L” part means that the receiver 4 is off, and the “H” part means that the receiver 4 is on. The POCSAG code is composed of n-bit (for example, 576-bit) preamble code (bit code) and (i + m) -bit (for example, 544-bit) batch repetition. Each batch includes an i bit (for example, 32 bit) synchronization code SC and an n bit (for example, 512 bit).
t) from the first frame F0 to the eighth frame F7 (however,
Each frame is composed of 64 bits). Then, the user unique number of the pager holder is assigned to any one of the first frame F0 to the eighth frame F7. FIG. 4 is a flowchart showing a sync detecting operation in the sync detecting apparatus of FIG. Less than,
The synchronization detection method of this embodiment will be described according to each step of this flowchart.

The synchronization detection operation of FIG.
The first process consisting of 0 to 103, the second process consisting of step 102, the third process consisting of step 104, the fourth process consisting of steps 105 to 108, and the first process consisting of steps 109 to 111. It is executed by the process of 5. First, when the power supply switch 2 of FIG. 2 is turned on, the power supply voltage output from the battery 1 is supplied to each circuit in the pager and becomes ready for reception. Step 10
When the synchronization detection operation is started at 0 and the timing of bit synchronization is reached at step 101, the switch means 4b in the receiver 4 is turned on by the control output signal S5 output from the battery control unit 24, and the inside of the receiver 4 is turned on. Receiver body 4a
Turns on. When the receiver 4 is turned on, the high frequency signal from the antenna 3 is received, amplified and demodulated by the receiver 4 to generate reception data S4, and the reception data S4 is the preamble code detection unit 21 and the synchronization code detection unit. 22 and the error correction unit 25. Then, in steps 102 and 103, the preamble code detection unit 21 and the synchronization code detection unit 22 simultaneously detect the preamble code and the synchronization code. In steps 102 and 103, the preamble code is also
If no sync code is detected, the process returns to step 100 and waits for the next bit sync timing. Step 1
When the preamble code is detected by 02, the battery control unit 24 is controlled by the preamble code detection signal S21 output from the preamble code detection unit 21, and the control output signal S5 is output from the battery control unit 24 and the receiver 4 The switch means 4b therein is turned on, and the receiver 4 is turned on for a predetermined time. The ON state of the receiver 4 continues until a certain time even if the preamble code is no longer detected. When the sync code is detected in step 103, the battery control unit 2 is activated by the sync code detection signal S22 output from the sync code detection unit 22.
4, frame timing control unit 23, and error correction unit 2
5 is controlled, and the receiver 4 is turned on at the subsequent frame timing and synchronization code timing.

At step 104, it is judged whether it is the synchronization code timing or the frame timing. When the determination result is the frame timing, the frame timing control signal S23 output from the frame timing control unit 23 is sent to the battery control unit 24, and when the determination result is the synchronization code timing, the synchronization code output from the synchronization code detection unit 22. The code detection signal S22 is sent to the battery control unit 24, and the control output signal S5 output from the battery control unit 24 turns on the receiver 4. In this way, the receiver 4 is turned on by the control output signal S5 output from the battery control unit 24 regardless of the frame timing or the synchronization timing, so that the preamble codes are detected at the same time in steps 105 and 109. Done. Steps 105 and 10
In FIG. 9, when the preamble code is detected by the preamble code detector 21, the preamble code detection signal S21 is sent to the battery controller 24, and the control output signal S5 output from the battery controller 24 causes the receiver for a predetermined time. 4 is turned on. If no preamble code is detected in step 105 on the frame timing side, data processing of the user unique number in frames F0 to F7 is performed in steps 106 to 108. That is, in step 106, if the received data S4 has an error, the error correction unit 25 corrects the error, and if there is no error, the received data S4 is sent to the data comparison unit 26 as it is. The data comparison unit 26 compares the output data of the error correction unit 25 with the user unique number data S6 stored in the memory 6. If they match, the comparison result is converted into CPU transfer data by the data processing unit 27 in step 107, and step 1
It is sent to the CPU 7 at 08. When the processing at this frame timing ends, the process returns to step 104 and waits for the next synchronization code timing or frame timing.

On the other hand, if the preamble code is not detected in step 109 on the sync code timing side, the sync code is detected in steps 110 and 111. That is, it is determined in step 110 whether or not the sync code is detected, and when the sync code is not detected,
In step 111, it is determined whether or not it is detected a plurality of times (for example, twice) in succession. If the sync code is not detected twice consecutively, it is considered that the batch including the sync code SC and the eight frames F0 to F7 is completed,
Returning to step 100, the battery control unit 24 is controlled by the sync code detection signal S22, the control output signal S5 turns on the receiver 4, and waits for the next bit synchronization timing. In step 111, it is determined whether or not the synchronization code is detected twice in succession. If it is determined at least twice in succession, synchronization is lost due to noise or the like. This can be easily prevented. As described above, the first embodiment has the following advantages (i) to (iii).

(I) When the receiver 4 is in the ON state, the received data S4 received by the receiver 4 is sent to the preamble code detector 21, the sync code detector 22, and the error corrector 25. Therefore, the preamble code detector 21 always operates to try to detect the preamble code. Therefore, it is not necessary to purposely turn on the receiver 4 in a frame to which the user unique number does not belong for detecting the preamble code as in the conventional case.
The time during which the receiver 4 is in the ON state is shortened and the power consumption can be reduced. (Ii) Since the sync code detector 22 always operates to detect the sync code except at the frame timing, it is possible to directly detect the sync code even if the preamble code is not detected, and the signal detection capability is improved. To do. (iii) In steps 110 and 111 of FIG. 4, if the sync code cannot be detected twice in succession at the sync code timing after the sync code is detected, the sync code detection unit 22 considers that the batch has finished Returning to 100, since the receiver 4 is not turned on until the timing of synchronizing the next bit, the power consumption can be further reduced. In step 111 of FIG. 4, it is determined whether or not the sync code is detected twice in succession.
It may be a number of times or any other number.

Second Embodiment FIG. 5 is a schematic block diagram showing the construction of a pager synchronization detecting device according to a second embodiment of the present invention, which is common to the elements shown in FIG. 1 according to the first embodiment. Common elements are denoted by common reference numerals. In this synchronization detecting device, the synchronization detecting device of FIG. 1 is provided with a first counter 28 which is a first counting means.
A second counter 29, which is a second counting means, and a selector 30, which is a selecting means, are added. The other structure is similar to that of the first embodiment. First counter 28
Is a circuit that outputs the first count signal S28 at a cycle of n bits (for example, 576 bits), the second counter 2
Reference numeral 9 is a circuit that outputs the second count signal S29 in a cycle of (i + m) bits (for example, 544 bits). These counts 28 and 29 are composed of, for example, up counters or down counters, and their output side is connected to the input side of the selector 30. Select 30
Is switched and controlled by the sync code detection signal S22 output from the sync code detector 22
Count signal S28 or second count signal S29
It is a circuit that selects one of the above and outputs it to the battery control unit 24. The selector 30 selects and outputs the first count signal S28 until the sync code is detected, and when the sync code is detected, the second count signal S28 is selected.
It has a function of selecting and outputting 29 and giving those signals to the battery control unit 24. Next, a synchronization detection method using the above-described pager synchronization detection apparatus will be described with reference to FIG.
This will be described with reference to (a), (b) and FIG. 7. Figure 6
5A and 5B are timing charts of FIG. 5, FIG. 5A is a timing chart for detecting a sync code from a preamble code, and FIG. 5B is a timing chart for directly detecting a sync code word. FIG. This Figure 6
3A and 3B correspond to the timing chart of FIG.

FIG. 7 is a flow chart of the sync detecting operation in the sync detecting apparatus of FIG. In the flowchart of FIG. 7, steps common to those of the flowchart of FIG. 4 are denoted by common reference numerals for easy understanding. The flowchart of FIG. 7 is basically different from the flowchart of FIG. 4 in that step 201 is provided between steps 100 and 101, and in step 201, the first count signal S28 of the first counter 28 is used. 576-bit cyclic operation is performed and step 1
It is only that the step 202 is provided between 03 and 104, and in the step 202, the periodical operation of 544 bits using the second count signal S29 of the second counter 29 is performed. The synchronization detection operation of FIG. 7 includes the first process including steps 100 to 103 and step 1
Second process consisting of 02 and steps 202 and 104
The third process consisting of, the fourth process consisting of steps 105 to 108, and the fifth consisting of steps 109 to 111.
It is executed by the process of. The synchronization detection method of this embodiment will be described below with reference to the flowchart of FIG. The synchronization detection operation is started in step 100, and the process proceeds to step 201. In step 201, the select 30 selects the first count signal S28 of the first counter 28 until the sync code detector 22 detects the sync code in the received data S4, and the first count signal S28 is selected.
To the battery control unit 24. Therefore, the control output signal S5 output from the battery control unit 24 causes 576
The receiver 4 is turned on in the cycle of bit. When the receiver 4 is turned on, steps 101 to 103 detect the preamble code and the synchronization code at the same time as in the first embodiment. When the sync code is detected in step 103, the process proceeds to step 202. In step 202, the output of the selector 30 is switched by the sync code detection signal S22 output from the sync code detection unit 22, and the second count signal S29 of the second counter 29 is selected and sent to the battery control unit 24. .
Therefore, the control output signal S5 output from the battery control unit 24 turns on the receiver 4 in a cycle of 544 bits. When the receiver 4 is turned on, it is determined in step 104 whether it is the synchronization code timing or the frame timing, as in the first embodiment.
8 is performed, and step 1 is performed at the synchronization timing.
The processing of 09-111 is performed.

As described above, the second embodiment has the following advantages (a) and (b). (A) Until the synchronization code is detected, the first count signal S28 of the first counter 28 is sent to the battery control unit 24 through the selector 30, and the control output signal S
5 turns on the receiver 4 in a cycle of 576 bits. Therefore, as shown in FIG. 3, since the preamble code is 576 bits, the receiver 4 is in the ON state for the minimum necessary time, and the preamble code can be reliably detected with the minimum power consumption. (B) As shown in FIG. 6, even if the preamble code cannot be detected or the signal has no preamble code, the receiver 4 is turned on in a cycle of 576 bits, so that the synchronization code must be generated within 17 batches. Can be detected, and the signal detection capability can be further improved as compared with the first embodiment. The present invention is not limited to the above embodiment, and various modifications can be made. As a modification, for example, the following (1) to
There is something like (3).

(1) The entire configuration of the pager is not limited to that shown in FIG. 2, and it is possible to change the circuit shown in FIG. 2 by omitting an extra circuit portion or adding another functional circuit, for example. Is. (2) In FIG. 5, the first and second counters 28 and 29 are connected in parallel, and the selector 30 switches between the 576-bit cycle and the 544-bit cycle, but these may be changed to another configuration. . For example, one 576bi
A counter of t is provided, and an output signal of a cycle of 544 bits and an output signal of a cycle of 576 bits are taken out from the counter, and one of the output signals is switched and output by a selection means such as a gate circuit. Good.
By doing so, the circuit configuration becomes simple. (3) In the above embodiment, the POCSAG code of the wireless signal is composed of a preamble code of 576 bits and a batch of 544 bits, but they may be any other number of bits. In this case, these bits
The circuit configuration of FIG. 1 or 5 may be changed so that the number can be processed. Also, for the wireless signals other than the POCSAG code system, if the circuit configuration of FIG. 1 or FIG. 5 is changed so as to adapt to those systems, the above embodiment can be adapted.

[0021]

As described above in detail, according to the first aspect of the invention, the bit code detecting means outputs the bit code for bit synchronization at all timings of bit synchronization, synchronization code timing and frame timing. The synchronization code is detected and the synchronization code is detected by the synchronization code detecting means at the timing of bit synchronization and the synchronization code timing. Therefore, when the receiver is in the on state, the bit code detection means always operates to detect the bit code. It is not necessary to turn the receiver on, and the power consumption generated when the receiver is on can be reduced. Moreover, since the sync code detecting means always operates to detect the sync code except at the frame timing, it becomes possible to directly detect the sync code without the bit code, and the signal detection capability is improved. According to the second invention, the first counting means of n bit and (i
+ M) bit second counting means is used, and the selection means is used to switch the cycle of the timing for bit synchronization and the cycle of the synchronization code timing to enable the detection of the synchronization code which does not require the bit code for bit synchronization. There is.
Therefore, until the sync code is detected, n bit
Based on the first count signal of the cycle, the switch control means turns on the receiver in n bit cycles. Therefore, since the length of the bit code is n bit, by turning on the receiver to the minimum necessary amount, the bit code can be reliably detected with the minimum power consumption. Moreover, even at a signal portion where no bit code exists, the synchronization code can be detected within a predetermined number of batches, because of the n bit cycle, and the signal detection capability can be further improved.

According to the third aspect of the invention, the first to fifth processes are executed to detect the synchronization. Therefore, when the receiver is in the ON state, the first, fourth and fifth processes are performed. Since it always tries to detect the bit code in the processing of the above, it is not necessary to bother to turn on the receiver for the frame that does not belong to the user unique number to detect the bit code as in the past, and the power consumption of the receiver is reduced. The amount can be reduced. Moreover, since the sync code is always detected by the fifth process except at the frame timing of the fourth process, it becomes possible to directly detect the sync code without the bit code, and the signal detection capability can be improved. . Furthermore, after detecting the synchronization code in the first process, if the synchronization code cannot be detected a plurality of times consecutively at the synchronization code timing of the fifth process through the third process, it is considered that the batch has ended, Since the receiver is not turned on until the timing of the next bit synchronization after returning to the processing of 1, the power consumption of the receiver can be further reduced. According to the fourth invention, the first to fifth processes are executed to detect the synchronization. Therefore, until the synchronization code is detected in the first process, the receiver is turned on in the n bit cycle. It becomes a state. Therefore, since the length of the bit code is n bits, the bit code can be reliably detected with the minimum power consumption by turning on the minimum required receiver. Furthermore, the third to fifth processes are (i +
m) Since the operation is performed in a bit cycle, even at a signal portion where no bit code exists, the synchronization code can be detected within a predetermined number of batches, and the signal detection capability can be further improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a synchronization detection device showing a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a pager according to an embodiment of the present invention.

FIG. 3 is a timing diagram of FIG.

FIG. 4 is a flowchart showing a synchronization detection operation of FIG.

FIG. 5 is a schematic configuration block diagram of a synchronization detection device showing a second embodiment of the present invention.

FIG. 6 is a timing diagram of FIG.

FIG. 7 is a flowchart showing the synchronization detection operation of FIG.

[Explanation of symbols]

 1 Battery 3 Antenna 4 Receiver 4a Receiver Main Body 4b Switch Means 5 Decoder 7 CPU 21 Preamble Code Detecting Section 22 Sync Code Detecting Section 23 Frame Timing Control Section 24 Battery Control Section 25 Error Correction Section 26 Data Comparison Section 27 Data Processing Section 28 , 29 counter 30 selector 100 to 103 first processing 102 second processing 104 third processing 105 to 108 fourth processing 109 to 111 fifth processing 201 576-bit periodic operation 202 544-bit periodic operation

Claims (4)

[Claims] 1. A radio signal composed of a bit code for bit synchronization, a synchronization code for byte synchronization, and a plurality of frames for transmitting a user unique number is transmitted by a receiver which is turned on for a predetermined time by a switch means. In a synchronization detection device of a pager that receives and detects a user unique number in the received wireless signal and performs a predetermined process, a bit code detection signal by detecting a bit code in the wireless signal received by the receiver A bit code detecting means for outputting a sync code detecting means for detecting a sync code in a radio signal received by the receiver and outputting a sync code detecting signal; and the sync code controlled by the sync code detecting signal. Frame timing control means for outputting a frame timing control signal at the frame timing subsequent to When one of the sync code detection signal and the frame timing control signal is input, switch control means for controlling the switch means to turn on the receiver for a predetermined time, and the sync code detection signal At the frame timing following the controlled sync code, if there is an error in the wireless signal received by the receiver, the error is corrected and output,
If there is no error, an error correction unit that outputs the wireless signal as it is, and a data processing unit that detects the user unique number from the output signal of the error correction unit and performs a predetermined process are provided. Pager synchronization detector. 2. A bit code consisting of n bits (where n is a positive integer) for bit synchronization, a synchronization code consisting of i bits (where i is a positive integer) for byte synchronization, and a user specific A radio signal composed of a plurality of frames each having a total of m bits (m is a positive integer) for number transmission is received by a receiver that is turned on for a predetermined time by the switch means, and the received radio signal is received. In a pager synchronization detection device for detecting a user unique number in a predetermined process and outputting a bit code detection signal by detecting a bit code in a radio signal received by the receiver, A sync code detecting means for detecting a sync code in a radio signal received by the receiver and outputting a sync code detection signal; and a first counter for outputting a first count signal at an n-bit cycle. Count means, a second count means for outputting a second count signal at (i + m) bit periods, and a first count signal of the first count means is selected until the synchronization code detection signal is input. Selecting means for selecting and outputting the second count signal of the second counting means when the synchronization code detection signal is input, and a selection means which is controlled by the synchronization code detection signal and follows the synchronization code. A frame timing control means for outputting a frame timing control signal at a frame timing, and when any one of the bit code detection signal, the output signal of the selecting means or the frame timing control signal is inputted, the switch means is controlled. Switch control means for turning on the receiver for a predetermined time, and the synchronization code detection signal Ri is controlled by the frame timing subsequent to the next of the synchronization code, and outputs performs its correct any errors in the wireless signal received by the receiver,
If there is no error, an error correction unit that outputs the wireless signal as it is, and a data processing unit that detects the user unique number from the output signal of the error correction unit and performs a predetermined process are provided. Pager synchronization detector. 3. A receiver that turns on a radio signal composed of a bit code for bit synchronization, a synchronization code for byte synchronization, and a plurality of frames for transmitting a user unique number by a switch means for a predetermined time. In the pager synchronization detection method of receiving and detecting the user unique number in the received wireless signal and performing a predetermined process, when the bit synchronization timing comes, the switch means is controlled to keep the receiver for a predetermined time. If the bit code and sync code in the radio signal received by the receiver are turned on at the same time and both bit code and sync code are not detected, the process returns to the first process and the next bit sync is performed. When the bit code is detected in the first process, which waits for the timing of
If the synchronization code is detected in the second process of controlling the switch means to turn on the receiver for a predetermined time based on the detection result, and the synchronization code is detected in the first process, the switch means is turned on by the detection result. A third process of controlling, turning on the receiver at the following frame timing and synchronization code timing, and detecting the bit code at each of those timings; and at the frame timing of the third process, When the bit code is detected, the process returns to the second process,
If the bit code is not detected, the user unique number in the frame in the radio signal received by the receiver is detected and a predetermined process is performed, and then the process returns to the third process to return to the next frame. In the fourth processing for waiting for timing and the synchronization code timing of the third processing, if the bit code is detected, the process returns to the second processing, and if the bit code is not detected, the synchronization is performed. If the code is detected and the sync code is detected,
The fifth process returns to the third process and waits for the next sync code timing. If the sync code is not detected a plurality of times in succession, the process returns to the first process and waits for the next bit synchronization timing. A pager synchronization detection method characterized by executing processing and. 4. A bit code consisting of n bits (where n is a positive integer) for bit synchronization, a synchronization code consisting of i bits (where i is a positive integer) for byte synchronization, and a user specific A radio signal composed of a plurality of frames each having a total of m bits (m is a positive integer) for number transmission is received by a receiver that is turned on for a predetermined time by the switch means, and the received radio signal is received. In a pager synchronization detection method for detecting a user unique number in the pager and performing a predetermined process, when the timing of bit synchronization comes, the switch means is controlled at an n-bit cycle to turn on the receiver for a predetermined time, When the bit code and the synchronization code in the radio signal received by the receiver are detected at the same time and both the bit code and the synchronization code are not detected, the process returns to the first process and the next process is performed. A first processing waiting for bit synchronization timing, when detecting the bit code in the first process,
If the synchronization code is detected in the second process of controlling the switch means to turn on the receiver for a predetermined time based on the detection result and the synchronization code is detected in the first process, (i + m) bits are detected. A third process of controlling the switch means at a cycle, turning on the receiver at a subsequent frame timing and a synchronization code timing, and detecting the bit code at each of those timings; When the bit code is detected at the frame timing of, return to the second processing,
If the bit code is not detected, the user unique number in the frame in the radio signal received by the receiver is detected and a predetermined process is performed, and then the process returns to the third process to return to the next frame. In the fourth processing for waiting for timing and the synchronization code timing of the third processing, if the bit code is detected, the process returns to the second processing, and if the bit code is not detected, the synchronization is performed. If the code is detected and the sync code is detected,
When the process returns to the third process and waits for the next sync code timing, and the sync code is not detected a plurality of times in succession, the process returns to the first process and the timing of the next bit synchronization is performed in an n-bit cycle. A pager synchronization detection method characterized by executing a fifth process of waiting.