JPH06124319A - Logical simulation device - Google Patents

Abstract

PURPOSE:To obtain the logical simulation device which can perform efficient timing verification. CONSTITUTION:A timing check primitive granting means 7 while writing a timing verification object element name, an input signal name, etc., in a timing check primitive information storage table 8 by referring to circuit information 6 obtained from a circuit storage means 2 and a timing check value definition file 6 outputs timing check primitive added circuit information 9 with an added timing check primitive to only a timing check object element which really requires a timing check. Therefore, the number of granted timing check primitives is minimized to perform the efficient timing verification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation device for performing logic simulation of the logic circuit while verifying the timing of each element of the logic circuit.

[0002]

2. Description of the Related Art In logic circuit design, a logic simulation device is often used as a means for checking the logic operation and timing verification.

FIG. 12 is a flow chart showing the timing verification operation of the conventional logic simulation apparatus. The operation will be described below with reference to FIG.

First, in step S31, an input test pattern signal is input to an input terminal of a logic circuit which is a circuit to be simulated, and an output value corresponding to an input value of each element is calculated to execute a logic simulation of the circuit to be simulated. .

Next, based on the simulation result obtained in step S31, in step S32, timing verification is performed on input / output signals of each element of the circuit to be simulated during execution of the logic simulation. The timing verification of each element is performed by a timing check primitive that is connected to the input / output of each element and checks the input / output signal change.

Next, in step S33, if it is recognized in the timing verification of step S32 that a timing error has occurred, the process proceeds to step S34 and step S34.
At 34, an error message list for reference of the cause of the timing error, such as the type of timing error, the time at which the error occurred, the element at which the error occurred, is output. On the other hand, when it is recognized in step S33 that the timing error has not occurred, the process proceeds to step S35 without proceeding to step S34.

In step S35, it is checked whether or not the simulation of all the elements of the circuit to be simulated is completed. If there is an element for which the simulation is not completed yet, the process returns to step S31, and the simulation of all the elements is completed. Until step S31
S5 is repeated.

In this way, the timing verification is performed by the logic simulation device.

[0009]

The conventional logic simulation device verifies the timing error by adding a timing check primitive to the input / output of each element of the logic circuit.

Since the timing check primitives are uniformly attached to the respective elements of the logic circuit as described above, the timing check primitives are attached even to the elements which do not actually need to be attached with the timing check primitives. There is a problem that there is a high possibility.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a logic simulation apparatus capable of performing efficient timing verification.

[0012]

A logic simulation apparatus according to the present invention performs a logic simulation of the logic circuit while verifying the timing of each element of the logic circuit having a delay function, and between the elements forming the logic circuit. Circuit information assigning means for assigning circuit information defining the connection relationship, and timing check definition file assigning means for assigning a timing check definition file defining the content of the timing verification for each element type of the logic circuit, Recognize the timing verification target element based on the circuit information and the timing check value definition file, and add the timing check primitive for detecting the input / output signal change to the timing verification target element and output the circuit information with the timing check primitive. Timing check When there are two or more timing verification target elements of the same type that input signals under exactly the same conditions, the timing check primitive granting means includes only one timing verification target element. Test pattern signal applying means for applying a timing check primitive and applying a test pattern signal to the logic circuit, and timing verification for an element to which the timing check primitive is applied based on the test pattern signal and circuit information with the timing check primitive And a simulation executing means for performing a logic simulation of each element of the logic circuit.

[0013]

In the present invention, the timing check primitive providing means, when there are two or more timing verification target elements of the same type which input signals under exactly the same conditions,
Since the timing check primitive is added only to one timing verification target element, meaningless timing check primitive allocation to the timing verification target element is avoided.

[0014]

2 is a block diagram showing the hardware structure of a logic simulation apparatus according to an embodiment of the present invention.
As shown in the figure, the logic simulation device is a CPU
15, a computer 17 having a memory 16 and the like therein,
A keyboard 13 as an information input means to the computer 17, and a C as an information output means from the computer 17.
It comprises an RT 12 and a printer 14.

FIG. 1 is a block diagram showing the configuration of a logic simulation apparatus which is an embodiment of the present invention. As shown in the figure, the circuit information 1 describing the connection relationship between the elements forming the logic circuit in the simulated circuit is read into the circuit information storage means 2 from the outside.

An example of this logic circuit is shown in FIG. 3, where the output signal S18 of the NAND gate 18 is the D input of the D flip-flop 20 and the D input of the D flip-flop 21.
Assigned to input. Further, the output signal S19 of the NOR gate 19 is given to the T input of the D flip-flop 20 and the T input of the D flip-flop 21.

Further, the simulation condition information 3 for specifying a portion to be simulated in the logic circuit, etc.
Then, the timing check condition information 4 which defines the content of the input / output signal timing verification for each element type is given to the timing check value definition file creating means 5. The timing check value definition file creating means 5 creates a timing check value definition file 6, which will be described in detail later, based on the simulation condition information 3 and the timing check condition information 4.

The timing check primitive assigning means 7 (with an unnecessary timing check primitive erasing condition) refers to the circuit information 1 and the timing check value definition file 6 obtained from the circuit storing means 2 and stores the timing verification primitive information storage table 8. While writing the timing verification target device name, the input signal name, etc., the circuit information 9 with the timing check primitive in which the timing check primitive is added only to the timing verification target device that truly needs the timing check is output.

The timing verification execution control means 11 (for logic simulation and) performs timing verification only on an element that needs to be truly verified based on the circuit information 9 with timing check primitive and the test pattern information 10. Perform a logical simulation.

As the timing verification, for example, when the element to be verified is a flip-flop, in addition to spike check, hazard check (negative spike check), relation check (timing check between two lines) and condition check (element or circuit). Check whether the specified signal change has occurred in the two input pins of the frame).

In addition to the spike check and the hazard check, timing verification such as race check and oscillator check can be performed on the elements constituting the loop circuit.

The spike check, the hazard check, and the timing check of the race check are the functions to check the signal entering the circuit portion other than the circuit portion of interest. The oscillating check is performed for the input value during the loop. An element whose output value is inverted (NAND gate, NO
This is a function that causes an error when all the elements in the loop are in an active state in a circuit in which an odd number of R gates) exist.

FIGS. 4 and 5 are explanatory views showing a part of the description contents of the timing check value definition file 6. As shown in FIG. 4 and FIG. 5, the timing check value definition file 6 includes at least the element type of the timing verification target,
The timing error type and verification value are described. By defining the timing check value definition file 6 in this way, different types of D flip-flops DF
The timing error type and the verification value can be set independently for each of the F and RS flip-flops RSFF.

Further, as shown in FIGS. 4 and 5, if the D flip-flop DFF is defined twice in the timing check value definition file 6, as shown in FIG.
The flip-flop DFF can also be made to generate two timing check primitives 90A and 90B.

Therefore, by describing the contents of the timing check value definition file 6 as shown in FIG. 4, the timing check primitive 90A verifies the setup timing of the D flip-flop DFF, and at the same time, the timing check primitive 9
Hold check and timing verification of spike error are performed by 0B.

If the contents of the timing check value definition file 6 are described as shown in FIG. 5, the timing check primitive 9 is sent to the flip-flop DFF.
At the same time as the setup timing verification of the verification value A1 is performed by 0A, the timing check primitive 9
The setup timing verification of the verification value A2 is performed by 0B.

FIG. 7 is a flow chart showing the timing verification operation of the logic simulation apparatus shown in FIG. The operation will be described below with reference to FIG.

First, in step S1, the circuit information 1 is loaded into the circuit information storage means 2. And step S2
Then, the test pattern information 10 is fetched by the timing verification execution control means 11.

Then, in step S3, the simulation condition information 3 is loaded into the timing check value definition file creating means 5, and in step S4, the timing check condition information 4 is loaded into the timing check value definition file creating means 5.

Next, in step S5, the timing check value definition file creating means 5 uses the simulation condition information 3 and the timing check condition information 4 as shown in FIGS. The timing check value definition file 6 having the description content in which the type and the verification value are independently set is generated and output to the timing check primitive adding unit 7.

Next, in step S6, the timing check primitive adding means 7 recognizes the timing verification target element based on the circuit information 1 and the timing check value definition file 6, and uses the timing check primitive information storage table 8 to The circuit information 9 with the timing check primitive in which the timing check primitive is added to each element of the timing verification target of the logic circuit is output to the timing verification execution control means 11 excluding the elements that are determined to be unnecessary to apply the timing check primitive.

Then, the timing verification execution control means 11
At step S7, based on the circuit information 9 with the timing check primitive and the test pattern information 10,
The logic simulation is executed, and in step S8, the timing verification is executed based on the circuit information 9 with the timing check primitive and the test pattern information 10.

Then, in step S9, it is determined whether or not the logic simulation has ended.
The logic simulation of step 7 and the timing verification of step S8 are performed. If it is determined in step S9 that the logic simulation has ended, the process ends.

FIG. 8 is a flow chart showing details of the timing check primitive adding operation of the timing check primitive adding means 7 in step S6 of FIG. The operation of the timing check primitive adding means 7 will be described below with reference to FIG.

First, in step S10, one element is extracted from the circuit information 1 according to a predetermined rule.

Then, in step S11, it is determined whether or not the extraction element (element extracted in step S10) is the timing verification target element by referring to the timing verification target element type of the timing check value definition file 6. .

If it is determined in step S11 that the extraction element is not the timing verification target element, the process proceeds to step S12. In step S12, it is determined whether or not the extraction processing has been completed for all the elements. If not, step S1
Return to 0. If it is determined in step S12 that the extraction process has ended, this process ends.

When it is determined in step S11 that the element is a timing verification target element, the process proceeds to step S13.
In step S13, it is determined whether or not the same type of element is already registered in the timing check primitive information storage table 8.

If NO is determined in step S13, the process proceeds to step S14. In step S14, the element name of the extraction element, the input pin, and the input signal value are registered in the timing check primitive information storage table 8.

For example, in the circuit shown in FIG. 3, when the D flip-flop 21 is the extraction element, as shown in FIG. 9, the extraction element name (DFF21), the input pin name (D input, T input) and The signal name (S18, S19) is registered.

After step S14, in step S15, a timing check primitive is added to the extraction element which is the timing verification target element. Then, step S12
To the extraction end determination processing of.

On the other hand, if YES is determined in step S13, the process proceeds to step S16. In step S16, it is determined whether or not the signals input to the input pins of the same type of element are all the same.

For example, consider a case where the D flip-flop 20 is an extraction element and the timing check primitive information storage table 8 has the contents shown in FIG. 9 in the circuit shown in FIG. In this case, the D flip-flop 20
Is a D flip-flop 2 already registered in Table 8.
Since it is the same kind of element as 1, and the output signal S18 of the NAND gate 18 is taken in at the D input and the output signal S19 of the NOR gate 19 is taken in at the T input, that is, the same signal is input to the same input pin. , Step S1
The determination of 6 is YES.

If YES is determined in step S16,
Immediately after the registration process of step S14 and the timing check primitive adding process of step S15, the extraction end determination process of step S12 is performed. That is, when there are two or more timing verification target elements of the same type that input signals under exactly the same conditions, only the first extraction element is provided with the timing check primitive, and the subsequent extraction elements are not provided with the timing check primitive.

If NO is determined in step S16, the registration process of step S14, the timing check primitive adding process of step S15, and the step S12 are performed.
The process shifts to the extraction process end determination process.

As described above, the timing check primitive assigning means 7 assigns the timing check primitive to the element of the same type that already receives the same input signal to the same input pin even if the extraction element is the element type of the timing verification target. If so, the timing check primitive is not added to the extraction element.

For example, in the circuit shown in FIG. 3, the D flip-flop 20 and the D flip-flop 21 are the same D flip-flop and the same input signal is taken in at the same input pin. Therefore, even if the D flip-flop is a timing verification target element type, as shown in FIG.
The timing check primitive 23 is provided only to one D flip-flop 21 (or only the D flip-flop 20), and the timing check primitives 22 and 23 are provided to the D flip-flops 20 and 21, respectively, as shown in FIG. There is no such thing.

As a result, since the number of timing check primitives to be added can be suppressed to the necessary minimum by adding the timing check primitives only to the elements that really need to be added, the time required for the timing verification is also shortened. Therefore, efficient timing verification can be performed.

[0049]

As described above, according to the present invention,
When there are two or more timing verification target elements of the same type that input signals under exactly the same conditions by the timing check primitive granting means, the timing check primitive is added only to one timing verification target element. The timing check primitive is not added to the meaningful timing verification target element, and the timing verification can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a logic simulation apparatus that is an embodiment of the present invention.

FIG. 2 is a block diagram showing a hardware configuration of the logic simulation apparatus shown in FIG.

FIG. 3 is a circuit diagram for explaining the operation of the embodiment.

4 is an explanatory diagram showing a timing check value definition file shown in FIG. 1. FIG.

5 is an explanatory diagram showing a timing check value definition file shown in FIG. 1. FIG.

FIG. 6 is a circuit diagram showing the concept of a timing check primitive.

7 is a flowchart showing a timing verification operation of the logic simulation apparatus shown in FIG.

8 is a flowchart illustrating a timing check primitive adding operation of the logic simulation apparatus shown in FIG.

9 is an explanatory diagram showing a timing check primitive information storage table shown in FIG. 1. FIG.

FIG. 10 is a circuit diagram showing an effect of this embodiment.

FIG. 11 is a circuit diagram showing an effect of this embodiment.

FIG. 12 is a flowchart showing a timing verification operation of the conventional logic simulation apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 circuit information 2 circuit information storage means 3 simulation condition information 4 timing check condition information 5 timing check value definition file creation means 6 timing check value definition file 7 timing check primitive assigning means 8 timing check primitive information storage table 9 circuit with timing check primitive Information 10 Test pattern information 11 Timing verification execution control means

Claims (1)

[Claims] 1. A logic simulation apparatus for performing logic simulation of the logic circuit while verifying the timing of each element of the logic circuit having a delay function, wherein the circuit defines a connection relation between the elements forming the logic circuit. Circuit information giving means for giving information, timing check definition file giving means for giving a timing check definition file defining the contents of the timing verification for each element type of the logic circuit, the circuit information and timing check value definition Timing check primitive adding means for recognizing a timing verification target element based on a file, adding a timing check primitive for detecting a signal change of its input / output to the timing verification target element, and outputting circuit information with a timing check primitive. Equipped with When there are two or more timing verification target elements of the same type that input signals under exactly the same conditions, the timing check primitive granting means adds a timing check primitive only to one timing verification target element. A test pattern signal applying means for applying a test pattern signal to the logic circuit, and the logic while performing timing verification on the element to which the timing check primitive is applied based on the test pattern signal and circuit information with a timing check primitive. A logic simulation device further comprising a simulation executing means for performing logic simulation of each element of a circuit.