JPH06124138A - Clock adjustment system - Google Patents

Abstract

PURPOSE:To highly precisely adjust a clock in a few hardware. CONSTITUTION:One of reference clocks distributed from the output of a clock distributing LSI 1 by using a tree-shaped wiring 2 is received by one LSI terminal, and a difference between the output phase of the reference clock and the output phase of a clock generated from a clock source which is the same as the reference clock, and allowed to pass through a general distribution path is observed. Thus, the phase adjustment of the clock can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock adjustment system.

[0002]

2. Description of the Related Art Generally, in an electronic system such as a computer system, a large number of flip-flops are used, and in order to synchronize them with a reference clock, a clock pulse from an oscillator is distributed to each flip-flop.

In a high performance system, a clock adjusting means is provided in order to reduce the phase difference between the clock terminals of these flip-flops.

[0004]

On the other hand, in a large system, in addition to the reference clock, a clock having a constant phase difference (phase clock) and a cycle of an integral multiple of the frequency of the reference clock are provided. The clocks are also used at the same time, and there is a drawback that complicated hardware is required to adjust each clock with high accuracy.

The present invention has been made to solve the above drawbacks, and an object of the present invention is to provide a clock adjusting system capable of adjusting a clock with high accuracy with a small amount of hardware.

[0006]

FIG. 1 shows an explanatory view of the principle of the present invention. The clock distribution LSI 1 includes a clock output terminal 5 that outputs a clock φ that has passed through the adjustment circuit 4, and a reference clock output terminal 6 that outputs a reference clock φ 0 that does not pass through the adjustment circuit 4, and is connected to the LSI 3 on the wiring board. To be done.

The LSI 3 is provided with a distribution circuit 8 for distributing the operation clock φ to the internal flip-flop 7. The clock output terminal 5 of the clock distribution LSI 1 is the clock input terminal 9 of each LSI 3, and the reference clock output terminal 6 is LS
It is connected to the reference clock input terminal 10 of I3.

.. are provided with a selection circuit 11 for selecting the input clock φ from the clock input terminal 9 and the reference clock φ 0, and the output from the selection circuit 11 is sent to the observation output collection circuit 12. Connected.

[0009]

[Operation] The clock distribution LSI 1 has the reference clock φ0.
And the clock φ that has passed through the adjustment circuit 4 is distributed to each LSI 3, and the selection circuit 11 in the LSI 3 uses the reference clock φ 0
And the operation clock φ are selected and output to the observation output collection circuit 12.

Based on the output result to the observation output collection circuit 12, the delay amount between the clock φ and the reference clock φ0 passed through the distribution circuit 8 of the LSI 3 is measured, and the difference between them is used as the offset amount. The offset amount thus obtained is used to determine the delay amount of each LSI 3, 3 ...
A value obtained by adding the offset amount to the delay amount in the conduction path of the reference clock φ0 in each LSI 3 is added to the clock φ.
Are matched, and the phases of the respective LSIs 3, 3 ...

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 shows an embodiment of the present invention. A clock distribution LSI 1 to which a clock φ1 from a reference oscillation source (not shown) is input is mounted on the wiring board to be adjusted, and clocks are supplied to each LSI 3 on the wiring board by an adjustment circuit in the clock distribution LSI 1. 4 via.

Further, the clock distribution LSI 1 is provided with a reference clock output terminal 6 for outputting the input clock φ from the clock input terminal 9 without passing through the adjusting circuit 4, and the output from the reference clock output terminal 6 is .. are distributed to the respective LSIs 3, 3, ... Via pattern wirings 2 having a constant delay amount, with elements relating to transmission delays such as wiring lengths, more accurately, impedances and the like.

On the other hand, each LSI 3 includes a clock input terminal 9 to which the clock φ output via the adjusting circuit 4 is input, and a reference clock input terminal 10 to which the reference clock φ 0 is input. The clock φ input from 9 is, as shown in FIG. 3, generally passed through a distribution circuit 8 which is amplified by a plurality of stages of buffers 13, 13 ... And which distributes the clock φ to each flip-flop 7, 7. And input to the selection circuit 11.

Further, the reference clock φ0 is simultaneously input to the selection circuit 11, and the selection circuit 11 receives a clock input via any route by a switch (not shown), that is, a distribution circuit. Either the clock φ passing through 8 or the reference clock φ0 is output to the observation terminal 14.

The output from the observation terminal 14 of each LSI 3 is
After being collected by the observation output collecting circuit 12, the waveform shaping circuit 1
5 is input to the waveform observing means 16 such as an oscilloscope, and the delay amount of each of the two routes in each LSI 3 is measured.

To measure the delay amount, as shown by a broken line in FIG. 2, the clock from the observation output collecting circuit 12 is fed back to the clock input terminal 9 of the clock distribution LSI 1 to oscillate and to oscillate in the closed loop. A method of measuring the oscillation frequency with the frequency counter 17 can be adopted.

Therefore, in the present embodiment, a difference in delay between the reference clock φ0 inside the LSI 3 and the clock φ output via the distribution circuit 8 is obtained, and this difference is used as an offset value for the reference of each LSI 3. Clock φ0
The adjustment circuit 4 is fixed with the value calculated by adding the delay amount of the clock φ as the delay amount of the clock φ passing through the distribution circuit 8.

The reference clock φ0 is distributed via a plurality (two in the present embodiment) of the reference clock output terminals 6, but the variation in the delay amount between the reference clock output terminals 6 is taken into consideration. In order to perform more accurate adjustment, one of the reference clocks φ0 supplied from different reference clock output terminals 6 is collected in one LSI 3, and each delay amount is obtained by the selection circuit 18, The offset value is corrected using the difference as a correction value. In this method, the reference clock φ0 is applied to a plurality of clock distribution LSIs.
It is also applicable to the case of supplying by 1.

FIG. 4 shows a modification of the tree-shaped wiring 2.
In the modification shown in FIG. 4A, the tree-shaped wiring 2
Is immediately branched from the reference clock output terminal 6 of the clock distribution LSI 1, and the reference clock input terminal 10 of each LSI 3, 3, ..., Or the reference clock input terminal 1
After passing through 0, they are matched and terminated by a resistance R equal to the characteristic impedance Z0 of each wiring 2, and the reference clock φ0 is transmitted to each wiring 2, 2, ... Under the same conditions.

The terminating resistor R is, as shown in FIG. 4B, near the reference clock output terminal 6 in the clock distribution LSI 1 or as shown in FIG. 4C, the reference clock output of the printed circuit board. It is also possible to dispose on the bonding pad of the terminal 6, and in this case, the resistance value is Z0 / n, where n is the number of branches of the tree-shaped wiring 2.

Further, the tree-shaped wiring 2 is once branched from the reference clock output terminal 6 of the clock distribution LSI 1 as shown in FIG. It is also possible to make a branch after the line is pulled out by '. In this case, assuming that the number of branches of the tree-shaped wiring 2 is n and the characteristic impedance is Z0, the characteristic impedance of the thick wiring 2'is
n, and as shown in FIG. 5 (a), when the termination is made on the LSI3 side, the resistance R of Z0 is as shown in FIGS.
As shown in FIG. 5, when the termination is made on the side of the clock distribution LSI 1, a resistor R of Z0 / n is mounted.

FIG. 6 shows another modification of the wiring 2.
This modification shows a case where the wiring 2 is branched inside the clock distribution LSI 1, and each wiring 2 has a resistance value equal to the characteristic impedance Z0 of each wiring 2 from the output gate 6 ′ of the clock distribution LSI 1. Is branched through.

As described above, branching the wiring 2 inside the clock distribution LSI 1 has the following advantages. That is, in the modified example shown in FIG. 4A and FIG. 5A, it is necessary to mount an individual component (terminating resistor R) other than the LSI, and FIG. 4B, FIG.
And in the modification shown in FIGS. 5B and 5C,
It is necessary to change the resistance value of the terminating resistor R depending on the number of branches of the wiring 2. However, in this modification, these problems are solved and one output is provided as shown in FIG. 6B. The same clock distribution LSI 1 can be used even if three wirings are used for one board and two wirings 2 are used for another board, and the versatility of the LSI can be improved. You can

Further, in the above-described embodiment, the reference clock φ0 is supplied to each L from each reference clock output terminal 6 of the clock distribution LSI 1 via the tree-shaped wiring 2 pattern.
Although it is distributed to SI3, in addition to this, it is also possible to distribute by using one-stroke writing wiring 2 connection, as shown in FIG. 7A, and in this case, it occurs between each LSI 3, 3 ... The delay time difference due to the wiring 2 may be measured or calculated in advance, and the value may be used as the correction value.

Incidentally, reference numeral 19 in FIG. 7A shows a termination circuit. In this case, it is possible to measure the delay time with the substrate alone, and according to such a distribution method, it becomes possible to drive a large number of LSIs 3.

The distribution of the reference clock φ0 is shown in FIG.
As shown in FIG.
It is also possible to make a single-stroke wiring connection including the inside, and in this case, the time error caused by the branch wiring 2 can be reduced and impedance matching becomes easy.

[0027]

As is apparent from the above description, according to the present invention, it is possible to adjust the clock with high accuracy by using less system hardware.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing a distribution circuit.

FIG. 4 is a diagram showing a modified example of a branch wiring.

FIG. 5 is a diagram showing another modification of the branch wiring.

FIG. 6 is a diagram showing still another modified example of the branch wiring.

FIG. 7 is a circuit diagram showing another embodiment of the present invention, (a) is an overall circuit diagram, and (b) is a diagram showing a mounted state.

FIG. 8 is a view showing still another embodiment of the present invention, (a)
Is an overall circuit diagram, and (b) is a diagram showing a mounted state.

[Explanation of symbols]

 1 clock distribution LSI 2 wiring φ0 reference clock φ clock 3 LSI 6 reference clock output terminal 10 reference clock input terminal

Claims (8)

[Claims] 1. A reference clock (φ0) distributed from a clock distribution LSI (1) output using a tree-shaped wiring (2) is received by one LSI terminal, and the reference clock (φ0) is received.
A clock phase adjustment method that adjusts the phase of the clock (φ) by observing the output phase difference with the clock (φ) generated by the same clock source as (φ0) and passing through the general distribution path. 2. The tree-shaped wiring (2) is immediately branched from the reference clock output terminal (6) of the clock distribution LSI (1) by n branches and has a substantially equal length, and the reference clock input terminal of the LSI (3).
Connected to (10), the reference clock input terminal (10) of each LSI (3) or a resistor having the value of the characteristic impedance (Z0) of the general wiring of the board after passing through the reference clock input terminal (10). The clock adjustment method according to claim 1, wherein the clock adjustment method is matched termination. 3. The tree-shaped wiring (2) is immediately branched from the reference clock output terminal (6) of the clock distribution LSI (1) by n branches and has a substantially equal length, and the reference clock input terminal of the LSI (3).
Connected to the clock distribution LSI (1), at the reference clock output terminal (6) of the clock distribution LSI (1), in the clock distribution LSI (1) or at the L
2. The clock adjusting system according to claim 1, wherein the clock adjusting method is connected to the outside of SI (1) and is matched and terminated by a resistor having a value of 1 / n of the characteristic impedance (Z0) of the general wiring of the substrate. 4. The tree-like wiring (2) is provided with a clock distribution L.
Connected to the reference clock output terminal (6) of SI (1), the characteristic impedance is the characteristic impedance of the general wiring of the board.
4. The clock adjusting method according to claim 2, wherein the thick wiring (2 ') having a value of 1 / n of (Z0) is branched. 5. The clock distribution LSI (1) is branched via a resistor that matches the characteristic impedance of the substrate at the output point of the output gate, and is then connected to the reference clock input terminal (10) of each LSI (3). The clock adjusting method according to claim 1, wherein the clock adjusting method is connected. 6. The reference clock (φ0) is distributed from a plurality of outputs of a clock distribution LSI (1) to each LSI (3, 3, ...) And among the reference clocks (φ0) from different outputs, 1
Each of them is input to an arbitrary LSI (3), the phase difference between the reference clocks (φ0) passing through the LSI (3) is observed, and the phase difference between the outputs is corrected.
The clock adjustment method described in 2, 3, 4 or 5. 7. A clock adjustment for distributing the reference clock (φ0) to each LSI (3, 3, ...) By a single-stroked wiring (2) instead of the tree-shaped wiring (2) according to claim 1. method. 8. A clock adjustment system in which the reference clock (φ0) is distributed by a one-stroked wiring (2) including wiring inside an LSI (3) instead of the tree-shaped wiring (2) according to claim 1. .