JPH06123896A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH06123896A
JPH06123896A JP27416892A JP27416892A JPH06123896A JP H06123896 A JPH06123896 A JP H06123896A JP 27416892 A JP27416892 A JP 27416892A JP 27416892 A JP27416892 A JP 27416892A JP H06123896 A JPH06123896 A JP H06123896A
Authority
JP
Japan
Prior art keywords
thin film
video signal
film transistor
liquid crystal
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP27416892A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Nakamura
弘喜 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27416892A priority Critical patent/JPH06123896A/en
Publication of JPH06123896A publication Critical patent/JPH06123896A/en
Withdrawn legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To decrease an ON-resistance in a video signal write switching thin film transistor and to shorten a write time and to reduce the number of divisions of a video signal by connecting plural thin film transistors hydroprocessed in parallel and keeping individual channel width within the range of a specific value. CONSTITUTION:Plural display pixel parts 4 formed two-dimensionally on the same substrate are controlled by forming the drive circuit of a shift regist 1, a buffer 2 and the video signal write switching thin film transistor 3, etc., on the substrate. The switching thin film transistor is driven point-sequentially. At this time, in the video signal writing thin film transistor 3, plural thin film transistors hydroprocessed are connected in parallel, and the individual channel width is kept in 1-30mum. Then, perfect hydroprocess is performed, and the dispersion of the process is reduced. Thus, the on resistance in the video signal write thin film transistor 3 is reduced, and the write time is shortened.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は表示装置に関し、とくに
駆動回路一体型のアクティブマトリックス型液晶表示装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a drive circuit integrated active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】近年、液晶表示装置は、薄型軽量、低消
費電力という大きな利点をもつため、液晶テレビ、日本
語ワードプロセッサやディスクトップパーソナルコンピ
ュータ等のOA機器等に種々の液晶表示装置が用いられ
ている。高品質表示が可能な駆動回路一体型のアクティ
ブマトリックス型液晶表示装置もより高品質な表示特性
が要求されている。
2. Description of the Related Art In recent years, since liquid crystal display devices have the great advantages of thinness, light weight, and low power consumption, various liquid crystal display devices have been used for OA equipment such as liquid crystal televisions, Japanese word processors and desktop personal computers. ing. The active matrix type liquid crystal display device integrated with a drive circuit capable of high quality display is also required to have higher quality display characteristics.

【0003】従来の駆動回路一体型のアクティブマトリ
ックス型液晶表示装置の部分回路図を図7に示す。従来
の駆動回路一体型のアクティブマトリックス型液晶表示
装置は、多結晶シリコンからなる薄膜トランジスタを用
いてシフトレジスタ1、バッファ2、映像信号書き込み
スイッチ用薄膜トランジスタ3等の駆動回路を基板上に
形成して、同一基板上に 2次元状に形成された複数の表
示画素部4を制御するスイッチング用薄膜トランジスタ
5を点順次に駆動する構成となっている。なお、6は信
号線を、7はゲート線を、8はゲート走査線駆動回路を
表す。ここで、映像信号書き込みスイッチ用薄膜トラン
ジスタ3はチャネル幅を広く形成してオン抵抗を小さく
することにより、必要な書き込み時間内に映像信号を書
き込めるように設計される。そのチャネル幅は、通常 3
00〜400 μmであるが、チャネル幅をさらに広くすると
映像信号書き込みスイッチ用薄膜トランジスタ3のゲー
ト・ドレイン間の容量に起因する突き抜け電圧が増える
ため(SID'90 DIGEST P315)、その幅にも制限がある。
FIG. 7 shows a partial circuit diagram of a conventional active matrix type liquid crystal display device integrated with a drive circuit. In a conventional active matrix type liquid crystal display device integrated with a drive circuit, a drive circuit such as a shift register 1, a buffer 2 and a video signal write switch thin film transistor 3 is formed on a substrate by using a thin film transistor made of polycrystalline silicon. The switching thin film transistor 5 for controlling a plurality of display pixel portions 4 formed two-dimensionally on the same substrate is driven in a dot-sequential manner. In addition, 6 is a signal line, 7 is a gate line, and 8 is a gate scanning line drive circuit. Here, the thin film transistor 3 for video signal write switch is designed so that a video signal can be written within a required writing time by forming a wide channel width and reducing on-resistance. Its channel width is usually 3
Although it is 00 to 400 μm, if the channel width is made wider, the punch-through voltage due to the capacitance between the gate and drain of the thin film transistor 3 for video signal write switch increases (SID'90 DIGEST P315), so the width is also limited. is there.

【0004】一方、多結晶シリコン薄膜トランジスタ
は、液晶表示装置のコントラスト低下の原因となるトラ
ンジスター動作のオフ側でドレインリーク電流が発生し
やすい。また、多結晶シリコン薄膜の特性を向上させる
ためには移動度を上げなければならない。このため、多
結晶シリコン薄膜トランジスタは、ドレインリーク電流
を下げ、移動度を上げるために水素化処理が通常行われ
ている。この水素化処理はチャネル幅と関連し、チャネ
ル幅が広くなると水素化処理の効果が少なくなることか
ら、チャネル部にスリットを入れ、開口部を形成する方
法が開示されている(特開昭 62-268161)。
On the other hand, in the polycrystalline silicon thin film transistor, a drain leak current is apt to occur on the off side of the transistor operation which causes a decrease in contrast of the liquid crystal display device. Also, the mobility must be increased in order to improve the characteristics of the polycrystalline silicon thin film. For this reason, polycrystalline silicon thin film transistors are usually subjected to hydrogenation treatment in order to reduce drain leakage current and increase mobility. This hydrogenation treatment is related to the channel width, and since the effect of the hydrogenation treatment becomes smaller as the channel width becomes wider, there is disclosed a method of forming a slit in the channel portion to form an opening (JP-A-62-62). -268161).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、現行テ
レビ放送(NTSC)規格からハイビジョン放送規格へ
の移行や、インタレース駆動からノンインタレース駆動
化等による画像表示の高品質化が進むと映像信号書き込
みスイッチ用薄膜トランジスタ3への映像信号の書き込
み時間が短くなり、点順次駆動法の場合、書き込みが困
難となる問題がある。
However, when the current television broadcasting (NTSC) standard is changed to the high-definition broadcasting standard, and the quality of image display is improved by the interlace drive to the non-interlace drive, video signal writing is performed. There is a problem that writing time of the video signal to the switching thin film transistor 3 becomes short, and writing becomes difficult in the case of the dot sequential driving method.

【0006】映像信号書き込み時間を長くする手段とし
て、シフトレジスタおよび映像信号を分割する手段も考
えられるが、映像信号の分割は外部駆動回路の増大およ
び調整が困難である。したがって、映像信号の分割数を
少なくするか、もしくは分割なしで済むように映像信号
書き込みスイッチ用薄膜トランジスタ3のオン抵抗を低
くすることが望ましいが、前述のようにチャネル幅にも
制限があり、またチャネル部にスリットを入れ、開口部
を形成した後水素化処理を行う方法にもつぎのような問
題がある。チャネル部に狭い開口部を形成し、その開口
パターン幅をエッチィングで形成する場合、四角い開口
部の角が丸みをおびたり、また、開口部自身を形成する
ことが困難である。そのうえ、開口部の幅が狭いと活性
層端部でのゲート電極耐電圧が悪くなる。
A shift register and a means for dividing the video signal can be considered as means for lengthening the video signal writing time, but it is difficult to increase and adjust the external drive circuit for the division of the video signal. Therefore, it is desirable to reduce the number of divisions of the video signal, or to lower the on-resistance of the video signal write switch thin film transistor 3 so that the division is not necessary. However, as described above, the channel width is also limited, and The method of performing a hydrogenation process after forming a slit in a channel part and forming an opening also has the following problems. When a narrow opening is formed in the channel part and the opening pattern width is formed by etching, it is difficult to form the opening itself by rounding the corners of the square opening. In addition, if the width of the opening is narrow, the withstand voltage of the gate electrode at the end of the active layer becomes poor.

【0007】さらに、駆動回路一体型液晶表示装置を水
素化処理する場合、薄膜トランジスタのチャネル幅がシ
フトレジスタ等では狭いパターンとして、映像信号書き
込み用薄膜トランジスタやバッファ回路および保護 MOS
ダイオードの薄膜トランジスタでは広いパターンとして
存在するため、映像信号書き込み用薄膜トランジスタ等
のチャネル幅に最適な時間で水素化処理を行うと、シフ
トレジスタ等では水素化処理が過剰となり駆動回路部の
薄膜トランジスタのディプレッション現象が生じ、オフ
時のリーク電流が増え、消費電力も増え、発熱などの問
題が生じる。
Further, when a liquid crystal display device integrated with a drive circuit is subjected to a hydrogenation process, a thin film transistor thin film transistor, a buffer circuit and a protective MOS are formed as a pattern in which a channel width of a thin film transistor is narrow in a shift register or the like.
Since the thin film transistor of a diode exists as a wide pattern, if the hydrogenation process is performed for an optimal time for the channel width of the thin film transistor for video signal writing, the hydrogenation process becomes excessive in the shift register and the depletion phenomenon of the thin film transistor in the drive circuit section occurs. Occurs, leakage current at the time of off increases, power consumption also increases, and problems such as heat generation occur.

【0008】本発明は、このような課題に対処するため
になされたもので、駆動回路一体型液晶表示装置におい
て、映像信号書き込みスイッチ用薄膜トランジスタのオ
ン抵抗を下げ、書き込み時間を短くし、および映像信号
の分割数を少なくすることのできる液晶表示装置を提供
することを目的とする。
The present invention has been made to solve such a problem, and in a drive circuit integrated type liquid crystal display device, the ON resistance of a thin film transistor for a video signal writing switch is lowered, the writing time is shortened, and an image is displayed. An object of the present invention is to provide a liquid crystal display device capable of reducing the number of signal divisions.

【0009】[0009]

【課題を解決するための手段】本発明の液晶表示装置
は、基板と、この基板上に 2次元状に形成された複数の
表示画素部と、これら表示画素部をそれぞれ制御する複
数のスイッチング用薄膜トランジスタと、この薄膜トラ
ンジスタを順次駆動するための信号線走査回路およびゲ
ート線走査回路よりなる駆動回路部とを基板上に備えた
液晶表示装置において、信号線走査回路は映像信号処理
部と、この映像信号処理部からの映像信号を信号走査線
へ書き込みを行う映像信号書き込み用薄膜トランジスタ
とを備え、映像信号書き込み用薄膜トランジスタが水素
化処理されてなる複数の薄膜トランジスタを並列に接続
し、かつ並列に接続された薄膜トランジスタの個々のチ
ャネル幅が 1μm 以上30μm 以下であることを特徴とす
る。
A liquid crystal display device according to the present invention comprises a substrate, a plurality of display pixel portions formed two-dimensionally on the substrate, and a plurality of switching pixels for controlling the display pixel portions. In a liquid crystal display device including a thin film transistor and a drive circuit unit including a signal line scanning circuit and a gate line scanning circuit for sequentially driving the thin film transistor on a substrate, the signal line scanning circuit includes a video signal processing unit and a video signal processing unit. A video signal writing thin film transistor for writing a video signal from the signal processing unit to a signal scanning line is provided, and a plurality of thin film transistors formed by hydrogenating the video signal writing thin film transistor are connected in parallel, and are connected in parallel. Each thin film transistor has a channel width of 1 μm or more and 30 μm or less.

【0010】本発明の液晶表示装置において、映像信号
書き込み用薄膜トランジスタとともにチャネル幅の広い
バッファ回路および保護 MOSダイオードの薄膜トランジ
スタを個々のチャネル幅が 1μm 以上30μm 以下である
薄膜トランジスタを複数個並列に接続してもよい。
In the liquid crystal display device according to the present invention, a plurality of thin film transistors each having a channel width of 1 μm or more and 30 μm or less are connected in parallel with a thin film transistor for video signal writing, a thin film transistor of a buffer circuit and a protection MOS diode having a wide channel width. Good.

【0011】本発明の液晶表示装置は、上述の表示画素
部および駆動回路部等を備えた基板の表示画素部全体
を、対向基板と所定の間隔で合わせ、そのギャップ部に
液晶を注入し、液晶セルを構成する。そして、外装アセ
ンブリを形成して本発明の液晶表示装置を得る。
In the liquid crystal display device of the present invention, the entire display pixel portion of the substrate having the above-mentioned display pixel portion, driving circuit portion, etc. is aligned with the counter substrate at a predetermined interval, and liquid crystal is injected into the gap portion, It constitutes a liquid crystal cell. Then, the exterior assembly is formed to obtain the liquid crystal display device of the present invention.

【0012】[0012]

【作用】チャネル幅の狭い薄膜トランジスタを複数個並
列に接続することによって、水素化処理をより完全に行
うことができる。また、チャネル幅はソースおよびドレ
イン領域間で完全なストライプ状になるので、水素化処
理をバラツキなく行うことができる。
By connecting a plurality of thin film transistors having a narrow channel width in parallel, the hydrogenation process can be more completely performed. Further, since the channel width has a perfect stripe shape between the source and drain regions, the hydrogenation treatment can be performed without variation.

【0013】さらに、駆動回路部や画素部等を含めて同
一基板上に形成されている薄膜トランジスタのチャネル
幅が略同一であるので、水素化処理等を同一工程で行う
ことができる。このため、とくに、映像信号書き込みス
イッチ用薄膜トランジスタのオン抵抗を下げ、書き込み
時間を短くし、および映像信号の分割数を少なくするこ
とができる。
Furthermore, since the channel widths of the thin film transistors formed on the same substrate including the drive circuit portion and the pixel portion are substantially the same, the hydrogenation treatment and the like can be performed in the same step. Therefore, in particular, it is possible to reduce the ON resistance of the thin film transistor for video signal writing switch, shorten the writing time, and reduce the number of divisions of the video signal.

【0014】[0014]

【実施例】本発明の実施例を図1から図6に基づき説明
する。多結晶シリコン薄膜トランジスタの水素化処理前
後におけるトランジスタ特性を図4に示す。水素化処理
を行うことにより、移動度の増大、しきい値電圧が低減
すること等から、オフ時のリーク電流の低減を図ること
ができる。ここで、図4に示した多結晶シリコン薄膜ト
ランジスタはソースおよびドレイン部はn−領域を有す
るLDD(Lightly Doped Drain )構造であることが好
ましい。LDD構造はドレイン部等の近傍の電荷分布を
徐々に変化させてドレイン接合等を構成する。電荷分布
が徐々に変化するため、接合部の接合電場も徐々に変化
し異常なリーク電流が流れなくなる。多結晶シリコン薄
膜トランジスタの場合、このようなLDD構造でないと
ゲートバイアスが負の領域でリーク電流が増大し、リー
ク電流が増大すると 1ゲート走査時間内の映像信号保持
特性が確保できないためである。
Embodiments of the present invention will be described with reference to FIGS. FIG. 4 shows transistor characteristics before and after hydrogenation treatment of the polycrystalline silicon thin film transistor. By performing the hydrogenation treatment, mobility is increased, threshold voltage is reduced, and the like, so that leakage current at the time of off can be reduced. Here, the polycrystalline silicon thin film transistor shown in FIG. 4 preferably has an LDD (Lightly Doped Drain) structure in which the source and drain portions have an n − region. The LDD structure forms a drain junction or the like by gradually changing the charge distribution in the vicinity of the drain portion or the like. Since the charge distribution gradually changes, the junction electric field at the junction also gradually changes and abnormal leakage current does not flow. This is because in the case of a polycrystalline silicon thin film transistor, unless the LDD structure is used, the leak current increases in the region where the gate bias is negative, and if the leak current increases, the video signal holding characteristic within one gate scanning time cannot be secured.

【0015】図5は、多結晶シリコン薄膜トランジスタ
の水素化処理後の移動度およびしきい値電圧特性のチャ
ネル幅依存性を示したものである。図5より、多結晶シ
リコン薄膜トランジスタでは、水素化処理を同一条件下
で行うと、チャネル幅が広いものほど、水素化が不十分
で移動度が低下し、しきい値電圧も大きくなる。一方、
チャネル幅が狭すぎると、ドレイン電流が流れにくくな
り、並列に接続する薄膜トランジスタの数が多すぎるこ
とになる。このために、本発明におけるチャネル幅は、
1μm 以上30μm 以下であることが重要である。
FIG. 5 shows the channel width dependence of the mobility and threshold voltage characteristics of a polycrystalline silicon thin film transistor after hydrogenation treatment. From FIG. 5, in the polycrystalline silicon thin film transistor, when the hydrogenation treatment is performed under the same conditions, the wider the channel width is, the insufficient hydrogenation is caused, the mobility is lowered, and the threshold voltage is increased. on the other hand,
If the channel width is too narrow, it becomes difficult for the drain current to flow, and the number of thin film transistors connected in parallel will be too large. For this reason, the channel width in the present invention is
It is important that the thickness is 1 μm or more and 30 μm or less.

【0016】なお、図6は、多結晶シリコン薄膜トラン
ジスタの水素化処理を長時間行うと、水素がドナー的に
作用して、トランジスタ特性がエンハンスメント型から
ディプレッション型へ推移するようすを示したものであ
る。
Note that FIG. 6 shows that when hydrogenation treatment of a polycrystalline silicon thin film transistor is performed for a long time, hydrogen acts as a donor and the transistor characteristics change from an enhancement type to a depletion type. .

【0017】図1は、本発明の多結晶シリコン薄膜トラ
ンジスタからなる駆動回路一体型のアクティブマトリッ
クス型液晶表示装置の部分回路図である。また、図2は
映像信号書き込みスイッチ用薄膜トランジスタ3の平面
図である。図1において、シフトレジスタ1、バッファ
2、映像信号書き込みスイッチ用薄膜トランジスタ3等
の駆動回路を基板上に形成して、同一基板上に 2次元状
に形成された複数の表示画素部4を制御するスイッチン
グ用薄膜トランジスタ5を点順次に駆動する構成となっ
ている。ここで、映像信号書き込みスイッチ用薄膜トラ
ンジスタ3は複数の薄膜トランジスタを並列に接続し、
かつ並列に接続された薄膜トランジスタの個々のチャネ
ル幅を約 8μm で形成した。そして、この薄膜トランジ
スタを 40 個並列に接続することにより、映像信号書き
込みスイッチ用薄膜トランジスタ3において、映像信号
書き込み時にオン抵抗 500Ω以下が達成できた。
FIG. 1 is a partial circuit diagram of an active matrix type liquid crystal display device integrated with a drive circuit, which is composed of a polycrystalline silicon thin film transistor according to the present invention. FIG. 2 is a plan view of the thin film transistor 3 for video signal write switch. In FIG. 1, drive circuits such as a shift register 1, a buffer 2, and a thin film transistor 3 for a video signal write switch are formed on a substrate to control a plurality of display pixel portions 4 which are two-dimensionally formed on the same substrate. The switching thin film transistor 5 is driven in a dot-sequential manner. Here, the video signal write switch thin film transistor 3 is formed by connecting a plurality of thin film transistors in parallel,
In addition, each thin film transistor connected in parallel has a channel width of about 8 μm. By connecting 40 thin film transistors in parallel, the on resistance of the video signal write switch thin film transistor 3 was 500Ω or less when writing the video signal.

【0018】通常、映像信号線配線容量は 10pF 程度で
あるので、スイッチング素子としての周波数特性(f=1/
(2πRC) )より 30 MHz 程度の周波数が得られる。これ
により、ハイビジョンの映像信号帯域も分割なしで行え
るようになり外部回路の負担が軽減される。
Since the video signal line wiring capacitance is usually about 10 pF, the frequency characteristics (f = 1 /
A frequency of about 30 MHz can be obtained from (2πRC)). As a result, the high-definition video signal band can be performed without division, and the load on the external circuit can be reduced.

【0019】図3は、本発明の多結晶シリコン薄膜トラ
ンジスタからなる駆動回路一体型のアクティブマトリッ
クス型液晶表示装置の他の部分回路図である。図3にお
いて、映像信号書き込みスイッチ用薄膜トランジスタ3
とともにバッファ回路2の薄膜トランジスタもチャネル
幅が約 8μm の複数の薄膜トランジスタを並列に接続し
た構成となっている。バッファ回路2はチャネル幅の大
きなインバータ回路が用いられるが、このバッファ回路
の薄膜トランジスタを並列接続構造とすることにより、
水素化が完全になり、かつ同一製造工程で水素化処理が
できた。
FIG. 3 is another partial circuit diagram of an active matrix type liquid crystal display device integrated with a drive circuit, which is composed of a polycrystalline silicon thin film transistor according to the present invention. In FIG. 3, a thin film transistor 3 for video signal write switch
At the same time, the thin film transistor of the buffer circuit 2 also has a structure in which a plurality of thin film transistors having a channel width of about 8 μm are connected in parallel. An inverter circuit having a large channel width is used as the buffer circuit 2. By using thin film transistors of this buffer circuit in a parallel connection structure,
The hydrogenation was completed, and the hydrogenation was possible in the same manufacturing process.

【0020】同様に、入力保護回路部に形成される静電
対策用の保護 MOSダイオードも水素化が不十分であると
高抵抗となり本来の機能低下をまねくが複数の薄膜トラ
ンジスタを、図8に示すように、並列に接続することに
より低抵抗化が達成できた。
Similarly, the protection MOS diode formed in the input protection circuit section as a countermeasure against static electricity has a high resistance if hydrogenation is insufficient and causes a deterioration in the original function, but a plurality of thin film transistors are shown in FIG. Thus, by connecting them in parallel, it was possible to achieve low resistance.

【0021】[0021]

【発明の効果】本発明の液晶表示装置は、映像信号書き
込み用薄膜トランジスタが水素化処理されてなる複数の
薄膜トランジスタを並列に接続し、かつ並列に接続され
た薄膜トランジスタの個々のチャネル幅を 1μm 以上30
μm 以下と狭くしたので、完全な水素化処理を行うこと
ができるとともに、水素化処理のバラツキを少なくする
ことができる。このため、映像信号書き込みスイッチ用
薄膜トランジスタのオン抵抗を下げ、書き込み時間を短
くすることができる。さらにオフ時のリーク電流を下
げ、消費電力や発熱を抑えることができる。したがっ
て、コントラストに優れた高品質の画像表示を有する液
晶表示装置が得られる。
According to the liquid crystal display device of the present invention, a plurality of thin film transistors for which a video signal writing thin film is hydrogenated are connected in parallel, and each thin film transistor connected in parallel has a channel width of 1 μm or more.
Since the width is made as small as μm or less, it is possible to perform a complete hydrogenation process and reduce variations in the hydrogenation process. Therefore, the on-resistance of the thin film transistor for video signal writing switch can be reduced, and the writing time can be shortened. Further, it is possible to reduce the leak current at the time of off and suppress power consumption and heat generation. Therefore, a liquid crystal display device having high-quality image display with excellent contrast can be obtained.

【0022】また、同一基板上に形成されている薄膜ト
ランジスタのチャネル幅が略同一であるので、水素化処
理等を同一製造工程で行うことができるため、製造工程
が簡略化することができ、液晶表示装置の信頼性が向上
する。
Further, since the thin film transistors formed on the same substrate have substantially the same channel width, the hydrogenation process and the like can be performed in the same manufacturing process, so that the manufacturing process can be simplified, and the liquid crystal The reliability of the display device is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の液晶表示装置の部分回路図である。FIG. 1 is a partial circuit diagram of a liquid crystal display device of the present invention.

【図2】本発明の液晶表示装置における映像信号書き込
みスイッチ用薄膜トランジスタ3の平面図である。
FIG. 2 is a plan view of a thin film transistor 3 for a video signal write switch in a liquid crystal display device of the present invention.

【図3】本発明の液晶表示装置の他の部分回路図であ
る。
FIG. 3 is another partial circuit diagram of the liquid crystal display device of the present invention.

【図4】多結晶シリコン薄膜トランジスタの水素化処理
前後におけるトランジスタ特性を示す図である。
FIG. 4 is a diagram showing transistor characteristics before and after hydrogenation treatment of a polycrystalline silicon thin film transistor.

【図5】多結晶シリコン薄膜トランジスタの水素化処理
後の移動度およびしきい値電圧特性のチャネル幅依存性
を示す図である。
FIG. 5 is a diagram showing channel width dependence of mobility and threshold voltage characteristics of a polycrystalline silicon thin film transistor after hydrogenation.

【図6】多結晶シリコン薄膜トランジスタの水素化処理
を長時間行った場合のトランジスタ特性を示す図であ
る。
FIG. 6 is a diagram showing transistor characteristics when a polycrystalline silicon thin film transistor is hydrogenated for a long time.

【図7】従来の液晶表示装置の部分回路図である。FIG. 7 is a partial circuit diagram of a conventional liquid crystal display device.

【図8】本発明の液晶表示装置の入力保護回路部におけ
る保護 MOSダイオードの部分回路図である。
FIG. 8 is a partial circuit diagram of a protection MOS diode in an input protection circuit section of the liquid crystal display device of the present invention.

【符号の説明】[Explanation of symbols]

1………シフトレジスタ、2………バッファ、3………
映像信号書き込みスイッチ用薄膜トランジスタ、4……
…表示画素部、5………スイッチング用薄膜トランジス
タ、6………信号線、7………ゲート線、8………ゲー
ト走査線駆動回路。
1 ......... Shift register, 2 ......... Buffer, 3 ...
Thin film transistor for video signal writing switch, 4 ...
Display pixel portion, switching thin film transistor, signal line, gate line, gate scanning line drive circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板と、この基板上に 2次元状に形成さ
れた複数の表示画素部と、これら表示画素部をそれぞれ
制御する複数のスイッチング用薄膜トランジスタと、前
記薄膜トランジスタを順次駆動するための信号線走査回
路およびゲート線走査回路よりなる駆動回路部とを前記
基板上に備えた液晶表示装置において、 前記信号線走
査回路は映像信号処理部と、この映像信号処理部からの
映像信号を信号走査線へ書き込みを行う映像信号書き込
み用薄膜トランジスタとを備え、前記映像信号書き込み
用薄膜トランジスタが水素化処理されてなる複数の薄膜
トランジスタを並列に接続し、かつ前記並列に接続され
た薄膜トランジスタの個々のチャネル幅が 1μm 以上30
μm 以下であることを特徴とする液晶表示装置。
1. A substrate, a plurality of display pixel portions formed two-dimensionally on the substrate, a plurality of switching thin film transistors for controlling the display pixel portions, and a signal for sequentially driving the thin film transistors. In a liquid crystal display device having a drive circuit unit including a line scanning circuit and a gate line scanning circuit on the substrate, the signal line scanning circuit performs a signal scanning of a video signal processing unit and a video signal from the video signal processing unit. A thin film transistor for writing a video signal for writing in a line, the thin film transistor for writing the video signal is connected in parallel to a plurality of thin film transistors, and the individual channel widths of the thin film transistors connected in parallel are 1 μm or more 30
A liquid crystal display device characterized by having a size of less than μm.
JP27416892A 1992-10-13 1992-10-13 Liquid crystal display device Withdrawn JPH06123896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27416892A JPH06123896A (en) 1992-10-13 1992-10-13 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27416892A JPH06123896A (en) 1992-10-13 1992-10-13 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH06123896A true JPH06123896A (en) 1994-05-06

Family

ID=17537988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27416892A Withdrawn JPH06123896A (en) 1992-10-13 1992-10-13 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH06123896A (en)

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US6181190B1 (en) 1997-12-04 2001-01-30 Telefonaktiebolaget Lm Ericsson (Publ) Electronic circuit and manufacturing method for electronic circuit
US6677609B2 (en) 1996-06-28 2004-01-13 Seiko Epson Corporation Thin film transistor, manufacturing method thereof, and circuit and liquid crystal display device using the thin film transistor
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