JPH0612385A - Microcomputer system - Google Patents

Abstract

PURPOSE:To use a one-chip microcomputer as a data-bus direct connection type slave-side microcomputer by adding a versatile port and a simple logic circuit. CONSTITUTION:For example, when data are read from the side of a host 1 to the side of a slave 2, an address is outputted from the data address terminal 8 of an AD0-AD1 once a host-side microprocessor executes an IN instruction, and a latch decoder 5 makes a chip select (CS) inverse terminal 15 active. A flip-flop 4 is reset with this CS inverse signal and a low level is outputted from a READY terminal 16. The READY terminal 16 of the side of the slave 2 and the READY terminal 9 of the side of the host 1 are connected to each other and the READY terminal 9 is made inactive to insert a wait state, extending a bus cycle. The CS inverse terminal 15 is connected to the INTO terminal 23 of the one-chip microcomputer 3, which is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microcomputer
More specifically, the present invention relates to a system in which a host-side microprocessor and a slave microcomputer (microcomputer) are connected to a data bus.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional microprocessor on the host side and a one-chip microcomputer on the slaze side are connected by a μPD70 to the microprocessor 1 on the host side.
A general-purpose microcomputer such as 216 (made by NEC) is used,
One-chip microcomputer 2 on the slave side is μPD80C4
Specialized slave microcomputers such as 2 (NEC) are used. The IORD inversion output 6 and the IOWR inversion output 7 of the host side microprocessor 1 are connected to the RD inversion input terminal 11 and the WR inversion input terminal of the slave side microcomputer 2. The address data (AD0-AD15) 8 from the host side microprocessor 1 is transferred to the R side of the host side microprocessor 1 through the control circuit 30.
It is returned to the EADY terminal 16, connected to the READY terminal 9 of the host side microprocessor 1, and connected to the CS inversion terminal 15, the AD inversion terminal 14 and the data wiring (D0-D7) 13 of the slave side microcomputer 2.

[0003]

The conventional host-side microprocessor 1 and the slave-side microcomputer 2 can be connected to the host-side (1) by using a general-purpose microprocessor, but the slave-side one-chip microcomputer is used. 2 is
Since there is no WR and RD (write, read) inversion signal terminal function, there is a problem in that only those specialized for slaves can be used.

An object of the present invention is to solve the above problems and to provide a microcomputer system in which a general-purpose microprocessor can be used on the slave side.

[0005]

A microcomputer system according to the present invention comprises a host side microprocessor having a ready input terminal, a read output terminal and a write output terminal, and a pole input terminal, and the host side microprocessor. A latch / decoder that forms a chip select signal from the address output of the processor, a chip select input terminal that inputs the chip select signal, a ready output terminal that is reset by this chip select input terminal and reset by an internal signal, and the lead. The slave-side microcomputer includes an output terminal and a read input terminal and a write input terminal that are connected to the write output terminal, and a poll output terminal that outputs a polling signal to the poll input terminal.

[0006]

1 is a block diagram of a micro computer system according to an embodiment of the present invention. A μPD70216 manufactured by NEC was used as the microprocessor 1 on the host side, and the microcomputer 2 on the slave side was a 4-bit
The flip-flop 4 is incorporated based on the NEC 5004, which is a one-chip microcomputer 3. A latch / decoder 5 and the like are necessary to connect the microprocessor 1 on the host side and the microcomputer 2 on the slave side.

First, a case where data is read from the host side (1) to the slave side (2) will be described. When the host microprocessor 1 executes the IN instruction, an address is output from the data address terminals 8 of AD0 to AD15, and the chip select (CS) inversion terminal 15 is activated by the latch / decoder 5.
The flip-flop 4 is reset by this CS inversion signal, and a low level is output from the READY terminal 16. The READY terminal 16 on the slave side (2) and the READY terminal 9 on the host side (1) are connected to each other.
The Y terminal 9 becomes inactive, the wait state is inserted, and the bus cycle is extended.

The CS inverting terminal 15 is connected to the INT0 terminal 23 of the one-chip microcomputer 3, and an interrupt is generated in this one-chip microcomputer 3. In the interrupt processing routine of the one-chip microcomputer 3, P30 terminal 18 and P31
Sampling the state of terminal 19 and P32 terminal 22,
The states of the D inversion terminal 11, the WR inversion terminal 12, and the A0 terminal 14 are identified, and it is determined that this is a read cycle. After that, the one-chip microcomputer 3 sets the P21 terminal 25 to high level and the POLL inversion terminal 17 to inactive (high level). The POLL instruction is executed immediately before the IN instruction of the host-side microprocessor 1 and the instruction next to the IN instruction does not proceed until the POLL inversion terminal 17 becomes active (low level). At this time, the one-chip microcomputer 3 is in the process of interrupting, and the P40-P43 terminals 20 and P50-P5 are
The data is output from the three terminals 21 to the P0-P7 terminals 13.

After that, when the P33 terminal 24 is set to the low level, the flip-flop 4 is set. As a result, the READY terminal 16 becomes active (high level), and the input to the READY terminal 9 brings the host side microprocessor 1 into the ready state, and the D0-D7 terminals 13
The data is read from and the read cycle ends. After that, the one-chip microcomputer 3 sets the P21 terminal 25 to the low level, and the POLL inversion terminal 17 becomes active.
As a result, the host microprocessor 1 finishes the IN instruction, and the processing shifts to the next instruction.

Next, a case where data is written from the host side (1) to the slave side (2) will be described. In this case, the procedure is the same as the read cycle,
The difference is that the host side microprocessor 1 outputs data by an OUT instruction, and the one-chip microcomputer 3 fetches data by an interrupt processing routine.

FIG. 2 is a block diagram of the second embodiment of the present invention. This embodiment is an example in which an 8-bit one-chip microcomputer μPD78214 is connected as the slave-side one-chip microcomputer 3a. The procedure for reading / writing data is the same as in the case of the 4-bit one-chip microcomputer.

In this embodiment, the slave side one-chip microcomputer 3a has a plurality of host side microprocessors (μP).
D70236) 1, 1a, the one-chip microcomputer μPD78214 can be used as a slave, and at the same time, data can be transferred from the host microprocessor 1 to another host microprocessor 1a.

[0013]

As described above, in the microcomputer system of the present invention, by adding a general-purpose port and a simple logic circuit to the conventional one-chip microcomputer, the one-chip microcomputer is directly connected to the data bus on the slave side. It has an effect that it can be used as a microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer system according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a microcomputer system according to a second embodiment 2 of the present invention.

FIG. 3 is a block diagram of a conventional host microprocessor and a slave one-chip microcomputer.

[Explanation of symbols]

 1,1a Host-side microprocessor 2 Slave-side microprocessor 3,3a One-chip microcomputer 4,4a R / S flip-flop 5 Latch decoder 5a, 5b Decoder 6,6a IO read / reverse terminal 7,7a IO write / reverse terminal 8a , 8c Data terminal 8b, 8d Address terminal 9, 9a Ready terminal 10, 10a POLL inversion terminal 30 Control circuit

Claims (1)

[Claims] 1. A host-side microprocessor having a ready input terminal, a read output terminal and a write output terminal, and a pole input terminal, and a latch / decoder for forming a chip select signal from an address output of the host-side microprocessor. A chip select input terminal for inputting the chip select signal, a ready output terminal reset by the chip select input terminal and reset by an internal signal, a read input terminal connected to the read output terminal and the write output terminal, A microcomputer system comprising: a slave side microcomputer provided with a write input terminal and a poll output terminal for outputting a polling signal to the poll input terminal.