JPH06120408A - Lead frame for semiconductor integrated device - Google Patents

Abstract

PURPOSE:To reduce DELTAI noise and thereby to prevent a false operation of an input buffer or a logic circuit, without necessitating a change of a manufacturing process and without increasing the cost. CONSTITUTION:Power supply-grounding lines 14a to 14d for connecting power supply ends (or grounding ends) of input buffers of a semiconductor element part, organic insulation films 16a to 16d, power supply-grounding lines 18a to 18d for connecting power supply ends (or grounding ends) of output buffers and organic insulation films 20a to 20d are constructed in a multilayer structure on inner leads 12a to 12d respectively. By this construction, the effective inductance (Leff) of a current passage is reduced, a voltage fluctuation DELTAV brought forth by a transient current at the time of an operation of the output buffer is reduced and thereby DELTAI noise at the time of a simultaneous switching operation is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a semiconductor integrated circuit or the like, and is used for a semiconductor integrated device, in which a voltage fluctuation caused by a transient current during the operation of an output buffer is reduced to prevent noise during a simultaneous switching operation. Regarding

[0002]

2. Description of the Related Art In a conventional semiconductor device, when a plurality of output buffers operating at high speed simultaneously perform switching operations, potential fluctuations occur in a power supply system conductor and a ground (GND) system conductor. So-called noise and ground bounce (hereinafter referred to as ΔI, if necessary) occur during so-called simultaneous switching operation of a plurality of output buffers. It is known that this ΔI causes a malfunction of the input buffer and the logic circuit in the semiconductor element.

The ΔI noise is a voltage fluctuation caused by a transient current when the output buffer operates, and this voltage fluctuation ΔV
Is approximated by the following equation (1). ΔV = n × Leff × (di / dt) (1) n: Number of buffers that perform switching operation simultaneously di / dt: Maximum rate of current change of buffer Leff: Effective inductance of current path

[0004]

By the way, in the recent multi-pin IC devices, the number of output buffers that perform switching operations simultaneously and the rate of change in current tend to increase with higher integration. Therefore, there is a drawback in that the ΔI noise is further increased and the malfunction of the input buffer and the logic circuit is likely to occur.

The present invention solves the problems in the prior art as described above. It is not necessary to change the manufacturing process, the cost is not increased, the ΔI noise is further reduced, and the input of the semiconductor element portion is reduced. An object of the present invention is to provide an excellent lead frame for a semiconductor integrated device which can prevent malfunction of a buffer and a logic circuit.

[0006]

To achieve this object, the invention of claim 1 electrically connects the island on which the semiconductor element portion is arranged, the electrode of the semiconductor element portion and the external terminal by wire bonding. In a lead frame for a semiconductor integrated device including an inner lead, a plurality of signal line portions connected to the semiconductor element portion of the island are insulated from the inner lead and provided in a multilayer structure.

According to a second aspect of the lead frame for a semiconductor integrated device of the present invention, at least one signal line portion of the multi-layered signal line portion is a power line or a ground line.

In the lead frame for a semiconductor integrated device according to the third aspect of the present invention, the multilayer structure of the signal line portion is within the range of sealing from the tip of the inner lead with the insulating member.

In the lead frame for a semiconductor integrated device according to a fourth aspect of the present invention, a plurality of signal line portions having a multi-layer structure are electrically connected between two power source lines in upper and lower insulated layers.
The two ground lines are electrically connected, one of the two power lines is connected to the power supply end of the input buffer of the semiconductor element part of the island, and the other of the two power supply lines is connected to the power supply of the output buffer. The ends are connected, the ground end of the input buffer of the semiconductor element portion of the island is connected to one of the two ground lines, and the ground end of the output buffer is connected to the other of the two ground lines. .

[0010]

With such a structure, in claims 1 and 2,
Since a plurality of signal line portions connected to the semiconductor element portion of the island are insulated from the inner leads and provided in a multilayer structure, and at least one signal line portion is connected to the power supply line or the ground line, for example, the semiconductor element portion The voltage fluctuation caused by the transient current during the operation of the plurality of output buffers is reduced, and ΔI during the simultaneous switching operation is reduced.
Can block noise.

According to the third aspect of the present invention, since the multilayer structure of the signal line portion is within the range of sealing from the tip of the inner lead with the insulating member, it can be sealed with an insulating member such as conventional plastic or ceramic. Since it is not necessary to change the manufacturing process used more, the cost does not increase.

According to a fourth aspect of the present invention, since the power supply end and the ground end of the input buffer and the output buffer of the semiconductor element portion of the island are separately connected to the power supply line or the ground line in the multilayer structure, the output of the semiconductor element portion is output. The ∆I noise generated in the buffer does not sneak into the input buffer,
The influence of ΔI noise can be reduced.

[0013]

Embodiments of a lead frame for a semiconductor integrated device according to the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a top view showing the structure of a lead frame for a semiconductor integrated device according to an embodiment of the present invention, and FIG.
2A is a cross-sectional view taken along the line AA in FIG. 1 and FIG.
FIG. 2 is a sectional view taken along line BB in FIG. 1. Also, in FIG.
It is a perspective view which expands and shows a principal part.

First, the description will be made according to claims 1 and 2.
1, FIG. 2 and FIG. 3, the lead frame for a semiconductor integrated device has an island 1 on which a semiconductor element portion is arranged.
0, inner leads 12a, 12b, 12c, 12d that surround the island 10 on all sides, and a power supply terminal or a ground terminal of an input buffer of a semiconductor element portion (not shown) arranged on the island 10 to connect the power supply of the input buffer. Power supply / ground lines 14a, 14 to be lines or ground lines
b, 14c, 14d.

Further, the lead frame for a semiconductor integrated device has organic insulating films 16a, 16b, 16c, 1 arranged in contact with the lower surfaces of the power / ground lines 14a-14d.
6d and an output buffer of a semiconductor element part (not shown) which is arranged to be bonded to the lower surfaces of the organic insulating films 16a to 16d and which is arranged on the island 10 by being connected to the power / ground lines 14a to 14d by through holes. The power supply line of the output buffer is connected to the power supply end or the ground end of the power supply / ground line 18a, 18b, 1
8c and 18d are provided.

Further, on the lead frame for a semiconductor integrated device, the organic insulating films 20a and 20b are arranged so as to be bonded to the lower surfaces of the power / ground lines 18a to 18d and the upper surfaces of the inner leads 12a to 12d. , 20c, 2
And 0d.

Here, the power / ground lines 14a to 14d are used.
Is used as a power supply line or a ground line of the input buffer. The power / ground lines 18a-18d are used as power lines when the power / ground lines 14a-14d are used as power lines, or are used as ground lines when the power / ground lines 14a-14d are used as ground lines. To do. That is, it is used as only one of the power supply line and the ground line.

Next, the operation and function of the structures of claims 1 and 2 will be described. Inner leads 12a-1
Power supply / ground lines 14a to 14d to be a power supply line or a ground line of the input buffer and an organic insulating film 16 on 2d.
a to 16d, power / ground lines 18a to 18d serving as power lines or ground lines of the output buffer, and organic insulating films 20a to 20d are laminated to form a multilayer structure.

Therefore, the effective inductance (Leff) of the current path is reduced. That is, the effective inductance (Leff) of the current path in “ΔV = n × Leff × (di / dt)” of the previous equation (1) is reduced, and the voltage fluctuation ΔV caused by the transient current during the operation of the plurality of output buffers. Is reduced, and ΔI during this simultaneous switching operation
Can block noise.

Next, a description will be given according to claim 3. Figure 2
In, power supply / ground lines 14a-14d, organic insulating films 16a-16d, power supply / ground lines 18a-18d,
The range of the multi-layer structure of the organic insulating films 20a to 20d is the range shown by the chain line in FIG. That is, the package 11 is formed by sealing only the range of the one-dot chain line with the insulating member 11a such as plastic or ceramic.

Next, the function of the structure of claim 3 will be described. Power supply / ground lines 14a to 14d,
Organic insulating films 16a to 16d and power / ground line 18a
.About.18d and the organic insulating films 20a to 20d in a multi-layered structure, which is sealed in the package 11 shown by the alternate long and short dash line in FIG. Therefore, conventional plastic,
It can be sealed with an insulating member such as ceramic, and there is no need to change the conventional manufacturing process, which does not increase the cost.

Next, a description will be given according to claim 4. When it is desired to provide both the power supply line and the ground line with respect to the configurations of claims 1 and 2, the power supply / ground lines 14a to 14 are provided.
In addition to the power supply / ground lines 18a-18d, the power / ground lines (14a-14d) and the power / ground lines (18a-18d) are insulated from each other to form a multilayer structure.

For example, the power supply / ground line of the first layer is used as the power supply line of the input buffer, and the power supply / ground line of the second layer is used as the power supply line of the output buffer. Furthermore, the power / ground line of the third layer is used as the ground line of the input buffer,
The power / ground line on the fourth layer is used as the output buffer ground line. In this case, through holes are used to connect the power supply / ground lines, which are the power supply lines for the first and second layers. Similarly, the power supply and ground lines, which are the ground lines of the third and fourth layers, are also connected by through holes.

Next, the operation in the structure of claim 4
The function will be described. In this configuration, the island 10
There are provided four layers of power supply / grounding lines, which are power supply lines to which the power supply ends and the grounding ends of the input buffer and the output buffer of the semiconductor element section arranged in the above are connected, and a ground line.

That is, the power supply line and the ground line of the input buffer and the output buffer are separated. Therefore, the ΔI noise generated in the output buffer does not sneak into the input buffer, and the influence of the ΔI noise can be reduced.

[0027]

As is apparent from the above description, in claims 1 and 2, a plurality of signal line portions connected to the semiconductor element portion of the island are insulated from the inner leads and provided in a multilayer structure, and at least Since one signal line portion is connected to the power supply line or the ground line, for example, voltage fluctuation caused by transient current during operation of a plurality of output buffers of the semiconductor element portion is reduced, and ΔI noise during this simultaneous switching operation is blocked. It has the effect of being able to.
According to the third aspect, since the multilayer structure of the signal line portion is within the range of sealing from the tip of the inner lead with the insulating member, it can be sealed with an insulating member such as a conventional plastic or ceramic, which is conventionally used. Since there is no need to change the manufacturing process, the cost is not increased. In the present invention, since the power supply end and the ground end of the input buffer and the output buffer of the semiconductor element part of the island are separately connected to the power supply line or the ground line in the multilayer structure, the output buffer of the semiconductor element part is generated. This has the effect that the influence of ΔI noise can be reduced since the influence of ΔI noise on the input buffer is eliminated.

[Brief description of drawings]

FIG. 1 is a top view showing a configuration in an embodiment of a lead frame for a semiconductor integrated device of the present invention.

FIG. 2A is a cross-sectional view showing a cross-sectional structure taken along line AA in FIG. (B) is a cross-sectional view showing a cross-sectional structure taken along line BB in FIG. 1.

FIG. 3 is an enlarged perspective view showing a main part of the embodiment.

[Explanation of symbols]

 10 Island 11 Package 11a Insulating member 12a-12d Inner leads 14a-14d, 18a-18d Power / ground line 16a-16d, 20a-20d Organic insulating film

Claims (4)

[Claims] 1. A lead frame for a semiconductor integrated device, comprising: an island on which a semiconductor element portion is arranged; and an inner lead for electrically connecting an electrode of the semiconductor element portion and an external terminal by wire bonding. A lead frame for a semiconductor integrated device, wherein a plurality of signal line portions connected to a semiconductor element portion of an island are provided in a multilayer structure having insulation on the inner leads. 2. The lead frame for a semiconductor integrated device according to claim 1, wherein at least one signal line portion of the multi-layered signal line portion is a power supply line or a ground line. 3. The lead frame for a semiconductor integrated device according to claim 1, wherein the multilayer structure of the signal line portion is within a range of sealing from the tip of the inner lead with an insulating member. 4. A plurality of signal line portions having a multi-layer structure are electrically connected between two power supply lines in upper and lower layers insulated from each other, and are electrically connected between two ground lines. The power supply terminal of the input buffer of the semiconductor element part of the island is connected to one of the two power supply lines, the power supply terminal of the output buffer is connected to the other of the two power supply lines, and the island is connected to one of the two ground lines. The ground end of the input buffer of the semiconductor element part of is connected,
2. The lead frame for a semiconductor integrated device according to claim 1, wherein the ground end of the output buffer is connected to the other of the two ground lines.