JP2606116B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of the present invention, and more particularly to a bypass capacitor formed inside a package for a semiconductor device.

[0002]

2. Description of the Related Art Hitherto, as a structure in which a bypass capacitor is formed inside a package for a semiconductor device, there are JP-A-3-94452 and JP-A-59-211121. This conventional example will be described with reference to the drawings.

FIG. 6 is a sectional view showing the structure of a conventional bypass capacitor inside a package. Also, FIG.
It is a circuit diagram of a power supply and a ground conductor of a conventional package.

According to FIG. 6, power supply conductor layers 2-a and 2-b connected to a power supply terminal 1 have a ground conductor layer 5 connected to a ground terminal 4 with an insulating layer 3 made of ceramic or polycarbonate interposed therebetween. -A to c are alternately stacked. The signal terminals 6 are connected to the semiconductor chip 9 via the signal conductor layers 7 and the bonding wires 8-c, respectively. Similarly, the power supply conductor layer 2 and the ground conductor layer 5 are connected to the semiconductor chip 9 via bonding wires 5-b, respectively. Since the power supply conductor layer 2 and the ground conductor layer 5 configured as described above constitute a multilayer capacitor and are connected in close proximity to the semiconductor chip 9, the high-frequency impedance of the power supply is lower than that of a bypass capacitor connected outside the package. The effect of reducing is large. This effect will be described with reference to a circuit diagram. In the circuit shown in FIG. 7, terminals V1 'and G1' are a power supply terminal 1 connected to a semiconductor chip, and a ground terminal 4, V2 'and G2' are a power supply terminal 1 and a ground terminal 4 connected to a printed circuit board or the like, respectively. is there. Generally, the power supply current changes depending on the operation state of the elements in the semiconductor chip, and the change in the power supply current is transmitted to the power supply conductor in the package via the power supply terminal V1 '. The change in the transmitted power supply current becomes a voltage fluctuation due to the back electromotive force of the inductance L _V1 ′ of the bonding wire or bonding stitch portion of the power supply conductor, and is led to the power supply terminal V 2 ′ connected to a printed circuit board or the like. At this time, as a means for suppressing power fluctuation, a bypass capacitor C _B ′ is inserted between the power conductor and the ground conductor to transmit the power fluctuation (AC component) to the bypass capacitor side and led out to a stable potential G2 ′ terminal side. I do. That is, the AC impedance of the power supply circuit in the package is determined by the pure resistances R _V1 ′ and R _V2 ′ and the inductance L _V1 ′ of the power supply conductor.
The impedance due to _LV2 'and the bypass capacitor C
'L _C1 from the derivation path to ground conductors' _B, L _C2',
It becomes a combined (parallel) impedance of the impedances of C _B ′, R _G2 ′, and L _G2 ′, and the impedance can be reduced as compared with the case of a single power supply conductor. In the conventional example described above, the insulator forming the capacitor is made of the same material as the insulator forming the package base, and generally has a structure assuming a ceramic such as alumina.

A conventional example using a package base made of a plastic such as an epoxy resin is disclosed in Japanese Patent Laid-Open No. 57-4925.
There are nine. This conventional example will be described with reference to the drawings.
FIG. 8A is a plan view of the second conventional example, and FIG. 8B is a sectional view.

In this second conventional example, the semiconductor chip 23
The die pad 24 directly below has a laminated structure of metal conductors 24-ac and dielectrics 25-a and 25b, whereby a capacitor is formed inside the package and the semiconductor chip is bonded by bonding wires 26-ae. The connection to the ground potential and the power supply potential of the leads 23 and the leads 27 is made to function as a capacitor. In this second conventional example, it is considered that the effect of having the capacitor inside the package has the same effect as that of the above-described conventional example, but the electrical connection is made only by the bonding wire. Therefore, the inductance is likely to be large, and the desired effect may not be obtained. It is also true that the simple structure of the plastic package impairs the cost and the like.

[0007]

Generally, a high-frequency impedance of a power supply conductor is reduced by forming a bypass capacitor inside a package, and a fluctuation in power supply potential due to an operation state of a semiconductor chip can be reduced. When the power supply impedance is reduced by the bypass capacitor to suppress the power supply potential fluctuation, it is desirable that the impedance via the bypass capacitor be smaller than the power supply impedance over a wide frequency band in order to obtain a sufficient effect. However, in the case of a bypass capacitor built into a conventional semiconductor device package, the ratio of the inductance of the power supply conductor and the capacitance of the bypass capacitor is reduced because the bypass capacitor is formed in a single structure in the package. It is constant within the package. As a result, the impedance resonance via the bypass capacitor becomes only one point, and there is a disadvantage that the frequency band in which the impedance is equal to or less than the impedance of the power supply conductor alone is narrowed.

[0008]

In a semiconductor device package according to the present invention, a bypass capacitor attached between a power supply and a ground potential of the semiconductor device is formed in the semiconductor device package, and the capacitance value of the bypass capacitor is measured by the package. It has a structure that changes depending on the location inside.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor package according to the present invention;

According to FIG. 1, a power supply wiring 10 is connected to a power supply terminal 1.
Power supply conductor layers 2-a, b made of a metal (gold, aluminum, etc.) layer or a semiconductor (polysilicon, etc.) layer
Is connected to a ground terminal 4 made of metal with an insulating layer 3 made of ceramic, polycarbonate or the like interposed therebetween.
1 and are alternately stacked with the ground conductor layers 5-a, b, and c connected to each other. Each of the signal terminals 6 is connected to the semiconductor chip 9 via a signal wiring 12, a signal conductor layer 7, and bonding wires 8-c made of gold or an alloy with gold. Similarly, the power supply conductor layers 2-a, b, the ground conductor layers 5-a, b,
c is connected to the semiconductor chip via a power supply line 13, a ground line 14, and bonding wires 8-a and 8-b, respectively. Power supply conductor layers 2-a, b and ground conductor layers 5-a, b, c
Are stacked with an insulating layer interposed therebetween, but the number of layers is changed between a portion directly below the semiconductor chip 9 and a peripheral portion near the terminals. That is, the power supply conductor layer 2-b and the ground conductor layer 5-c do not form a conductor pattern immediately below the semiconductor chip 9. FIG. 2 shows a corresponding perspective view. Here, the through-hole 17 is provided to allow the wiring from the external terminal 16 to pass through a conductor layer that does not need to be connected to connect the external terminal 16 to a specific conductive ground layer. The bonding stitch 18 is provided for connecting the external terminal 16 to the semiconductor chip 9. The lid 19 is made of metal or the like. The other parts are the same as those shown in FIG. This makes it possible to change the ratio of the capacitance per unit area and the inductance of the conductor between the portion immediately below the chip and the portion around the terminals, and two resonance frequencies can be obtained for convenience. FIG. 3 is a circuit diagram showing the power conductor and the ground conductor. According to FIG. 3, the power supply current generated in the semiconductor chip 9 flows into the package from the power supply terminal V1 connected to the semiconductor chip. The power supply current changes depending on the operation state of the semiconductor chip 9, whereby the bonding wires 8-a, b, c,
Each conductor layer 2, 5, 7 and each wiring 10, 11, 12, 1
The back electromotive force of the inductance L _V1 such as 3, 14 is generated, and the power supply voltage fluctuates. To effectively reduce this variation,
A bypass capacitor may be inserted between the power supply conductor and the ground conductor to transmit a power supply voltage fluctuation component (AC component) to the bypass capacitor side, and a path may be provided for leading to a stable potential G2 terminal side. In this embodiment, the configuration of the bypass capacitor is composed of two capacitors, C _B1 and C _B2 , due to the difference in capacitance value per unit area and the difference in the surrounding inductance.

The difference in the effect of the bypass capacitor between the semiconductor device package of the present invention shown in FIG. 1 and the conventional semiconductor device package shown in FIG. 6 will be described with reference to a graph. The only difference between the packages shown in FIGS. 1 and 6 is the configuration of the bypass capacitor. In the package of FIG. 1, the capacitance immediately below the semiconductor chip is halved compared to the package of FIG. FIG. 4 shows the frequency change of the power source impedance at this time. According to this, the impedance characteristics of each power supply conductor (filled by a dotted line) are almost the same in the present invention, and the impedance characteristics via a bypass capacitor of a conventional package (filled by a dashed line) have a lower resonance frequency. The impedance has also become smaller. However, the impedance characteristic (filled with a solid line) of the package of the present invention via the bypass capacitor has a value equal to or less than the impedance of the power supply conductor alone since it has two resonance frequencies and the frequencies are relatively close to each other. The frequency bandwidth B is about twice as wide as the frequency bandwidth B 'in the conventional package.

Next, a second embodiment of the present invention will be described. In FIG. 5, in order to change the capacitance value of the bypass capacitor in the semiconductor device package, the power supply conductor layer 2-
b and the grounding conductor layers 5-c and d are formed, and the power supply conductor layer 2-a and the grounding conductor layer 5-
a and b constitute a bypass capacitor. By configuring the bypass capacitor in this manner, the effect of reducing the noise component flowing from the external terminal 16 as well as the effect described in the previous embodiment can be obtained. This is because the impedance of the bypass capacitor can be reduced in a relatively wide frequency band since the external terminal 16 has a capacitance component in the immediate vicinity of the external terminal 16 and has only the external terminal 16 as an inductance component.

In the first and second embodiments of the present invention, a bypass capacitor having different capacitance is obtained by partially changing the number of layers of the power supply conductor layer and the ground conductor layer in the semiconductor package. Alternatively, the distance between the power supply conductor layer and the ground conductor layer may be partially changed, or the dielectric constant of the insulating film between the power supply conductor layer and the ground conductor layer may be partially changed to bypass different capacitances. A capacitor may be obtained.

[0014]

As described above, the structure of the bypass capacitor in the package for a semiconductor device according to the present invention is such that a plurality of capacitors having different capacitance values are formed in the package so that the inductance of the bypass capacitor and the inductance of the conductor part are reduced. A plurality of resonance frequencies can be provided.
The plurality of resonance frequencies can be set between 2 and 10 times by appropriately adjusting the capacitance value of the bypass capacitor. Therefore, by applying the configuration of the bypass capacitor of the present invention, the frequency band can be expanded as compared with the configuration of the conventional bypass capacitor, and the power supply voltage suppressing effect can be increased in a wide frequency band.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device package according to an embodiment of the present invention.

FIG. 2 is a perspective view of FIG. 1;

FIG. 3 is a circuit diagram of power and ground conductors of the semiconductor device package of FIG. 1;

FIG. 4 is a graph showing frequency characteristics of impedance of a bypass capacitor.

FIG. 5 is a sectional view of a semiconductor device package according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device package.

FIG. 7 is a circuit diagram of a power supply / ground conductor of the semiconductor device package of FIG. 5;

8A is a plan view of a second conventional semiconductor device package, and FIG. 8B is a cross-sectional view of FIG. 8A.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power terminal 2-a, b Power conductor layer 3 Insulating layer 4 Ground terminal 5-a, b, c Ground conductor layer 6 Signal terminal 7 Signal conductor layer 8-a, b, c Bonding wire 9 Semiconductor chip 10 Package base 16 External terminal 23 Semiconductor chip 24-a, b, c Metal conductor (die pad) 25-a, b Dielectric 26-a, b, c, d, e Bonding wire 27 Lead

Claims (3)

(57) [Claims] 1. A package base, a semiconductor chip disposed in the package base, a power supply terminal provided outside the package base for supplying a power supply potential to the semiconductor chip, and a ground connected to the semiconductor chip. A ground terminal provided outside the package base for supplying a potential, a signal terminal for inputting / outputting a signal to / from the semiconductor chip, a power conductor layer to which the power terminal is connected, and A ground conductor layer to which a terminal is connected; and the conductor layer and the ground conductor layer provided with an insulator layer interposed therebetween in a first region of the package base where the power supply terminal, the ground terminal, and the signal terminal are provided. And a conductor provided in a second region of the package base on which the semiconductor chip is mounted with the insulator layer interposed therebetween. A second bypass capacitor comprising a first bypass capacitor and a ground conductor layer, wherein the first bypass capacitor and the second bypass capacitor have different capacitances. 2. The first bypass capacitor and the second bypass capacitor, wherein the number of layers of the conductor layer and the insulator layer is different between the first region and the second region. The semiconductor device according to claim 1, wherein: 3. The first bypass capacitor and the second bypass capacitor have different areas of the conductor layer and the insulator layer facing each other between the first region and the second region. The semiconductor device according to claim 1, wherein: