JPH06119199A - Execution control system for test program - Google Patents

Abstract

PURPOSE:To test a part to control a system such as the conversion mechanism of a dynamic address and a storage protective mechanism, etc., by generating an address conversion table independently by a test program, and performing the test of the address conversion mechanism and the storage protective mechanism managed by a monitor program in the ordinary operation of a computer. CONSTITUTION:IPL is performed in step S1, and the monitor program is loaded by the IPL. The monitor program is not provided with the address conversion table, and it can control two kinds of programs for architecture, and is provided with a state of PSW when control is delivered to the program. Other setting is performed by the monitor program in step S2, and the test program is loaded according to the instruction of an operator in step S3. The address conversion table is generated by the test program in step S4, and the setting of the storage protective mechanism is performed by the test program in step S4, and also, the test program is executed in step S6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test program execution control system capable of testing a system control portion such as a dynamic address translation mechanism and a memory protection mechanism.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a conventional test processing procedure. In step S1, IPL is performed and the monitor program is loaded. In step S2, the monitor program creates an address conversion table. In step S3, the memory protection mechanism (ring N
o. ) Is set. In step S4, other settings (interrupt processing, etc.) are performed. In step S5, the test program (T
P) is loaded. In step S6, a test is performed by executing the test program.

FIG. 9 is a diagram showing an operation at the time of loading a conventional test program. In step S1, a test program is loaded. In step S2,
Set the PSW architecture mode to old architecture. In step S3, control is passed to the test program. In step S4, the test program of the old architecture is executed. The old architecture is
It means a logical configuration that can operate on the current computer and a new product computer, and the new architecture means a logical configuration that can operate only on the new product computer.

The monitor program is for controlling and monitoring the test program (loading / starting the test program, monitoring interrupts, etc.). The test program tests the hardware and firmware of the computer. The test program of the present invention tests the hardware and firmware of the CPU.

The address translation mechanism is a function provided in hardware to assist the operating system when implementing the virtual memory system. The virtual memory system allows a program to use a logical address space of a much larger capacity than the actual memory capacity of the main memory. By using the logical address space, the program can create the program as if continuous addresses were given in the main memory.

The address conversion table is a correspondence table for converting a logical address into a real address. This address translation table is used for block table, segment
It consists of three types of tables: tables and page tables. Creating the address conversion table means expanding this correspondence table in the main memory.

FIG. 10 is a diagram for explaining the outline of the address conversion table. The logical address is composed of a block number, a segment number, a page number and a displacement within a page. The block table has a plurality of entries, and the entry valid / invalid bit and the segment table start address are written in each entry. The segment table has a plurality of entries, and entry valid / invalid bits, ring numbers and page table start addresses are written in each entry. page·
The table has a plurality of entries, each entry having an entry valid / invalid bit and a page address.

The conversion from the logical address to the real address is performed as follows. First, the entry of the block table corresponding to the block number of the logical address is read to obtain the segment table start address. Next, the entry corresponding to the segment number of the logical address in the segment table specified by the obtained segment table start address is read,
Find the table top address. Next, the requested page
The entry corresponding to the page number of the logical address in the page table specified by the table top address is read to obtain the page address. Next, the real address is obtained by adding the obtained page address and the displacement within the page of the logical address.

If the program being executed mistakenly accesses the area of another program, the data area, or the area of the operating system, the program may run away or the other program or data may be destroyed. The memory protection mechanism is for preventing such a situation from occurring. If the wrong area is accessed by the storage protection mechanism, execution is suppressed or aborted and a storage exception program interrupt occurs. The memory protection function is performed on the logical address space of each segment.

The storage protection function is a ring protection function that protects the storage by the size of the segment ring number (designated by the area in the entry of the segment table) and the PSW ring number (designated by the program status word). And the limit protection function that protects the memory outside the limit register. The setting of the storage protection mechanism is to set the ring number in the area in the entry of the segment table.

FIG. 11 is a diagram for explaining the outline of the memory protection mechanism. In the illustrated example, the main memory is divided into a monitor program area, an address conversion table area, an area A, a test program area, and an area B. The ring number of the monitor program area is set to 1 and the address conversion table area is set. The ring number of the area is 2, the ring number of the area A is 3, the ring number of the area of the test program is 5, and the ring number of the area B is 6.

In the illustrated example, when the ring number of the current PSW when the monitor program operates is 0, all areas on the main memory can be read / written. If the ring number of the current PSW (given by the monitor program) when the test program operates is 4,
The area of the test program and the area B can be read / written, but the area of the monitor program, the area of the address conversion table and the area A cannot be written.

The interrupt function is a function for changing the state of the CPU according to the conditions inside or outside the system or the condition of the CPU itself. Interrupts are classified into four types: input / output interrupts, program interrupts, supervisor call interrupts, and machine interrupts. An interrupt factor occurs and CP
If U is ready to accept this, replace the current PSW with the old PS
W is stored in the fixed address of the main memory as the W, the new PSW stored in advance in the fixed address of the main memory is read as the current PSW, and then the CPU shifts to the process defined by the new PSW. The "other setting" in FIG. 8 means that a new PSW is set at a fixed address in the main memory so that the processing at the time of interrupt occurrence can be executed when each interrupt occurs.

[0014]

Normally, the monitor program generates a memory protection exception interrupt when the test program tries to destroy the monitor area so that the test program does not destroy the monitor area. Create an address translation table. Therefore, since the address translation table itself is also an asset of the monitor, when the test program tries to change the address translation table, a memory protection exception occurs.

In the conventional system as shown in FIG. 8, the test program operates under the control of the address conversion table created by the monitor program and the memory protection, so that the diagnosis cannot be performed. That is, the test program cannot destroy the resources of the monitor program. Further, in the conventional method as shown in FIG. 9, it is impossible to execute the test program described by the instruction set of the new architecture.

A first object of the present invention was created in view of this point, and it is possible to perform a test of a portion that controls a system such as a dynamic address translation mechanism and a memory protection mechanism. It is in. A second object of the present invention is to operate two kinds of test programs having different instruction sets on one computer. The third object of the present invention is to
It is to be able to handle interrupts generated by two different test programs.

[0017]

Therefore, according to the test program execution control method of claim 1, the test program creates its own address translation table, sets the memory protection, and monitors the program during normal operation of the computer. It is characterized by testing the address translation mechanism and the memory protection mechanism managed by.

According to another aspect of the test program execution control method of the present invention, the test program is loaded, the first instruction of the loaded test program is determined, and the first instruction is the instruction of the first architecture or the instruction of the second architecture. If it is an instruction of the first architecture, the program state word architecture
Set the mode to a predetermined value and execute the test program. If the instruction is of the second architecture, set the architecture mode of the program state word to another predetermined value and execute the test program. It is characterized by doing.

According to the test program execution control method of claim 3, the type of interrupt generated by the test program is registered, and when an interrupt occurs in the test program, it is checked whether or not the interrupt is the expected interrupt. If the interrupt is the expected interrupt, the architecture mode of the program state word at the time of the interrupt is determined, the architecture mode is checked to determine whether it is the first architecture mode or the second architecture mode, and the first architecture mode In the case of, the processing according to the interface of the first architecture is performed, the architecture mode of the program state word is set to the first architecture, control is passed to the test program, and in the case of the second architecture mode, Performs processing according to the interface of the second architecture. , Set the architecture mode program status word to the second architecture, it is characterized in that passes control to the test program.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a test processing procedure in the present invention. In step S1, IPL is performed. IPL
Causes the monitor program to be loaded. The monitor program of the present invention does not have an address conversion table (including storage protection). It can control programs with two different architectures. Holds the PSW state (ring number, etc.) when control is passed to the program. This is different from the conventional monitor program.

In step S2, other settings (interrupt processing, etc.) are made by the monitor program. In step S3, the test program is loaded according to the instruction of the operator. The test program of the present invention has an address translation table (including memory protection),
It is different from the conventional test program. Step S4
Then, the Tetos program creates the address translation table. In step S5, the test program sets the memory protection mechanism (ring No.). In step S6, the test program is executed.

Two specific examples of typical tests will be described below. (1) Block conversion specification test Confirm that a block conversion exception program interrupt is generated when an area where the invalid bit of the block table is ON is accessed. Also, it is confirmed that the specified logical address (the invalid bit of each table is OFF) matches the expected real address. (2) Memory protection exception test If an attempt is made to write to an area assigned a segment ring number smaller than the ring number of the current PSW,
Confirm that a memory protection exception program interrupt has occurred. Further, it is confirmed that the area assigned with the segment ring number larger than the ring number of the current PSW can be normally read / written.

FIG. 2 is a diagram showing the structure of the PSW (program status word) used in the present invention. P used in the present invention
SW has an architecture mode designation bit. The architecture mode designation bit is set to 0 in the case of the old architecture, and the architecture mode designation bit is set to 1 in the case of the new architecture.
If an attempt is made to execute an instruction for a new architecture while the architecture mode specification bit is 0, a program interrupt will occur. Similarly, attempting to execute an instruction for the old architecture while the architecture mode designation bit is 1 will cause a program interrupt. The monitor program of the present invention basically operates on the old architecture.

FIG. 3 is a diagram for explaining the instruction set of the old and new architectures. The branch instruction is GO in the old architecture, and the branch instruction is JUM in the new architecture.
P. The head instruction of the test program using the old arch instruction set is GO, and the head instruction of the test program using the new arch instruction set is JUMP.

FIG. 4 is a diagram showing general-purpose registers of the old and new architectures. In the old architecture, there are 16 general-purpose registers R0 to R15, and each general-purpose register has a 2-byte structure. In the new architecture, there are 32 general-purpose registers R0 to R31, and each general-purpose register has a 4-byte structure.

FIG. 5 is a diagram showing a process at the time of loading the test program in the present invention. Although the computer of the present invention is of the old type, it can execute the test program of the old architecture or the test program of the new architecture by emulating with the special firmware (making the instruction set of the new architecture operable). Running the test program of the new architecture is for debugging this test program.

In step S1, a test program is loaded. In step S2, the first instruction of the loaded test program is determined. Step S
At 3, it is checked whether it is an old arche instruction. If Yes, the process proceeds to step S4, and if No, the process proceeds to step S7.

In step S4, the architecture mode of PSW is set to old arch. In step S5, control is passed to the test program. In step S6, the old arch test program is executed. In step S7, the architecture mode of PSW is set to new arch. In step S8, control is passed to the test program. In step S9, the new arch test program is executed.

6 and 7 are diagrams for explaining the operation when an interrupt occurs according to the present invention. In step S1, the test program issues an interrupt monitoring request. If a program interrupt occurs during execution of a normal test program, control passes to the monitor program, causing abnormal termination.
Since the test program of the present invention intentionally generates a program interrupt (tests for address conversion and memory protection), it notifies the monitor program in advance so that it will not end abnormally even if a program interrupt occurs. An instruction for issuing a supervisor call interrupt is used for the interrupt monitoring request. (You must match the interface with the monitor program. When this interrupt occurs, the monitor program will handle it so that it will not end abnormally even if a program interrupt occurs during execution of the test program. Pass control to)

In step S2, the monitor registers an interrupt. In step S3, the test program generates an interrupt. In step S4, it is checked whether the monitor is the expected interrupt. If Yes, go to step S5
If No, the process ends abnormally. In step S5, the architecture mode of the PSW at the time of interruption is determined.

In step S6, it is checked whether the old architecture mode is set. If Yes, the process proceeds to step S7, and if No, the process proceeds to step S9. In step S7, processing is performed according to the interface of the old arche.
For example, the monitor program must restore (previously save) the state of the test program when it was used by the test program, when the control is passed to the test program again. The number of registers saved / restored is 16 (0 to 15) (32 bytes) for the old arch, but 32 (0 to 31) (128 bytes) for the new arch.

In step S8, the architecture mode of PSW is set to old arch. In step S9, processing is performed according to the new arch interface. In step S10, the architecture mode of PSW is set to new arch. In step S11, control is passed to the test program. In step S12, a test is executed.

[0033]

As is apparent from the above description, according to the present invention, it is possible to diagnose the dynamic address translation mechanism and the memory protection mechanism which cannot be diagnosed under the control of the conventional monitor program. Further, according to the present invention, both of two types of test programs having different instruction sets can be executed on one computer. Furthermore, according to the present invention, an interrupt generated by a test program of a certain instruction set can be processed, and an interrupt generated by a test program of another instruction set can also be processed.

[Brief description of drawings]

FIG. 1 is a diagram showing a test processing procedure according to the present invention.

FIG. 2 is a diagram showing a configuration of a PSW of the present invention.

FIG. 3 is a diagram showing an instruction set of the old and new architectures.

FIG. 4 is a diagram illustrating general-purpose registers of old and new architectures.

FIG. 5 is a diagram showing a process at the time of loading a test program according to the present invention.

FIG. 6 is an operation (No. 1) when an interrupt occurs in the present invention.
FIG.

FIG. 7 is an operation (No. 2) when an interrupt occurs in the present invention.
FIG.

FIG. 8 is a diagram showing a conventional example.

FIG. 9 is a diagram showing a conventional loading operation.

FIG. 10 is a diagram illustrating an outline of an address conversion table.

FIG. 11 is a diagram for explaining an outline of a memory protection mechanism.

[Explanation of symbols]

 TP test program R0 to R31 general-purpose registers

Claims (3)

[Claims] 1. The test program creates an address translation table independently, sets storage protection, and tests the address translation mechanism and storage protection mechanism managed by the monitor program during normal operation of the computer. Test program execution control method. 2. A test program is loaded, an instruction at the head of the loaded test program is determined, it is checked whether the head instruction is an instruction of the first architecture or an instruction of the second architecture, and the instruction of the first architecture is read. If it is an instruction, the architecture mode of the program state word is set to a predetermined value, the test program is executed, and if it is an instruction of the second architecture, the architecture mode of the program state word is changed to another. The test program execution control method is characterized in that the test program is executed by setting it to a predetermined value. 3. An interrupt type generated by a test program is registered. When an interrupt occurs in the test program, it is checked whether or not the interrupt is an expected interrupt. If the interrupt is the expected interrupt, an interrupt is generated. The architecture mode of the program state word at the time is determined, and whether the architecture mode is the first architecture mode or the second architecture mode is checked. In the case of the first architecture mode, the first architecture mode Performs processing according to the interface, sets the architecture mode of the program state word to the first architecture, transfers control to the test program, and in the case of the second architecture mode, adjusts to the interface of the second architecture. And the program status word architecture Set de the second architecture, execution control method of the test program, characterized in that passes control to the test program.