JPH06113525A - Snubber circuit - Google Patents

Abstract

PURPOSE:To provide a snubber circuit which suppresses excessive surge voltage at the time of reverse recovery of a free-wheeling diode connected with a self- extinguishing power semiconductor element, or suppresses erroneous function of drive circuit or controller. CONSTITUTION:Snubber circuits 10, 20, 30, connected in parallel with self- extinguishing power semiconductor elements constituting a power converter, are connected in parallel with a second snubber circuit constituted of capacitors 16, 26, 36. Capacitances of the capacitors are selected such that the time required for reverse recovery of a FWD is equal to the time required for discharge of the second snubber circuit thus suppressing excessive surge voltage at the time of reverse recovery of free-wheeling diode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a free wheeling diode (hereinafter referred to as FWD) connected in anti-parallel with a self-arc-extinguishing type power semiconductor constituting a power converter.
The present invention relates to a snubber circuit that suppresses surge voltage generated during reverse recovery.

[0002]

2. Description of the Related Art A self-extinguishing type power semiconductor that constitutes a power conversion device is provided with an IG capable of extremely high-speed switching operation.
BT and MOSFET have been applied in recent years. Figure 5 shows IG
It is the figure which showed the circuit structure of the voltage type 3 phase inverter which is one of the power converter devices which used BT. 1 is a DC power supply (power supply voltage Ed), 11, 12, 21, 22, 31, 32 are IGBTs, 13, 23, 33 are resistors, 14, 24, 34
Is a diode and 15, 25 and 35 are capacitors.
The resistor 13, the diode 14, and the capacitor 15 constitute the snubber circuit 10, and similarly, the snubber circuits 20 and 3
0 is configured. In addition, 17, 18, 27, 28,
37 and 38 are FWD, IGBT11,12,2
1, 22, 31, and 32 are respectively connected in antiparallel.

As shown in FIG. 5, two IGBTs are connected in series, and this series circuit is connected between the positive and negative electrodes of the DC power source 1 to obtain I
A voltage-type three-phase inverter for converting DC power into three-phase AC power is configured by performing power conversion by alternately turning on and off the GBTs and connecting three sets of the IGBT series circuits in parallel with each other. To be done. When the FWD that is connected in anti-parallel to the IGBT reversely recovers, the surge voltage or the like caused by the wiring inductance is avoided, and the IGBT is
A snubber circuit is provided in parallel with the series circuit of the IGBT in order to protect the self-extinguishing type power semiconductor such as T and prevent malfunction of the control circuit.

Here, in the snubber circuit, one set of snubber circuits is connected in parallel to one set of IGBT series circuits like the snubber circuits 10, 20, 30 shown in FIG. 5, or FIG. It is known that a snubber circuit 10 'composed of a resistor 3 ", a diode 4", and a capacitor 5 "is connected to each IGBT. One direction is a diode characteristic, and the other direction is a constant voltage source Zener. By utilizing the characteristics of the diode, it is possible to obtain the effect as a snubber circuit by connecting the series circuit of the Zener diode and the capacitor in parallel to the series circuit of the IGBT or by connecting to each IGBT. Japanese Patent Application Laid-Open No. 3-
It is known from Japanese Patent No. 136412.

Generally, an inductive load represented by an induction motor is often connected to the load of the voltage source inverter, and when the inductive load is connected, the basic operation of the inverter circuit is equal to the operation of the chopper circuit. . Therefore,
The conventional technique will be described below based on the chopper circuit.
FIG. 6 is a circuit diagram of a chopper circuit using an IGBT.
1 is a DC power supply, 2 is an IGBT, 3 is a resistor, 4 is a diode, 5 is a capacitor, 7 is a FWD, and 9 is an inductive load. The snubber circuit 10 is composed of the resistor 3, the diode 4 and the capacitor 5. IGBT2, snubber circuit 1
0 and the diode 7 form a closed loop, and its inductance is the wiring inductance 81.

FIG. 8 is a circuit diagram in which a chopper circuit using an IGBT is connected to the snubber circuit which is the series circuit of the Zener diode and the capacitor described above. 6 is the same as the circuit configuration shown in FIG. 6 except that the snubber circuit 10 is changed to a snubber circuit 10 "by a series circuit of a Zener diode 4'and a capacitor 5 '. Here, an operation waveform diagram of the chopper circuit shown in FIG. Then, the operation of the chopper circuit of Fig. 6 will be described based on the waveforms of the current I _DF and voltage V _DF of the FWD 7 shown in Fig. 10. In Fig. 9, the load current I _L flows through the FWD 7 while the IGBT 2 is off. In the chopper circuit, the IGBT2 is turned on again while the current is flowing to the FWD 7. In Fig. 10, when the IGBT2 is turned on at t = 0, I _DF starts to decrease, and the FWD 7 causes the reverse current (reverse current). (Recovery current) is passed for a period of t ₁ to t ₃ , that is, after the reverse recovery period has passed, the arc is extinguished.

[0007]

In semiconductor elements such as power transistors that have been conventionally used, since the switching time is slower than the reverse recovery period of FWD, a sharp change in current and voltage during the reverse recovery period of FWD does not occur. , Has been suppressed by this switching time. But IGB
Since the switching time of T is almost the same as the reverse recovery period of FWD, changes in current and voltage are not suppressed during this reverse recovery period.

At the end of the reverse recovery period, the wiring inductance 8
1 (the inductance is L _S ) and the voltage ΔV generated by the current change rate dI _DF / dt of the reverse recovery current of the FWD 7 is represented by the equation (1), and ΔV = L _S × dI _DF / dt (1) This ΔV Is superposed on the power supply voltage Ed of the main circuit, and a very high voltage V _DP expressed by the equation (2) is generated.

V _DP = ΔV + Ed = L _S × dI _DF / dt + Ed (2) If this voltage V _DP exceeds the breakdown voltage of the semiconductor element, the semiconductor element is destroyed. Since the voltage of the FWD changes in an extremely short time, the voltage change rate dV _DF / dt may be very high and may be 10 × 10 ³ [V / μS] or more, which causes the drive circuit and the control device. There is a problem in that malfunctions of

The present invention has been made in view of the above problems of the prior art. Even when an element such as an IGBT having a short switching time is used in a power converter such as a voltage type three-phase PWM inverter, the element An object of the present invention is to provide a snubber circuit that prevents destruction and malfunction of a drive circuit and a control device.

[0011]

In order to achieve the above object, according to the present invention, in addition to a snubber circuit according to the prior art (hereinafter referred to as a first snubber circuit), a snubber circuit including only a capacitor (hereinafter referred to as a snubber circuit) is used. , Second snubber circuit) is connected in parallel to a self-extinguishing type power semiconductor device connected between the positive and negative electrodes of the power supply.

Furthermore, the capacitance of the capacitor forming the second snubber circuit is selected so that the reverse voltage recovery time of the FWD and the time when the discharge of the capacitor forming the second snubber circuit ends are equal. Alternatively, the capacity of the capacitor forming the second snubber circuit is selected so that the time when the reverse recovery current of the FWD becomes maximum is equal to the time when the voltage of the capacitor forming the second snubber circuit becomes minimum. .

[0013]

In general, when the FWD is in the ON state, this F
When the IGBT that opposes the WD is turned on, the power supply is short-circuited. In this case, the current reduction rate of FWD-dI _DF / dt is F
Depending on the voltage applied to WD, as the circuit voltage decreases, the current reduction rate of FWD also decreases.

According to the snubber circuit of the present invention, the voltage applied to the FWD becomes the capacitor voltage of the second snubber circuit, and during the power supply short-circuit period, a current flows due to the discharge of the capacitor of the second snubber circuit, and the voltage of the capacitor. Will fall. As the capacitor voltage decreases, the FWD current decrease rate −dI _DF / dt also decreases, and the FWD reverse recovery current and the reverse recovery current change rate dI _DF / dt decrease.

Therefore, the second snubber circuit, the IGBT, the FW
The voltage ΔV represented by the equation (1) generated by the wiring inductance L _{1 of the} closed loop formed of D is suppressed. Further, the main circuit voltage superimposed on the voltage ΔV is not the power supply voltage Ed, but the capacitor voltage V _C1 of the second snubber circuit.
become. Since the capacitor voltage V _C1 of the second snubber circuit is lowered by the discharge, its value is lower than the power supply voltage Ed. Therefore, the voltage value V _DP applied at the end of the reverse recovery period, that is, the sum of the voltage ΔV and the capacitor voltage of the second snubber circuit can be reduced, and the voltage value V _DP does not exceed the breakdown voltage of the semiconductor element.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a voltage type three-phase inverter according to the present invention. In addition to the conventional circuit shown in FIG. 5, the voltage type three-phase inverter of FIG. 1 is connected with capacitors 16, 26 and 36 forming a second snubber circuit. Other elements having the same functions as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

As described above, the basic operation when the inductive load is connected to the voltage source inverter can be replaced with the operation of the chopper circuit, and the operation of the snubber circuit of the present invention, particularly the operation of the second snubber circuit will be described. Description will be made based on the operation of the chopper circuit shown in FIG. In FIG. 2, 6 is the second
A capacitor forming a snubber circuit, 82 is a wiring inductance of the main circuit, and 83 is a closed-loop wiring inductance (inductance L ₁ ) composed of the IGBT, the FWD and the capacitor 6. The second snubber circuit is connected in parallel with the first snubber circuit including the resistor 3, the diode 4 and the capacitor 5. The other elements having the same functions as those of the conventional circuit of FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 3 shows current / voltage waveforms of the capacitor 6 and the FWD 7 immediately after the IGBT 2 in the chopper circuit shown in FIG. 2 is turned on. In FIG.
When the GBT 2 turns on at t = 0, the current I _DF flowing through the FWD 7 begins to decrease, and I _DF = 0 at t = t ₁ . At this time, the FWD 7 and the IGBT 2 connected between the positive and negative electrodes of the power supply are simultaneously turned on, resulting in a power supply short circuit. Therefore, the electric charge accumulated in the capacitor 6 is discharged, the current I _C1 flows to the FWD 7 side, and the terminal voltage V _C1 of the capacitor 6 decreases.

Next, reverse recovery current begins to flow after I _DF = 0 at t = t ₁ , reaches the maximum value I _rp at t = t ₂ , and then I _DF = 0 again at t = t ₃ . , FWD
7 is turned off. Until FWD7 reverse recovers
A voltage represented by the formula (3) is generated between the anode and the cathode of the FWD 7.

V_DF= L₁× dI_DF/ Dt + V_C1 (3) However, dI_DF/ Dt is the current change rate of the reverse recovery current.
Here, V that is the main circuit voltage_C1Capacitor 6 has a short power supply
It is lower than the DC power supply voltage Ed due to the discharge associated with the
And the current change rate of FWD7 that depends on the main circuit voltage-dI
_DF/ Dt also becomes low. Therefore, t = t₂Reverse recovery in
Maximum current I _rpAlso becomes smaller.

Therefore, while the FWD 7 reversely recovers, the capacitor 6 of the second snubber circuit is discharged, so that the FWD
The voltage V _DF generated at both ends of 7 is suppressed, and an excessive voltage exceeding the withstand voltage of the semiconductor element is not generated. That is,
This means that if the voltage V _{C1 of the} capacitor 6, which is the main circuit voltage, decreases, the voltage V _DF generated across the FWD 7 is suppressed.

T> t₃Will recharge the capacitor 6
It is a period of time. Capacitor 6 is a wiring inductor for the main circuit
Is charged by the sensor. Where V_DF≒ V_C1Because
Voltage change rate between anode and cathode of FWD7 dV_DF/
dt does not become too large. Therefore, the second snubber circuit
The maximum reverse recovery current I _rpTake
t = t₂At the voltage V of capacitor 6_C1Is the smallest
Such a capacity, or I_DF= 0 and FWD7
Turns off t = t₃Out of the condenser 6
Current I_C1Is I_C1Select a capacity such that = 0
The voltage V generated across the FWD 7 due to_DFIs suppressed
It

[0023]

As described above, in the snubber circuit of the present invention, a second snubber circuit including a capacitor is provided in addition to the conventional snubber circuit, and the capacitor capacity of this second snubber circuit is appropriately selected. By doing so, the excessive surge voltage that has been generated at the time of reverse recovery of FWD,
The voltage change rate dV _DF / dt can be suppressed.

Thus, even when an element such as an IGBT having a short switching time is used in a power converter such as a voltage type three-phase PWM inverter, a malfunction of a drive circuit and a controller is prevented and a power semiconductor element or the like is prevented from being destroyed. You can

[Brief description of drawings]

FIG. 1 is a configuration diagram of a voltage type three-phase inverter using a snubber circuit according to the present invention.

FIG. 2 is a configuration diagram of a chopper circuit using a snubber circuit according to the present invention.

[Figure 3] Current / voltage waveform diagram of chopper circuit

FIG. 4 is a configuration diagram of a chopper circuit using a snubber circuit according to the present invention.

FIG. 5 is a configuration diagram of a conventional voltage-type three-phase inverter

FIG. 6 is a configuration diagram of a conventional chopper circuit.

FIG. 7 is a block diagram of a conventional inverter (for one arm)

FIG. 8 is a configuration diagram of a conventional chopper circuit.

FIG. 9 is an operation waveform diagram of a conventional chopper circuit.

FIG. 10 is a current / voltage waveform diagram of a diode of a conventional chopper circuit.

[Explanation of symbols]

 1 DC power supply 2 IGBT 3,3 "resistance 4,4" diode 4'zener diode 5,5 ', 5 "capacitor 6 capacitor 7 diode 9 inductive load 10, 20, 30 first snubber circuit 11, 21, 31 IGBT 12,22,32 IGBT 13,23,33 Resistor 14,24,34 Diode 15,25,35 Capacitor 16,26,36 Second snubber circuit capacitor 17,27,37 Free wheeling diode 18,28,38 Free Wheeling diode 81 Wiring inductance 82 Main circuit wiring inductance 83 Closed loop wiring inductance

Claims (6)

[Claims] 1. A snubber circuit of a power converter using a self-extinguishing type power semiconductor element, wherein a first snubber circuit and a second snubber circuit composed of only a capacitor are connected between the positive and negative electrodes of a power supply. The self-extinguishing type power semiconductor device connected in parallel, the time until reverse recovery of the freewheeling diode connected in anti-parallel to the self-extinguishing type power semiconductor device, and the second The snubber circuit is characterized in that the capacitance of the capacitor is selected so that the time for discharging the capacitor constituting the snubber circuit is equal. 2. A snubber circuit of a power converter using a self-extinguishing type power semiconductor device, wherein a first snubber circuit and a second snubber circuit composed of only a capacitor are connected between the positive and negative electrodes of a power supply. Connected in parallel to the self-arc-extinguishing power semiconductor device, the reverse recovery current of the freewheeling diode connected in anti-parallel to the self-extinguishing power semiconductor device is the maximum time, A snubber circuit characterized in that the capacitance of the second snubber circuit is selected such that the time at which the voltage of the capacitor is lowest becomes equal. 3. The snubber circuit according to claim 1 or 2, wherein the first snubber circuit comprises a resistor, a diode and a capacitor. 4. The snubber circuit according to claim 1, wherein the first snubber circuit is composed of a series circuit of a Zener diode and a resistor. 5. The snubber circuit according to claim 1, wherein the power conversion device is a voltage type three-phase PWM inverter. 6. The snubber circuit according to claim 1, wherein the power conversion device is a chopper circuit.