JPH06112336A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06112336A JPH06112336A JP25874492A JP25874492A JPH06112336A JP H06112336 A JPH06112336 A JP H06112336A JP 25874492 A JP25874492 A JP 25874492A JP 25874492 A JP25874492 A JP 25874492A JP H06112336 A JPH06112336 A JP H06112336A
- Authority
- JP
- Japan
- Prior art keywords
- polyparaxylylene
- thin film
- semiconductor device
- film
- dielectric constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は弗素化ポリパラキシリレ
ンを層間絶縁膜として使用する半導体装置の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using fluorinated polyparaxylylene as an interlayer insulating film.
【0002】大量の情報を迅速に処理する必要から、情
報処理装置の主体を構成する半導体装置は単位素子の小
形化による集積化が進んでLSIやVLSIが実用化さ
れている。Since it is necessary to process a large amount of information quickly, the semiconductor device that constitutes the main body of an information processing device has been integrated by miniaturization of unit elements, and LSI and VLSI have been put to practical use.
【0003】こゝで、単位素子の小形化による集積化は
配線パターンの微細化と多層化により行なわれている。
すなわち、導体線路の最小線幅はサブミクロン(Sub-mi
cron) に及んでおり、また、各単位素子間を結ぶ導体線
路は錯綜することから立体配線構造がとられている。Here, the integration by miniaturization of the unit element is carried out by making the wiring pattern finer and multilayering.
That is, the minimum line width of the conductor line is
Cron), and the conductor lines that connect the unit elements are complicated, so a three-dimensional wiring structure is adopted.
【0004】一方、これら半導体装置を装着する多層配
線基板についても高密度実装が可能なマルチチップモジ
ール(MCM)の開発が進められている。本発明は立体
構造を構成する層間絶縁膜に関するものである。On the other hand, the development of a multi-chip module (MCM) capable of high-density mounting is under way even for a multilayer wiring board on which these semiconductor devices are mounted. The present invention relates to an interlayer insulating film forming a three-dimensional structure.
【0005】[0005]
【従来の技術】層間絶縁膜を構成する材料の必要条件
は、 絶縁抵抗値が高いこと、 誘電率が小さなこ
と、 耐熱性が優れていること、などであり、無機絶
縁材料としては二酸化硅素(SiO2),窒化硅素(Si3N4)
, 燐硅酸ガラス( 略称PSG)などが、また、有機絶縁材料
としてはポリイミドなどが使用されている。2. Description of the Related Art Necessary conditions for a material forming an interlayer insulating film are high insulation resistance value, low dielectric constant, excellent heat resistance, etc. As an inorganic insulating material, silicon dioxide ( SiO 2 ), silicon nitride (Si 3 N 4 )
Thus, phosphosilicate glass (abbreviated as PSG) is used, and polyimide is used as the organic insulating material.
【0006】こゝで、集積化が進み、また信号の周波数
が増加するに従って、誘電率の小さなことの必要性が益
々増加してきた。すなわち、高集積化によって層間絶縁
膜の厚さが1μm 以下になっている現在、層間絶縁膜を
挟んで上下に対向して電極や配線が存在する場合は次式
で表される静電容量(C)のために漏話(Cross-talk)
が生ずるが、この場合、静電容量(C)の大きさは誘電
率(ε)に比例している。[0006] Here, as the integration progresses and the frequency of the signal increases, the need for a small dielectric constant is increasing more and more. That is, when the thickness of the interlayer insulating film is 1 μm or less due to high integration, when the electrodes and wirings are vertically opposed to each other with the interlayer insulating film interposed, the capacitance ( Cross-talk for C)
In this case, the magnitude of the electrostatic capacitance (C) is proportional to the dielectric constant (ε).
【0007】 C=εA/3.6 πd (pF)・・・・・・・(1) こゝで Aは対向する電極の面積(cm2) dは厚さ(cm) また、電子回路を通る信号の遅延時間(τ) はできるだ
け小さいことが必要であるが、この遅延時間(τ) は次
式で表されるように電子回路が形成されている基板の誘
電率(ε)に比例することから、誘電率の少ない材料を
使用する必要がある。C = εA / 3.6 πd (pF) ... (1) where A is the area of the opposing electrodes (cm 2 ) d is the thickness (cm), and the signal passing through the electronic circuit The delay time (τ) of is required to be as small as possible, but this delay time (τ) is proportional to the dielectric constant (ε) of the substrate on which the electronic circuit is formed, as expressed by the following equation. , It is necessary to use a material with a low dielectric constant.
【0008】 τ∝=ε1/2 /c ・・・・・・・(2) こゝでcは光の速度 以上のことから、層間絶縁膜の構成材料としては誘電率
(ε)の小さなことが必要であるが、SiO2やSi3N4 など
の無機絶縁材料は一般に耐熱性が優れ、また高い絶縁抵
抗値を示すものゝ、一般に誘電率が大きく、最も小さな
材料であるSiO2でも誘電率値は3.8 である。Τ∝ = ε 1/2 / c (2) Here, c is higher than the speed of light, so that the dielectric constant (ε) is small as a constituent material of the interlayer insulating film. However, inorganic insulating materials such as SiO 2 and Si 3 N 4 generally have excellent heat resistance and high insulation resistance, and even if SiO 2 is the smallest material, it generally has a large dielectric constant. The permittivity value is 3.8.
【0009】一方、有機絶縁材料であるポリイミドは誘
電率が3.2 と無機絶縁材料に較べると小さく、層間絶縁
膜の構成材料として適している。然し、ポリイミドなど
有機絶縁材料を使用する上での問題はカバレッジ(Cover
age)の悪いことである。On the other hand, polyimide, which is an organic insulating material, has a dielectric constant of 3.2, which is smaller than that of an inorganic insulating material, and is suitable as a constituent material of an interlayer insulating film. However, the problem with using organic insulating materials such as polyimide is the coverage (Cover
age) is bad.
【0010】すなわち、被処理基板への被覆法として
は、有機溶媒に溶解した有機絶縁材料をスピンコート法
により被処理基板上に被覆する方法が一般的であり、ポ
リイミドの場合はヒドラジンなどの溶媒に溶解してスピ
ンコートが行なわれているが、この特徴として図3に示
すように半導体基板1の上にパターン形成されている第
1層目の配線2による凹凸に拘らず、ポリイミド膜3の
表面は平坦に形成されることである。That is, as a method of coating the substrate to be processed, a method of coating an organic insulating material dissolved in an organic solvent on the substrate to be processed by a spin coating method is generally used. In the case of polyimide, a solvent such as hydrazine is used. As a characteristic of this, spin coating is carried out by dissolving in the polyimide film 3 regardless of the unevenness due to the wiring 2 of the first layer patterned on the semiconductor substrate 1 as shown in FIG. The surface is to be formed flat.
【0011】こゝで、配線2の線幅は集積度の向上と共
に微小化しているが、半導体素子を駆動するに必要な電
流量は一定に保持する必要があることから、配線のアス
ペクト比(高さ/幅)は益々大きくなる傾向にある。Here, although the line width of the wiring 2 is becoming finer as the degree of integration is improved, the amount of current required to drive the semiconductor element must be kept constant. The height / width) tends to increase.
【0012】こゝで、第1層の配線2の直上に第2層の
配線2が存在する場合は、介在するポリイミド膜3の厚
さが極端に薄くなるために相互間の静電容量が増大する
と云う問題がある。When the second-layer wiring 2 is present immediately above the first-layer wiring 2, the intervening capacitance of the polyimide film 3 is extremely thin, and therefore the mutual capacitance is increased. There is a problem that it will increase.
【0013】一方、気相成長法で成膜する場合は下地基
板の凹凸に比例して相似形の膜成長が行なわれることか
ら、この目的に適している。そこで、ポリイミドよりも
更に誘電率が少なく且つ気相成長法で成膜が可能な有機
絶縁材料が層間絶縁膜の構成材料として必要である。On the other hand, when the film is formed by the vapor phase epitaxy method, a film having a similar shape is grown in proportion to the unevenness of the underlying substrate, which is suitable for this purpose. Therefore, an organic insulating material having a dielectric constant smaller than that of polyimide and capable of forming a film by a vapor phase growth method is required as a constituent material of the interlayer insulating film.
【0014】[0014]
【発明が解決しようとする課題】集積度が向上し多層構
造をとる半導体装置の層間絶縁膜としては誘電率が小さ
く、且つカバレジの良い材料が必要である。A material having a small dielectric constant and good coverage is required for an interlayer insulating film of a semiconductor device having an improved integration degree and a multilayer structure.
【0015】こゝで、スパッタ法や気相成長法で成膜が
可能な材料としてSiO2,Si3N4 ,PSG などの無機絶縁材
料が公知であるが、これらの材料はカバレジは良いもの
ゝ、誘電率が大きく、一方、ポリイミドは誘電率は比較
的小さいものゝ、カバレジが悪いと云う問題がある。Here, inorganic insulating materials such as SiO 2 , Si 3 N 4 and PSG are known as materials that can be formed into a film by the sputtering method or the vapor phase growth method, but these materials have good coverage. "Although the permittivity is large, on the other hand, polyimide has a relatively low permittivity," but it has a problem of poor coverage.
【0016】そこで、ポリイミドよりも誘電率が小さく
且つカバレジの良い材料を実用化することが課題であ
る。Therefore, it is an object to put into practical use a material having a smaller dielectric constant than polyimide and good coverage.
【0017】[0017]
【課題を解決するための手段】上記の課題はジパラキシ
リレンガスを熱分解して得たパラキシリレンラジカルを
第1の配線層が形成してある半導体基板上に導入し、第
1の配線層上で重合させてポリパラキシリレンの薄膜を
形成した後に、この薄膜を弗素化して弗素化ポリパラキ
シリレンとし、この薄膜を層間絶縁膜として使用するこ
とを特徴として半導体装置の製造方法を構成することに
より解決することができる。The above-mentioned problems are solved by introducing para-xylylene radicals obtained by thermally decomposing diparaxylylene gas onto a semiconductor substrate having a first wiring layer formed thereon. A method for manufacturing a semiconductor device characterized in that after a thin film of polyparaxylylene is polymerized on a wiring layer to form a thin film of fluorinated polyparaxylylene, the thin film is used as an interlayer insulating film. Can be solved by configuring
【0018】[0018]
【作用】発明者は図1の一般式(5)で表されるポリパ
ラキシリレンに着目した。ポリパラキシリレンはパリレ
ンの名でユニオン・カーバイド社より市販されている材
料であって、誘電率は約2.6 とポリイミドより小さく、
気相成長法により作ることができる。The inventor has paid attention to the polyparaxylylene represented by the general formula (5) in FIG. Polyparaxylylene is a material marketed by Union Carbide under the name of Parylene, and has a dielectric constant of about 2.6, which is smaller than that of polyimide.
It can be made by the vapor growth method.
【0019】その作り方を述べると、図1の(3)式に
示すジパラキシリレンを原料とし、この原料を入れた容
器内を真空排気して減圧すると共にに加熱して蒸発せし
め、この蒸気を約700 ℃に加熱すると(4)式に示すパ
ラキシリレンラジカルに分解する。The method for producing the same will be described. The raw material is diparaxylylene represented by the formula (3) in FIG. When it is heated to ℃, it decomposes into para-xylylene radicals represented by the formula (4).
【0020】次に、このパラキシリレンラジカルを室温
に導くと重合が進行して(5)式に示すポリパラキシリ
レンを得ることができる。このポリパラキシリレンはカ
バレジ性が優れていることから、LSIなどの半導体装
置において、パッケージの表面に被覆してα線などによ
る放射線障害を防ぐ方法が提案されている。(例えば特
開昭57-99758)然し、ポリパラキシリレンの問題点は耐
熱性は約400 ℃と優れているものゝ、この値はN2中或い
はH2中のような不活性ガス雰囲気中での値であって、大
気中での耐熱性は不充分である。Next, when this para-xylylene radical is brought to room temperature, the polymerization proceeds and polyparaxylylene represented by the formula (5) can be obtained. Since this polyparaxylylene has excellent coverage, a method of covering the surface of the package of a semiconductor device such as an LSI to prevent radiation damage due to α rays or the like has been proposed. (For example, JP-A-57-99758) However, the problem with polyparaxylylene is that it has an excellent heat resistance of about 400 ° C. This value is in an inert gas atmosphere such as N 2 or H 2. The heat resistance in the atmosphere is insufficient.
【0021】そこで、発明者はこのポリパラキシリレン
を弗素化し、図1の(6)式に示すようにフェニール基
を構成する水素(H)原子を弗素(F)原子に置換する
ことにより大気中での耐熱性を向上するものである。Therefore, the inventor fluorinated the polyparaxylylene and replaced the hydrogen (H) atom constituting the phenyl group with a fluorine (F) atom as shown in the formula (6) of FIG. It improves the heat resistance of the inside.
【0022】なお、フェニール基のH原子の置換位置と
置換量は任意であって(6)式は一例に過ぎない。この
ように弗素化すると、これにより耐熱性が向上すると共
に誘電率も約2.3程度にまで低下させることができる。The substitution position and substitution amount of the H atom of the phenyl group are arbitrary, and the formula (6) is merely an example. Such fluorination improves heat resistance and reduces the dielectric constant to about 2.3.
【0023】[0023]
【実施例】実施例1:図2は半導体基板上の層間絶縁膜
としてポリパラキシリレン膜を気相成長法で形成する装
置の構成を示している。EXAMPLE 1 FIG. 2 shows the structure of an apparatus for forming a polyparaxylylene film as an interlayer insulating film on a semiconductor substrate by a vapor phase growth method.
【0024】すなわち、試料管5にジパラキシリレン6
を入れ、ヒータ7により160 ℃に加熱すると、ジパラキ
シリレン6は昇華を始める。コック8を開き、昇華して
きたジパラキシリレン6をヒータ9で約600 ℃に加熱す
るとジパラキシリレンは分解してパラキシリレンラジカ
ルとなる。That is, diparaxylylene 6 is added to the sample tube 5.
Then, when heated to 160 ° C. by the heater 7, the diparaxylylene 6 starts sublimation. When the cock 8 is opened and the sublimed diparaxylylene 6 is heated to about 600 ° C. by the heater 9, the diparaxylylene is decomposed into paraxylylene radicals.
【0025】このパラキシリレンラジカルを減圧してい
る堆積チャンバ10の中に導くと、そこには約25℃の温度
に水冷されているステージ11があり、この上に半導体基
板12が載置してあるが、この上でパラキシリレンラジカ
ルの重合が進行してポリパラキシリレンの薄膜を得るこ
とができる。When the paraxylylene radical is introduced into the deposition chamber 10 under reduced pressure, there is a stage 11 which is water-cooled to a temperature of about 25 ° C., on which a semiconductor substrate 12 is placed. However, the polymerization of para-xylylene radicals proceeds on this, and a thin film of poly-para-xylylene can be obtained.
【0026】この状態で30分処理して厚さが3μm の薄
膜を得ることができた。次に、ポリパラキシリレンの薄
膜の付いた基板をF2ガス5%濃度のN2ガス中で常温で30
分処理することにより弗素化を行なうことができた。In this state, the film was treated for 30 minutes to obtain a thin film having a thickness of 3 μm. Next, the substrate with the thin film of polyparaxylylene was used at room temperature in N 2 gas with F 2 gas 5%
Fluorination was able to be performed by carrying out a minute treatment.
【0027】このようにして得た弗素化ポリパラキシリ
レンは大気中で400 ℃以上の耐熱性をもち、また誘電率
も約2.3 程度に下げることができた。 実施例2:実施例1の方法によりSi半導体基板上に厚さ
が3μm のポリパラキシリレン薄膜を形成した後、この
基板をプラズマ処理装置の下流位置に置き、プラズマ処
理装置に三弗化窒素(NF3)を供給すると共に排気系によ
り1torrに減圧した状態でマイクロ波を750 Wの出力で
照射してプラズマを作り、ダウンフロー位置で40分処理
して弗素化を行なった。The thus-obtained fluorinated polyparaxylylene had a heat resistance of 400 ° C. or higher in the atmosphere, and the dielectric constant could be reduced to about 2.3. Example 2 After a polyparaxylylene thin film having a thickness of 3 μm was formed on a Si semiconductor substrate by the method of Example 1, this substrate was placed at a position downstream of the plasma processing apparatus, and nitrogen trifluoride was placed in the plasma processing apparatus. While supplying (NF 3 ) and reducing the pressure to 1 torr by the exhaust system, microwaves were irradiated at an output of 750 W to form plasma, and the plasma was processed at the downflow position for 40 minutes for fluorination.
【0028】このようにして得た弗素化ポリパラキシリ
レンは大気中で400 ℃以上の耐熱性を示し、また誘電率
も約2.3 程度にすることができた。The thus-obtained fluorinated polyparaxylylene exhibited a heat resistance of 400 ° C. or higher in the atmosphere and a dielectric constant of about 2.3.
【0029】[0029]
【発明の効果】本発明の実施により耐熱性が優れ、また
低誘電率の示す層間絶縁膜を得ることができる。According to the present invention, an interlayer insulating film having excellent heat resistance and a low dielectric constant can be obtained.
【図1】本発明に係る弗素化ポリパラキシリレンの形成
を説明した一般式を表わす図FIG. 1 is a general formula illustrating the formation of fluorinated polyparaxylylene according to the present invention.
【図2】ポリパラキシリレン膜形成装置の構成を示す断
面図である。FIG. 2 is a sectional view showing a configuration of a polyparaxylylene film forming apparatus.
【図3】スピンコート法の問題点を説明する断面図であ
る。FIG. 3 is a cross-sectional view illustrating a problem of the spin coating method.
2 配線 3 ポリイミド膜 6 ジパラキシリレン 12 半導体基板 2 Wiring 3 Polyimide film 6 Diparaxylylene 12 Semiconductor substrate
Claims (2)
パラキシリレンラジカルを第1の配線層が形成してある
半導体基板上に導入し、該第1の配線層上で重合させて
ポリパラキシリレンの薄膜を形成した後に該薄膜を弗素
化して弗素化ポリパラキシリレンとし、該薄膜を層間絶
縁膜として使用することを特徴とする半導体装置の製造
方法。1. A paraxylylene radical obtained by thermally decomposing diparaxylylene gas is introduced onto a semiconductor substrate on which a first wiring layer is formed, and polymerized on the first wiring layer. A method for manufacturing a semiconductor device, comprising forming a thin film of polyparaxylylene, fluorinating the thin film to form fluorinated polyparaxylylene, and using the thin film as an interlayer insulating film.
ズマのダウンフローによることを特徴とする請求項1記
載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the thin film is fluorinated by down-flowing a fluorine compound gas plasma.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25874492A JPH06112336A (en) | 1992-09-29 | 1992-09-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25874492A JPH06112336A (en) | 1992-09-29 | 1992-09-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06112336A true JPH06112336A (en) | 1994-04-22 |
Family
ID=17324484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25874492A Withdrawn JPH06112336A (en) | 1992-09-29 | 1992-09-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06112336A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041519A (en) * | 1996-03-26 | 1998-02-13 | Lg Electron Inc | Liquid crystal display device and its manufacture |
US5888905A (en) * | 1997-11-06 | 1999-03-30 | Texas Instruments Incorporated | Integrated circuit insulator and method |
EP0966039A2 (en) * | 1998-06-15 | 1999-12-22 | Kishimoto Sangyo Co., Ltd. | Insulating film for semiconductor device and semiconductor device |
US6130171A (en) * | 1997-11-18 | 2000-10-10 | Nec Corporation | Residue removal process for forming inter-level insulating layer of paraylene polymer without peeling |
US6150284A (en) * | 1997-06-20 | 2000-11-21 | Nec Corporation | Method of forming an organic polymer insulating film in a semiconductor device |
JP2004072049A (en) * | 2002-08-09 | 2004-03-04 | Ricoh Co Ltd | Organic tft element and method of manufacturing same |
-
1992
- 1992-09-29 JP JP25874492A patent/JPH06112336A/en not_active Withdrawn
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041519A (en) * | 1996-03-26 | 1998-02-13 | Lg Electron Inc | Liquid crystal display device and its manufacture |
US6150284A (en) * | 1997-06-20 | 2000-11-21 | Nec Corporation | Method of forming an organic polymer insulating film in a semiconductor device |
US5888905A (en) * | 1997-11-06 | 1999-03-30 | Texas Instruments Incorporated | Integrated circuit insulator and method |
US6130171A (en) * | 1997-11-18 | 2000-10-10 | Nec Corporation | Residue removal process for forming inter-level insulating layer of paraylene polymer without peeling |
US6368412B1 (en) | 1997-11-18 | 2002-04-09 | Nec Corporation | Apparatus with high temperature gas releasing means for vapor deposition of parylene polymer without peeling |
EP0966039A2 (en) * | 1998-06-15 | 1999-12-22 | Kishimoto Sangyo Co., Ltd. | Insulating film for semiconductor device and semiconductor device |
EP0966039A3 (en) * | 1998-06-15 | 2002-10-16 | Kishimoto Sangyo Co., Ltd. | Insulating film for semiconductor device and semiconductor device |
JP2004072049A (en) * | 2002-08-09 | 2004-03-04 | Ricoh Co Ltd | Organic tft element and method of manufacturing same |
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