JPH06110854A - Parallel computer device - Google Patents

Abstract

PURPOSE:To provide a new digital computer system which can simultaneously process plural programs in parallel with each other and at a high speed. CONSTITUTION:An arithmetic processor 11 is provided to serve as a host processor together with the arithmetic processing elements 12a and 12b surrounding the processor 11, and the memory banks 14 which are usually connected to the bus lines of both elements 12a and 12b and then can be connected to the bus line of the processor 11 after the separation from the bus lines of the elements 12a and 12b by a switch 13. The switch 13 functions to connect the banks 14 o the host arithmetic processor or an arithmetic processor. Then a controller 15 is added to control the switch 13 through the host arithmetic processor. In such a constitution, a parallel computer is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer system. More specifically, the present invention relates to a new digital computer system capable of simultaneously processing a plurality of programs in parallel at high speed.

[0002]

2. Description of the Related Art Various attempts have been made so far for the purpose of speeding up computer processing. One of the means for realizing such high-speed processing is to speed up the processing speed of the arithmetic element, and the other means is to increase the number of arithmetic processing devices to a high degree to speed up the processing as a whole. Is aimed at. However, under the present circumstances, the processing speed of the arithmetic element has been increased to near the limit of its possibility, and a dramatic improvement in the processing speed cannot be expected. On the other hand, with the improvement of the LSI manufacturing technology, a considerable problem has been solved and the possibility has been opened up regarding the increase in the number of elements constituting the system.

Under these circumstances, at present, a method for increasing the speed of a computer system by increasing the number of arithmetic processing devices is considered promising. In the case of a parallel computer having a plurality of arithmetic processing devices, theoretically, if n arithmetic processing elements having the same arithmetic processing speed are used, a processing speed of n times as a whole can be obtained. However,
In practice, it is difficult to uniformly control the respective arithmetic processing elements, and the mutual coupling method between the respective arithmetic processing elements poses a problem. Therefore, it is difficult to obtain a processing speed proportional to the number of the arithmetic processing elements. It's actually very difficult.

The mutual coupling methods for exchanging data between the respective arithmetic processing elements that have been studied so far are roughly divided into (1) common bus method (2) switching method (3) specific operation It is classified as a connection between processing elements. In the case of the common bus system (1) among these, each arithmetic processing element is connected to the common bus,
A memory that can be commonly used by the respective arithmetic processing elements is also connected. Then, data is exchanged between the arithmetic processing elements via the common memory. Although this method has an advantage that data can be exchanged at high speed, it cannot connect too many arithmetic processing elements to the common bus, and further, it requires the control of the bus right. There is. Also,
In the case of the switching method (2), a switch such as a multi-stage switching network is used to couple arbitrary arithmetic processing elements. The switch in this case would play a role similar to a telephone switch such as a crossbar switch.
In this switching method (2), the hardware of the switching circuit network becomes enormous when the number of arithmetic processing elements increases, and it is necessary to control the switches, and the data transfer rate is not so fast. There is. Furthermore, a specific inter-processing element coupling (3)
In the above, mutual coupling is limited to specific arithmetic processing elements, which is clear in terms of hardware, but there is a restriction that the use is limited to special ones.

As described above, each of the mutual coupling methods has advantages and disadvantages. For this reason, in the current parallel computer system, a configuration is adopted in which these methods are used together to make up for their respective disadvantages.

[0006]

As described above, in the parallel computer, the construction of the mutual coupling method between the respective arithmetic processing elements has become a very important issue, and ideally, in the mutual coupling method. (1) data can be exchanged at high speed between arbitrary arithmetic processing elements, (2) data exchange can be easily controlled, and (3) hardware for realizing mutual coupling is simple. It is required to have a structure and to have a degree of freedom of expansion in addition of arithmetic processing elements. However, as described above, none of the parallel computers having the arithmetic processing elements of a certain scale or more, which have been proposed or studied so far, satisfy all such requirements.

The present invention has been made in view of the above circumstances, solves the drawbacks of the conventional apparatus, enables high-speed processing, can be easily operated and controlled, and has simpler hardware. It is an object of the present invention to provide a parallel computer device having a new mutual coupling method that enables a configuration.

[0008]

In order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by one arithmetic processing unit serving as a host, some arithmetic processing elements surrounding this arithmetic processing unit, and a host arithmetic processing unit. And a number of memory banks that can be connected to the selected arithmetic processing unit or element by selecting one of the arithmetic processing elements by a switch, and this memory bank is connected to either the host arithmetic processing unit or the arithmetic processing element. There is provided a parallel computer device comprising a switch device for coupling and a control device for controlling the switch device from a host arithmetic processing device.

[0009]

In the parallel computer system according to the present invention, the host arithmetic processing unit and the arithmetic processing element are connected via the memory bank, and the memory bank is either the host arithmetic processing unit or the arithmetic processing element at a certain time. It is connected by a heel switch, and by switching the switch, it is possible to immediately connect to the host arithmetic processing unit and the arithmetic processing element. The memory bank connected to the arithmetic processing unit or the arithmetic processing element operates as a normal memory of the arithmetic processing unit or the arithmetic processing element. For this reason, data exchange between the arithmetic processing unit and the arithmetic processing elements can be performed at a very high speed in the time for writing data in the memory bank and the time for switching the memory banks.

[0010]

1 is a block diagram illustrating an embodiment of the present invention. For example, as shown in FIG. 1, the parallel computer system of the present invention includes an arithmetic processing unit (11) serving as a host and a number of arithmetic processing element groups (12).
have. Any one of the host arithmetic processing unit (11) and one specific arithmetic processing element (12a, b, c ...) Of the arithmetic processing element group (12) can be operated by the switch (13) to select the memory bank group. It can be connected to the memory bank in (14). The operation of the switch device (13) is controlled by the control device (15) controlled by the host arithmetic processing device (11).

The memory bank group (14) is composed of a plurality of memory banks, and each memory bank can be given a unique bank number (n). And each memory
The bank is connected to the host arithmetic processing unit (11) or the arithmetic processing elements (12a, b, c ...) By the switch (13), and the connection enables the host arithmetic processing unit (11) or the arithmetic processing element (12a). , B, c ...) Is mapped to a specific memory space.

The arithmetic processing elements (12a, b, c ...)
Has the following three states. <A> Execution <B> Reset <C> Hold Execution <A> is a state in which the arithmetic processing element is executing processing according to the code written in the memory of the memory bank connected to the arithmetic processing element. .

The reset <B> state means that control is transferred to a specific address of a certain memory and the execution <A> state is entered regardless of the current state of the arithmetic processing element. The hold <C> state is a state in which the operation of the arithmetic processing element is stopped. When the hold <C> state is released, the arithmetic processing element executes from the previous state <A>
To start.

The three states of such an arithmetic processing element are:
It is exactly the same as the three states of a normal computer. In addition, the host arithmetic processing unit (11) includes an arithmetic processing element (1
2a, b, c ...), a reset signal can be sent. The arithmetic processing elements (12a, b, c ...) Are reset by this reset signal. The initial state of the arithmetic processing elements (12a, b, c ...) Is the hold state.

For more detailed explanation, referring to FIG. 2, a host arithmetic processing unit (11), two arithmetic processing elements (12a) (12b), and one bank have a memory capacity of one.
In a parallel computer system composed of 28 Kbyte memory banks (n0 to n15), first, 16 memory banks (n0 to n15) are set to the arithmetic processing elements (12
a) Connect to the (12b) side. Each of the memory banks having bank numbers (n) 0 to 7 is connected to eight memory spaces separated from the memory address 0 of the arithmetic processing element (12a) by 128 Kbytes. That is, the memory bank n0 has memory addresses 0 to 1FFFF (16
Memory number n1 is memory address 2
0000-3FFFF, memory bank n2 is memory
The addresses 40000 to 5FFFF ..., And the memory bank n7 are connected to the memory addresses E0000 to FFFFF. Similarly, the memory banks n8 to n15 are connected to the arithmetic processing element (12b).
The arithmetic processing element and the memory bank thus connected to the memory space of the arithmetic processing element completely function as one computer. Therefore, in this computer system, a parallel computer system is configured by a total of three computers including the host arithmetic processing unit (11) and two computers including the two arithmetic processing elements (12a) and (12b). Each of the memory banks n0 to 15 is separated from the bus of the arithmetic processing element (12a) (12b) by the switch (13) controlled by the host arithmetic processing unit (11), and is connected to the bus of the host arithmetic processing unit (11). Can be connected. At this time, if the memory address connected to the host arithmetic processing unit (11) is 80000-9FF
It can be FF.

With such a structure, the data exchange between the host arithmetic processing unit (11) and the arithmetic processing elements (12a) (12b) is performed by switching the memory bank switch and the data on the switched memory bank. It becomes possible to execute at high speed by reading / writing. That is, for example, the code to be executed by the arithmetic processing element is stored in the memory bank n0 of the arithmetic processing element (12a).
4, the data for which the code is processed is sent from the host processing unit (11) to the processing element (12a), the code given by the processing element (12a) is executed, and the calculation result is stored in the memory bank n5. It shall be output. At this time, the host arithmetic processing unit (11) first switches the memory bank n0 to the host arithmetic processing unit (11), reads the code from the file, and then the host arithmetic processing unit (11).
Write to memory addresses 80000 to 9FFFF. That is, the code has been written in the memory bank n0. Similarly, data is written in the memory bank n4. After such preparation is completed, the arithmetic processing element (12a) executes the given code and outputs the result to the memory bank n4. Arithmetic processing element (12
When the processing in a) is completed, the memory bank n4 is connected to the host arithmetic unit (11). The host arithmetic processing unit (11) obtains the processing result of the arithmetic processing element (12a).
After obtaining the processing result, the host arithmetic processing unit (11) writes new data to the memory bank n4 and sends it to the arithmetic processing element (12a), and the arithmetic processing element (12a) is based on the given data. Starts the next process. With respect to the arithmetic processing element (12b), the code and data given from the host arithmetic processing unit (11) can be processed by the same procedure. Arithmetic processing element (12
a) and the arithmetic processing element (12b) with the same code to execute different data processing in parallel, first, the memory bank n0 and the memory bank n8 are simultaneously connected to the host arithmetic processing unit (11). , Write code simultaneously to these two memory banks. After that, the respective data are written in the memory bank n4 and the memory bank n12, and the arithmetic processing element (12a) and the arithmetic processing element (12
If the process in b) is started, different data can be processed in parallel.

The changeover switch (13) is used to switch between the host arithmetic processing unit and the arithmetic processing elements of the memory bank, and the changeover switch (13) is entirely controlled by the host arithmetic processing unit (11). In that case,
It is possible to have the following structures and functions. <A> The switch is controlled by the host arithmetic processing unit.

<A> In the initial state, all the switches are connected to the arithmetic processing element side.

<C> When switched to the host arithmetic processing unit side, the following two modes are prepared. (A) WO (Write only) mode (b) RW (read / write) mode <D> In the RW mode, only one memory bank can be connected to the bus of the host arithmetic processing unit.

<E> In WO mode, a plurality of memory banks can be simultaneously connected to the bus of the host processing unit. <F> Prepare a switch status register that indicates the connection status of the memory bank. This register indicates that the memory bank is connected to the host processing unit when, for example, the flag of the bit corresponding to the memory bank is set. When it is not set, it is assumed that it is connected to the processing element side. The host arithmetic processing unit sets the flag of each bit. The flag is reset automatically when the switch is switched from the host processor bus to the processor element side.
Each processing element can read the switch status register of its own memory bank. For a change in the state of each bit of the register, an interrupt signal is generated to the arithmetic processing element having the memory bank corresponding to the changed bit.

<K> There are the following three commands for switching the switch. WO, n Memory n is connected to the host processor bus in WO mode.

RW, n Memory n is connected to the host processor bus in RW mode. RESET Returns the memory connected to the host processing unit to the PE bus. However, n is a memory bank number.

<K> The WO command sequence is as follows.

<1> A flag is set in n bits of the switch status register. <2> If the host arithmetic processing unit has a memory bank connected in the RW mode, this is switched to the arithmetic processing element side. <3> Wait until the interrupt to the arithmetic processing element by the flag of <1> is accepted. However, when the arithmetic processing element is in the hold state, the process immediately proceeds to 4.

<4> Connect memory bank n to the host processor bus.

<X> The sequence of the RW command is as follows. <1> Set a flag in the n-bit of the switch status register. <2> If there is a memory bank connected to the host arithmetic processing unit bus, all of them are switched to the arithmetic processing element side. <3> Wait until the interrupt to the arithmetic processing element due to the flag change of <1> is accepted. However, if the arithmetic processing element is in the hold state, immediately move to the next <4>.

<4> Connect memory bank n to the host processor bus.

<CO> The sequence of the RESET command is as follows. Host processing unit (11)
Switch all memory banks connected to the bus to the processing element side. The arithmetic processing element has the following functions for the switch status register.

1) Corresponds to an interrupt issued for a change in the bit of the switch status register. 2) The contents of the switch status register can be read. 3) Generate an interrupt signal to the host arithmetic processing unit.

An example of control of the parallel computer having the above functions is as follows. That is, in the initial state,
The memory banks n0 to n15 are all processing elements (1
2a) and (12b). The arithmetic processing elements (12a) and (12b) are in the hold state. The host arithmetic processing unit (11) includes an arithmetic processing element (1
2a), sending appropriate code or data to the memory bank of the arithmetic processing element (12b). For each arithmetic processing element (12a) (12b), code and data are written from the host arithmetic processing unit (11) to the memory bank, and the arithmetic processing elements (12a) (12b) are ready to be executed. If so, the host processor (1
1) sends a reset signal to the arithmetic processing elements (12a) (12b). The arithmetic processing elements (12a) and (12b) that have received the reset signal are put into the execution state according to the code and data sent from the host arithmetic processing unit (11). Of course, a certain specific execution code in the arithmetic processing element may be prepared as a ROM.
In this case, in the initial state, the host arithmetic processing unit (11)
A reset signal can be sent immediately from.

The arithmetic processing elements (12a) (12b) receiving the reset signal from the host arithmetic processing unit (11),
In the execution state, the respective arithmetic processing elements operate in parallel. The host arithmetic processing unit (11) and the arithmetic processing element (1
Data communication between 2a and 12b can be performed at high speed by switching memory banks. Since an interrupt signal can be generated from either side to the other
If the bank switching and communication procedures are programmed, both sides can send necessary data to the other party when necessary and can receive the data from the other party.

Data communication between the arithmetic processing elements (12a) and (12b) is performed via the host arithmetic processing unit (11). In this case, the memory bank of the arithmetic processing element (12a) (12b) for sending out data is connected to the host arithmetic processing unit (11), and the data of this memory bank is once copied to the memory of the host arithmetic processing unit (11). After that, the memory bank on the sending side is connected to the host arithmetic processing unit (11) to write the copied data. Efficiently processing elements (12a) (12) without copying to the memory of the host processing unit (11).
b) In order to execute inter-communication, the memory space on the side of the host processing unit (11) connected to the memory bank is set to 8000.
Not only one of 0 to 9FFFF, but a plurality of them may be used. For example, if the memory space of the memory addresses A0000 to BFFFF on the side of the host arithmetic processing unit (11) can also be connected to the memory bank, the memory bank of the source of the data will have memory addresses of 80000 to 9F.
The memory bank on the data receiving side is connected to the memory addresses A0000 to BFFFF. In this way, data transfer between the arithmetic processing elements (12a) and (12b) can be executed by memory transfer in the host arithmetic processing unit (11).

Except for data communication by memory bank switching, the arithmetic processing elements (12a) and (12b) also operate as a complete computer. This means that the arithmetic processing elements (12a) and (12b) are also the host arithmetic processing unit (11).
It means that it can have the same function as. if,
If the arithmetic processing elements (12a) and (12b) have a switch function and a control function having the host arithmetic processing unit (11), as shown in FIG. 3, the arithmetic processing elements (12a)
(12b) also becomes one host arithmetic processing unit (11), and several arithmetic processing elements (for example, 12a)
a, 12ab ...) can be connected. It is possible to increase the number of processing elements in a pyramid shape,
A large-scale parallel computer can be easily constructed.

[0034]

As described above, according to the present invention, a parallel computer including a plurality of arithmetic processing elements connected to one host arithmetic processing unit in a star shape via a memory bank is realized. Each processing element constitutes a completely independent computer. The data transfer between the host processing unit and each processing element can be executed as a memory transfer of data in the host processing unit by connecting the memory bank of the processing element to the host processing unit. Memory bank switching can be executed by one input / output instruction. Therefore, data communication can be performed at extremely high speed. WO
The mode can be used to write data or program code to the memory banks of multiple processing elements at the same time.

Further, since the memory bank switching control is collectively performed by the host arithmetic processing unit, no conflict problem occurs and a simple control procedure results in good efficiency. Further, the arithmetic processing element can be provided with a function as a host arithmetic processing device. By doing so, it becomes possible to connect a plurality of arithmetic processing elements below the arithmetic processing elements, and a large-scale parallel computer system can be easily constructed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a parallel computer system that is an embodiment of the present invention.

[FIG. 2] Two arithmetic processing elements, a memory of 128 Kbytes
3 is a block diagram showing an example of a system configured by block 16. FIG.

FIG. 3 is a system diagram in which arithmetic processing elements are further connected below the arithmetic processing elements and the arithmetic processing elements are arranged in a pyramid shape.

[Explanation of symbols]

 11 Host Arithmetic Processing Unit 12 Arithmetic Processing Element Group 12a, 12b, 12c Arithmetic Processing Element 13 Switch Device 14 Memory Bank Group 15 Switch Control Device

Claims (2)

[Claims] 1. A processor as a host, several processor elements surrounding the processor, and usually a processor element coupled to a bus line of the processor element by a switch. And a number of memory banks that are decoupled from the bus lines of the host processor and can be coupled to the bus lines of the host processor, for coupling this memory bank with either the host processor or the processor elements. A parallel computer device comprising a switch device and a control device for controlling the switch device from a host arithmetic processing device. 2. The digital computer system according to claim 1, wherein when one of the memory banks is coupled to an arithmetic processing element by the switch device, an interrupt signal is generated for the arithmetic processing element and the combined memory. A parallel computer device characterized by comprising a control device for giving bank information.