JPH06110779A - Circuit and system for controlling cache memory access - Google Patents

Abstract

PURPOSE:To provide a cache memory access control circuit which can improve total memory access speed and whose availability as a displaying memory is excellent by avoiding the generation of a cache miss hit at the time of data access. CONSTITUTION:The circuit can transfer data between a memory cell array 1 and the data part 2B of a cache memory 2 altogether through a parallel port. On the other hand, the access circuit 4 previously judges whether a next access becomes a hit or not from the contents of a register 4a and concerning access predicted to miss-hit, the access circuit 4 gives only a line address to a cache memory part before actual access. Following it, the access circuit 4 gives the line address and a column address to the cache memory part so as to surely hit at the time of actual access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory access control circuit and a cache memory access control method, and more particularly to a cache memory access control circuit and a cache memory access control method suitable for computer equipment having a high speed bus interface.

[0002]

2. Description of the Related Art Conventionally, in order to increase the memory access speed, a method has been widely used in which a cache memory is connected via a bus between a main memory and a control circuit such as a CPU and data is accessed from the cache memory. ing. In this method, tag comparison, that is, the row address in the input address and the row address of the data stored in the cache memory are performed each time the memory is accessed. At the same time that the target data was accessed, the row data was transferred to the cache memory.

By the way, in recent years, a high-speed bus interface has been devised and its range of use is expanding. However, when this high-speed bus interface is used together with the above-mentioned cache memory, the tag comparison time or the memory access time at the time of a cache miss becomes a bottleneck, and a sufficient access speed cannot be obtained in utilizing the performance of the high-speed bus interface. The problem occurs. Therefore, a method using a DRAM having a built-in buffer memory is adopted. In this method, for example, a plurality of buffer memories are used as individual cache data areas and a plurality of continuous row data are stored therein. According to this method, if the tag comparison is performed only for the first access and there is a hit, it is possible to successively access the data from the next without tag comparison.

However, in this method, for example, CP
When a plurality of circuits such as U, display controller, and graphic processor are simultaneously accessed, there is a problem that the probability of a miss hit increases. Also,
When this system is used as an image memory, there is a problem that it is difficult to guarantee the time when data can be read without disturbing the display.

[0005]

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem, and it is possible to improve the total memory access speed by avoiding the occurrence of a cache miss at the time of data access. It is an object of the present invention to provide a cache memory access control circuit and a cache memory access control method which are excellent in utility as a display memory.

[0006]

The cache memory access control circuit of the present invention achieves the above-mentioned object.
A memory cell array composed of a matrix of rows and columns, and cache data storage means connected to the memory cell array through a parallel port in the column direction and capable of performing batch transfer of row unit data as cache data between the memory cell array and the memory cell array. A row address storage means for storing a row address of the cache data stored in the cache data storage means; an access circuit for generating a row address and a column address to access the cache data storage means; When the row address stored in the row address storage means is compared with the comparison means for comparing the given row address with the row address stored in the row address storage means, if the row addresses match, the cache data corresponding to the matched row address , The column address given by the access circuit If the row address does not match, the access circuit is notified of this fact, and the corresponding row data is sent from the memory cell array through the parallel port to the cache data storage means. And a control means for updating the row address of the row address storage means.

Further, the access circuit includes storage means for storing the row address stored in the row address storage means,
Based on the row address stored in the storage means, it is determined whether or not the data to be accessed next is stored in the cache data storage means, and the data to be accessed is stored in the cache data storage means. When it is determined that the row address and the column address are transferred to the comparison means and the control means, and when it is determined that the data to be accessed is not stored in the cache data storage means, only the row address is compared. Means for transferring the row address and the column address to the comparison means and the control means after receiving the notification of the row address mismatch from the control means.

In the cache memory access control method of the present invention, a memory cell array composed of a matrix of rows and columns is connected to the memory cell array through parallel ports in the column direction, and a row unit is provided between the memory cell array and the memory cell array. In a method of controlling access to a cache memory having a cache data storage area capable of simultaneous data transfer, it is determined whether data to be accessed next to the cache memory is stored in the cache data storage area. Side, and a step of transferring the row address to the cache memory when the access side determines that the data to be accessed next is not stored in the cache data storage area. Cache hit / cache for different row addresses A step of determining a hit, and a step of simultaneously transferring the data of the row address from the memory cell array to the cache data storage area through the parallel port when a cache mishit is determined for the transferred row address, After batch transfer of the row data from the memory cell array to the cache data storage area, a step of transferring the row address and the column address for which the cache mishit is determined from the access side to the cache memory, and the transfer of the row address to the transferred row address. On the other hand, when a cache hit is determined, the step of determining, as access data, the data of the portion designated by the column address in the cache data corresponding to the matching row address.

[0009]

According to the present invention, the row address given from the access circuit is compared with the row address stored in the row address storage means, and if the row addresses match (hit) as a result of the comparison, the matched row address. The data in the portion designated by the column address given by the access circuit in the cache data corresponding to is determined as access data. When the row addresses do not match (in the case of a mishit), this is notified to the access circuit, and the corresponding row data is simultaneously transferred from the memory cell array to the cache data storage means through the parallel port and the row address storage is performed. Update the row address of the instrument.

On the other hand, the access circuit has storage means for storing the row address stored in the row address storage means,
Based on the row address stored in this storage means, it is determined whether or not the data to be accessed next is stored in the cache data storage means. As a result, when it is determined that the data to be accessed is stored in the cache data storage means, the row address and the column address are transferred to the comparison means and the control means in order to actually perform the data access. If it is determined that the data to be accessed is not stored in the cache data storage means,
When only the row address is transferred to the comparing means, and then the access circuit receives the notification of the row address mismatch from the controlling means, the transferred row address and column address are transferred to the comparing means and the controlling means and the actual access is performed. I do.

That is, the present invention is configured so that row-wise data transfer between the memory cell array and the cache data storage means can be performed simultaneously through the parallel port. Prior to the above, only the row address was sent to the comparison means to cause a mishit, so that the hit was definitely made in the actual access. Here, since the data transfer between the memory cell array and the cache data storage means is performed all at once, the access circuit generates a row address and then generates an address including a row address and a column address after a very short time. Moreover, since the cache data update process at the time of a miss can be performed during the data transfer period by the previous access, the access circuit can process all accesses in substantially the same time. Therefore, when the high-speed bus interface is adopted, it is possible to secure the memory access time necessary for exhibiting the performance of the high-speed bus interface. Also,
When the present invention is used as a display memory, display data can be continuously read out at high speed without disturbing the display.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a cache memory access control circuit according to an embodiment of the present invention.

In the figure, reference numeral 1 is a memory cell array composed of a matrix of rows and columns. The memory cell array 1 is capable of row-based data access and memory cell-based data access by matrix designation. 2 is a cache memory. The cache memory 2 includes a tag unit 2A for holding a row address, a data unit 2B for holding cache data in units of lines corresponding to the tag unit 2A, and whether or not cache data in the data unit 2B is valid. The valid bit portion 2C shown in FIG. Memory cell array 1 and cache memory 2 described above
The data section 2B in the memory cell array 1 is connected to the data section 2B in the cache memory 2 through the parallel port so that data for one row of the memory cell array 1 can be simultaneously transferred. A row address latch 3 temporarily holds a row address given by an access circuit 4 such as a CPU for accessing the cache memory 2. A decoder 5 decodes the row address held in the address latch 3 to decode the memory cell array 1
Specify the line to access. A column address latch 6 temporarily holds the column address given by the access circuit 4. Reference numeral 7 denotes a row address held in the row address latch 3 and the tag unit 2 in the cache memory 2.
It is a comparator for judging hit / miss hit by comparing with the row address stored in A. An interface circuit 8 controls the interface between the cache memory 2 and the access circuit 4. As described above, the cache memory unit in the cache memory access control circuit according to the present embodiment is configured by the components other than the access circuit 4.

The access circuit 4 also has a register 4a for holding the same row address as the row address stored in the tag section 2A in the cache memory 2.

Next, the operation of the cache memory access control circuit of this embodiment will be described with reference to FIGS.
2 is a diagram showing the timing of each signal in this operation, FIG. 3 is a flowchart showing the operation on the side of the access circuit 4, and FIG. 4 is a flowchart showing the operation on the side of the cache memory unit.

It is assumed that the row address is not held in the register 4a in the access circuit 4 immediately after the power is turned on.
As shown in FIG. 2A, when the first memory access is performed (step 301), the access circuit 4 gives only the row address to the cache memory section (step 30).
2).

The row address given by the access circuit 4 is latched in the row address latch 3 at the falling edge of the RAS (ROW ADDRESS STROVE) signal. When the row address is latched in the row address latch 3 (step 401),
The row address and the row address stored in the tag unit 2A in the cache memory 2 are compared by the comparator 7 (step 402). In the first comparison, since there is no cache data in the cache memory 2, a mishit is determined.

When the mishit is determined, the interface circuit 8 informs the access circuit 4 of the mishit.
Send CK (NOT ACKNOWLEDGE) signal (step 40
3). When the access circuit 4 receives this NACK signal (step 303), it stores the row address for which the mishit has been determined this time in the register 4a (step 30).
4). When the interface circuit 8 determines a mishit, the data of the target row address is cached in the data section 2B of the cache memory 2 from the memory cell array 1 through the parallel port based on the decode information of the row address obtained from the decoder 5. As a batch transfer. At the same time, the row address is registered in the tag section 2A corresponding to the data section 2B storing the cache data, and a bit having a value indicating that the cache data is valid is set in the valid bit section 2C (step 404).

After the data transfer from the memory cell array 1 to the cache memory 2 is completed, the access circuit 4 generates an address obtained by adding the column address to the row address which is a hit this time (step 305).

At this time, since the same row address has already been stored in the tag portion 2A of the cache memory 2, the hit is judged by the comparator 7. If a hit is determined, the interface circuit 8 sends an ACK (ACKNOWLEDGE) signal to the access circuit 4 to inform the access circuit 4 (step 405).

On the other hand, the column address in the address given from the access circuit 4 is latched by the column address latch 6 and input to the interface circuit 8. As a result, the data of the target column in the cache data stored in the data section 2B having the matching row address is read as access data (step 406), and the read data is transferred to the access circuit 4 through the interface section 8. (Step 407). During this data transfer, the access circuit 4 determines that the next data to be accessed is the cache memory 2.
Register 4a for determining whether or not it is stored in the data section 2B of
Judging from the contents of (step 301).

When it is determined that the target data is stored in the data section 2B of the cache memory 2, the access circuit 4 generates an address including a row address and a column address and transfers it to the cache memory section. (Step 305).

The target data is the cache memory 2.
When it is determined that the data is not stored in the data section 2B of the access circuit 4, the access circuit 4 transfers only the row address to the cache memory section as in the operation described above, as shown in (b) of FIG. At step 302), a mishit is generated in the comparator 7, and the data of the target row address is transferred all at once from the memory cell array 1 to the data section 2B of the cache memory 2 through the parallel port. At the same time, the row address is registered in the corresponding tag portion 2A, and a bit having a value indicating that the data is valid is set in the valid bit portion 2C (step 404).

After this, the access circuit 4 stores the row address which is a hit this time in the register 4a (step 304), and subsequently, the address including the row address and the column address which is this hit is stored in the cache memory unit. Transfer (step 305).

After the cache memory 2 is once filled,
Data is updated according to an algorithm such as LRU (Least Recently Used). That is, the row data having the lowest access frequency is erased before the new row data is transferred to the cache memory 2, and the new cache data is stored in the area. Therefore, in this case, the access circuit 4 updates the content of the register 4a using the same algorithm in order to make the content of the register 4a in the access circuit 4 follow this. For example, access circuit 4
If a mishit is determined for the transferred address (row address) in anticipation of a more hit, the row address with the lowest access frequency is erased in the register 4a, and this time there is a mishit. Register a new row address. Similarly, when writing data to the data portion 2B of the cache memory 2, the access circuit 4 similarly writes the cache data of the portion to be rewritten in the data portion 2B of the cache memory 2 based on the row address held in the register 4a. Determine whether is stored. If not stored, only the row address is generated before the access and the target row data is transferred from the memory cell array 1 to the data section 2B of the cache memory 2 all at once. After that, the row address and the column address are given to the cache memory unit, the write data is transferred to the cache memory unit, and the data of the corresponding row address in the cache memory 2 is rewritten. After rewriting the data, before the new data is transferred from the memory cell array 1 to the cache memory 2, the rewritten data is returned to the memory cell array 1.

As described above, the cache memory access control circuit of this embodiment is designed so that data transfer between the memory cell array 1 and the data section 2B of the cache memory 2 can be performed simultaneously through the parallel port. In addition, regarding an access in which a mishit is expected, only a row address is given from the access circuit 4 to the cache memory unit before the actual access to cause a mishit.
Then, the row address and the column address are given to the cache memory section so that the actual access is surely hit. Here, since the data transfer between the memory cell array 1 and the data section 2B of the cache memory 2 is performed all at once, the access circuit 4 generates a row address and then, after a very short time, outputs the row address and the column address. It suffices if it occurs, and since the cache data update processing at the time of a miss can be performed during the data transfer period by the previous access, the access circuit 4 processes all accesses to the cache memory 2 in substantially the same time. be able to. Therefore, when the high-speed bus interface is adopted, it is possible to secure the memory access time necessary for exhibiting the performance of the high-speed bus interface.

When the display data is read from the cache memory 2 of this embodiment, the cache data is updated so that the necessary display data is transferred from the memory cell array 1 to the data section 2B of the cache memory 2 during the horizontal blanking period. Should be done. As a result, display data can be read at high speed without disturbing the display.

Further, in this case, a specific area of the cache memory 2 is defined as a storage area dedicated to the display data, and the LRU is controlled so that the display data in the dedicated storage area is not erased by a memory access other than the display data read. The time required for continuous reading of the display data can be more surely guaranteed.

[0030]

As described above, according to the cache memory access control circuit and the cache memory access control method of the present invention, the occurrence of a cache mishit at the time of data access is avoided and the total memory access speed is improved. Can be planned. Further, when the present invention is used as the display memory, the display data can be continuously read out at high speed without disturbing the display.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory access control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing the timing of each signal for explaining the operation of the cache memory access control circuit of FIG.

FIG. 3 is a flowchart showing a procedure of operation of an access circuit.

FIG. 4 is a flowchart showing a procedure of an operation of a cache memory unit.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Cache memory, 2A ...
Tag part, 2B ... Data part, 2C ... Valid bit part, 3
... row address latch, 4 ... access circuit (CPU), 4
a ... register, 5 ... decoder, 6 ... column address latch,
7 ... Comparator, 8 ... Interface circuit.

Claims (3)

[Claims] 1. A memory cell array composed of a matrix of rows and columns, and connected to the memory cell array through a parallel port in the column direction, and row-by-row data can be simultaneously transferred to the memory cell array as cache data. Cache data storage means, a row address storage means for storing a row address of cache data stored in the cache data storage means, and an access circuit for generating a row address and a column address to access the cache data storage means. Comparing means for comparing the row address given by the access circuit with the row address stored in the row address storage means, and if the row addresses match as a result of the comparison by the comparing means, the row address corresponds to the matched row address. Given from the access circuit in the cache data If the row address does not match, the access circuit is notified of this fact, and the corresponding row data is sent from the memory cell array through the parallel port. A cache memory access control circuit, comprising: a control means for performing simultaneous transfer to the cache data storage means and updating the row address of the row address storage means. 2. The cache memory access control circuit according to claim 1, wherein the access circuit stores a row address stored in the row address storage means, and a row address stored in the storage means. On the basis of the above, it is determined whether the data to be accessed next is stored in the cache data storage means, and if it is determined that the data to be accessed is stored in the cache data storage means, the comparison means and the When the row address and the column address are transferred to the control means and it is determined that the data to be accessed is not stored in the cache data storage means, only the row address is transferred to the comparison means, and the row data is transferred from the control means. After receiving the notification of the address mismatch, the row address and the column address are compared with the comparison means and the column address. A cache memory access control circuit having means for transferring to a control means. 3. A memory cell array composed of a matrix of rows and columns, and a cache which is connected to the memory cell array through a parallel port in the column direction and is capable of performing simultaneous data transfer in units of rows with the memory cell array. In a method of controlling access to a cache memory having a data storage area, a step of determining on the access side whether or not data to be accessed next to the cache memory is stored in the cache data storage area, When the access side determines that the data to be accessed to the memory is not stored in the cache data storage area, a step of transferring a row address to the cache memory, and a cache hit / cache miss for the transferred row address The process of determining the hit and the transferred row add If a cache miss hit is determined for the cache memory, a step of simultaneously transferring the data of the row address from the memory cell array to the cache data storage area through the parallel port, and transferring from the memory cell array to the cache data storage area After the batch transfer of the row data, the step of transferring the row address and the column address for which the cache mishit has been determined from the access side to the cache memory, and the case where a cache hit has been determined for the transferred row address, match And a step of determining data of a portion designated by the column address in the cache data corresponding to the row address as the access data.