JPH06105950B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus capable of synthesizing a plurality of images.

[Conventional technology]

2. Description of the Related Art Conventionally, an image synthesizing device that creates an image by synthesizing a plurality of images is known.

In such an apparatus, first, an area in which another image is to be fitted is set with respect to the original image, and an instruction is given to fit another image in the area.

[Problems to be solved by the invention]

In the above-mentioned device, the original image and the other image are switched in the peripheral portion of the area where the image is to be fitted. However, the other image is not always output immediately with the switching, and a predetermined time delay occurs. It was sometimes output.

There are various factors for this, and as one of them, it is conceivable that the other image is output after undergoing a process having a predetermined time such as a spatial filtering process.

For this reason, there arises a problem that, for example, there is no image at the switching position of the image, that is, the peripheral portion where the image is to be fitted.

The present invention aims to solve such problems.

[Means for Solving Problems] An image processing apparatus for forming a composite image by switching between a first image and a second image and outputting the first image, the first supply supplying the first image. Means (corresponding to the color reader 1 in FIG. 1 in this embodiment), second supplying means for supplying the second image (corresponding to the memory 303 in FIG. 7 in this embodiment), the first supply Designating means for designating a synthesis area on the first image when the second image is synthesized with the first image supplied by the means (in the present embodiment, the digitizer shown in FIG.
16), signal generating means for generating an instruction signal for instructing the second supplying means to supply the second image in order to combine the second image in the combining area (in the present embodiment, 2 Figure SYNC104
(Corresponding to a region signal generating section 51 for generating a signal), image processing for performing a predetermined image processing on the second image signal supplied from the second supplying means in response to the instruction signal generated by the signal generating means. Means (the seventh embodiment in the present embodiment)
Figure filter 304, enlargement interpolation circuit 305, complementary color conversion table 30
(Corresponding to 6), the first image and the second image image-processed by the image processing unit are switched and output with a delay corresponding to the processing time by the image processing unit from the signal generation by the signal generation unit. Output means (in this embodiment, FIG. 2 SY
After the image supply instruction by NC104, delay circuits 312-314, 31
6, 317, 319 corresponding to the switching circuit 100 that is switched later), and.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a color image forming system to which the present invention is applied. As shown, the system has an upper digital color image reading device (hereinafter referred to as a color reader) 1, a lower digital color image printing device (hereinafter referred to as a color printer) 2, and a video processing device 3. The color reader 1 reads color image information of a document for each color by a color separation means described later and a photoelectric conversion element such as a CCD, and converts the color image information into an electric digital image signal. The color printer 2 is an electrophotographic laser beam color printer that reproduces a color image for each color according to the digital image signal and transfers the color image to a recording paper a plurality of times in a digital dot form for recording. The video processing device 3 is a device for converting an analog video signal from an externally connected video device into a digital image signal and inputting it to the color reader 1.

First, the configuration of the color reader 1 will be described. 999 is the manuscript,
Reference numeral 4 denotes a platen glass on which an original is placed, and 5 is a rod array lens for collecting a reflected light source from the original exposed and scanned by the halogen exposure lamp 10 and inputting an image to the full-magnification full-color sensor 6. 5,6,7,10 are original scanning units
As 11 together, exposure scanning is performed in the direction of arrow A1. The color-separated image signal that is read line by line while being exposed and scanned is amplified to a predetermined voltage by the sensor output signal width circuit 7, and then input to the video processing unit by the signal line 501 to undergo signal processing. . 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line for supplying a drive pulse for the full-size full-color sensor 6, and all necessary drive pulses are generated in the video processing unit 12. Reference numerals 8 and 9 denote a white plate and a black plate for white level correction and black level correction of the image signal, and by irradiating with the halogen exposure lamp 10, it is possible to obtain a signal level of a predetermined density, and Used for white level correction and black level correction.

Reference numeral 13 denotes a control unit having a micro computer, which is a display on the operation panel 20 by the bus 508, key input control and control of the video processing unit 12,
The position sensors S1 and S2 detect the position of the document scanning unit 11 through the signal lines 509 and 510, and the signal line 503 drives the stepping motor 14 to move the scanning body 11 in a pulsed manner. Signal line
The exposure lamp driver 21 controls ON / OFF of the halogen exposure lamp 10 via 504, control of light amount, control of the digitizer 16 and internal keys via the signal line 505, control of the display section, and all other controls of the color reader section 1. . The color image signal read by the above-described exposure scanning unit 11 during the exposure scanning of the document is input to the video processing unit 12 via the amplification circuit 7 and the signal line 501.

The details of the original scanning unit 11 and the video processing unit 12 described above will be described with reference to FIG.

The color image signal input to the video processing unit 12 is sampled and held by the sample / hold circuit S / H43.
It is separated into three colors (blue) and R (red). The separated color image signal is subjected to analog processing in the analog color signal processing circuit 44 and then A / D converted into a digital color image signal. In this embodiment, the color reading sensor 6 in the document scanning unit 11 is set to 5 as shown in FIG.
FiFo memory because it is divided into areas and arranged in a staggered pattern
Using 46, 2,4 channels are being scanned in advance, and the remaining 1,
Corrects the misalignment of the reading position of the 3,5 channel. FiF
The position-corrected signal from the memory 46 is input to the black correction circuit / white correction circuit, and the color reading sensor 6 is used by using the signal corresponding to the reflected light from the white plate 8 and the black plate 9 described above. The unevenness in darkness, the uneven light amount of the halogen exposure lamp 10, and the variation in the sensitivity of the sensor are corrected. Color image data proportional to the amount of light input to the color reading sensor 6 is converted by a logarithmic conversion circuit 86 for matching with the human eye's relative luminous characteristics, and then from the color image signal from the video interface 101 and the original scanning unit 11. Is input to the switching circuit 100 that switches the color image signal.

Incorporation of color image data from the video processing device 3 into the video processing unit 12 in the color reader 1 will be described below.

The setting of such acquisition is performed by the digitizer described below. FIG. 3 is an external view of the digitizer 16.
A key 427 is an entry key for setting an embedding combination mode, which will be described later, and a coordinate detection plate 420 is a coordinate position detection plate for designating an arbitrary area on a document or setting a magnification, and a point pen. 421 designates the coordinates.

On the coordinate detection plate 420, the size when recorded on a recording material such as paper from the video processing device is 100%, 200% on the upper right,
Three types of 400% are displayed.

In order to perform inset composition of the image from the video processing device 3, after pressing the inset composition key 427 in FIG.
To specify the position to fit. The inset region refers to, for example, a hatched portion in FIG. 4, which is a signal such as the timing chart SYNC in FIG. 4 for each line in the section in the sub-scanning direction A → B. Is distinguished from the area. It should be noted that C in FIG. 4 indicates the size of the entire document, and the shaded portion is the portion designated by the digitizer. The SYNC signal 104 is sent to the video processing device 3 through the video interface 101 shown in FIG.

In addition to the SYNC signal, the video interface 101 outputs the FREEZE signal 102 and VCLK103 to the video processing device 3.
The timing chart of these control lines is shown in FIG. That is, the FREEZE signal 102 and the SYNC signal 104 are the operation unit.
It is generated by pressing the start button of 20, and as shown in FIG. 5, the FREEZE signal 102 becomes "1" by pressing the start button, and the SYNC signal 104 becomes "in the range corresponding to the area designated by the digitizer 16." 1 ".

However, if the number of copies is 1 or more and an error such as a paper jam occurs during copying, the error is canceled and the copy button is pressed, the FREEZE signal 102 becomes Active.
It does not become "1", and only SYNC 104 and VCLK 103 are output to the interface 101. In the present embodiment, FIG.
A full-color print is performed by repeating the color process as shown in (4), and the colors of this print are shown in the figure.

Next, regarding the operation of the present embodiment configured as described above,
An explanation will be given using the flow chart of the controller (CPU) shown in FIG.

When the power is turned on, the controller 13 reads the operated keys on the operation panel 20 and the digitizer 16 (# 0
1). If there is an operated key, it is judged whether or not the key is a key for instructing copy start (# 03). If it is a key for instructing copy start, the process branches to # 05, and if not, the process branches to # 23.

Here, the following description will be given starting with # 23 assuming that keys other than the copy start key are turned on.

In # 23, it is determined whether or not the instruction of the area to be subjected to the inset combining is instructed by the switch 427 shown in FIG. 3, and when instructed, the instructed area is stored (# 2
5) If it is not instructed, it is determined whether or not the number of prints is designated (# 27). As a result of the determination, if the number of prints is set, the set number is written to the register (# 29), and if not set, the process corresponding to another key input is performed (# 31). ).

Next, a case where the copy start is instructed in # 03 will be described. When the start of copying is instructed, it is first determined whether or not the error flag is set (# 05). If there is no error flag, the FREEZE signal described in FIG. 2 is used.
102 is generated (# 07). Accordingly, the image data is written in the memory 303 in the video processing device described later with reference to FIG. Next, the error flag is reset (# 09).
In order to drive the scanner, the stepping motor drive circuit 15 shown in FIG. 1 is instructed to start driving. As a result, the scanner starts moving, and the HS
In synchronism with YNC and VCLK, each signal processing circuit shown in FIG. 1 is operated and each color component of the full color is sequentially output to the color conversion circuit 50 shown in FIG. 2 and processed by each of the circuits described above. It is then supplied to the color printer 2. The color printer 2 rotates a drum 716, which will be described later, according to the image signals sequentially sent from the video processing unit 12, and the ITO is rotated for each rotation.
The P signal (image leading edge signal) is returned to the unit 12. In this embodiment, full-color printing is performed with four colors of Y, M, C and Bk, and one color printing requires four rotations of the drum 716.

Therefore, in # 13, it is determined whether or not the ITOP signal has come four times (# 13), and until the ITOP signal has come four times, it is determined whether or not an error has occurred on the printer side (# 14) and the error is detected. If there is no error, the process returns to step # 13. If an error occurs, the error flag is temporarily set, the drive of the scanner is stopped, and it is determined whether the error has been canceled (# 21). When it is detected that ITOP has come 4 times in # 13, it is considered that one print is completed, so the number register is decremented (# 17), and whether the content becomes "0" or not When it is "0", the process returns to step S11. When it is not "0", the process returns to step # 11 and the copy operation is continued again.

In the embodiment shown in the flow chart described above, when an error occurs due to a paper jam in the color printer or other causes while the copying operation of a plurality of sheets is being performed (# 14), the flow is performed after the error is released. The next copy operation is not performed unless the copy start key is turned on because the key returns to.

Also, since the error flag is set once in # 19,
Even if the copy start key is turned on with returning to the above #
Since the flow branches from 05 to # 11, the freeze signal in # 07 does not occur, and it is possible to prevent a new image signal from being written in the memory 303.

Therefore, it is possible to prevent the frozen image data from being stored in the memory 303 before an error occurs and to prevent other data from being erroneously written in the memory 303.

VCLK 103 is an image data synchronizing signal in the video processing unit 12, and this signal is sent to the video processing device 3. The video processing device 3 has color image signals 105, 106 and 107 synchronized with VCLK103 and an EN signal 1 indicating the effective area of this signal.
Send 08 and to Video Interface 101. This EN signal 1
When 08 is 0, the switching circuit 108 selects the color image signal from the logarithmic conversion circuit 86 and outputs it to the circuit in the subsequent stage, and when 08, selects the color image signal from the video interface 101 to select the circuit in the subsequent stage. Output to.

As a control signal for switching the switching circuit 100, the above-mentioned S
Although it is conceivable to use the YNC 104, in the present embodiment, the switching circuit 100 is switched by using the EN signal from the video processing device 3 without using the SYNC 104, so that the following effects are obtained.

That is, when the switching circuit 100 is switched by using the SYNC signal, the color image signals 105, 10 from the video interface 101 when the response of the video processing device 3 is slow.
Switching of the switching circuit 100 is performed before 6,107 are output. Therefore, at the time of switching of the switching circuit 100, in other words, a black streak occurs at the end of the switching and combining of images. According to this, since the switching circuit 100 is switched by the EN signal from the video interface 101, it is possible to prevent the generation of such black streaks.

When the video processing device 3 is performing image processing such as edge enhancement using a plurality of pixels, the response of the video processing device 3 becomes particularly slow.

Next, a detailed circuit diagram of the switching circuit 108 is shown in FIG. In this circuit diagram, 113 to 118 are data selectors such as 74LS157 (model name), have two input data, and select terminals S
One of the two input data is selected according to the signal 112 of When signal 112 is 0, selector output OUT Y570, M57
Y ₀ 120, M ₀ 121, and C ₀ 122 are selected for the lines 1 and C 572, and when the signal 112 is 1, Y ′ 105, M ′ 106, and C ′ 107 are selected.
The selection signal 112 is controlled by signals 110 and 111 from the controller 13 in addition to the EN signal 108 described above.

Depending on the settings of the signals 110 and 111, the switching circuit 100 has three functions: dedicated to video image signals, dedicated to a reflection original (copying original) image, and inset composition. This function is shown in the table below.

That is, if the signals 110 and 111 are set to 0, the reflection original is trimmed by the area designated by the digitizer 16, and color correction, masking, gamma conversion, etc. are properly performed according to the nature of the image to be imaged according to the EN signal. Control so that you can do it. The EN signal 108 is used for the color correction and masking circuit 4 which will be described later.
8 and the gamma conversion circuit 52 are also connected.

Next, returning to FIG. 2, the description will be continued. The signal from the switching circuit 110 is input to the black extraction UCR circuit 47, which produces a black component signal and subtracts the black component signal from the color signals 570, 571, 572. The color correction / masking circuit 48 corrects the color separation filter of the color reading sensor 6 (first shown) and the color image signal of the video processing device 3.

Here, the operation of the color correction / masking circuit 48 will be described.

For each color component image data Yi, Mi, Ci, Masking correction for calculating a linear expression of each color and performing color correction is well known.

Since the color correction / masking circuit 48 in this embodiment makes this coefficient value variable with respect to the input image, the coefficient value can be set by the CPU via the data bus.

In the present embodiment, either the first matrix coefficient M ₁ or the second matrix coefficient M ₂ can be set from the bus connected to the control 13.

The coefficient of M ₁ is assigned for correction of the color separation filter in the original scanning unit 11, and the coefficient of M ₂ is assigned for correction of the video processing device 3.

Switching between these two coefficients M ₁ and M ₂ is selected by the EN signal 108 which is a signal from the video interface 101. That is, the coefficient of M ₁ is selected in the case of the color image signal from the document scanning unit 11 and the coefficient of M ₂ is selected in the case of the signal from the video processing device 3 to perform the color correction. The output of the color correction / masking circuit 48 is input to the color conversion circuit 50. In this embodiment, the function of the color conversion circuit 50 is used as a scale.

Reference numeral 52 is a gamma conversion circuit for controlling the color balance and color shading of the output image in this system. Basically, it is data conversion by a LUT (lookup table), and is used to specify the input from the operation unit. The LUT data is rewritten in association with each other. Further, the RAM 52 of this embodiment has five types of yellow, magenta, cyan, black, and MONO.
It has at least two types (Fig. 6 (b) A and B),
The area A has a gamma characteristic of A and the area B has a gamma characteristic of B so that a single print can be obtained.

Switching between the areas A and B is performed by the EN signal 108 from the video interface 101.

The RAM 52 for gamma conversion is designed so that the characteristics can be individually switched for each color, and can be rewritten by the controller 13 in association with the operation from the liquid crystal touch panel key on the scanning panel.

A scaling control circuit 53 and a 5-line buffer 54 scale the output signal of the gamma conversion circuit 52, and a filter circuit 55.
Edge processing and smoothing are performed at. The output of the filter circuit 55 is input to the color printer 2 through the printer interface circuit 56.

As described above, in the present system, the color image information from the video processing device 3 is fitted in the position designated by the digitizer 16, and the optimum color correction and gamma correction of the document scanning unit 11 and the video processing device 3 are performed. .

Next, the configuration of the video processing device 3 will be described with reference to FIG.

In FIG. 7, 300 is an NTSC that converts a video signal input as a composite signal, for example, an NTSC signal, into R, G, B signals.
Decoder, 301 is a switching circuit for selecting either RGB input a or R, G, B signals from NTSC decoder 300, 302 is a signal for selecting the signals selected by the switching circuit 301 for A / D separately for R, G, B respectively.
A / D converter for conversion, 303 is a memory in which the signal A / D converted by the A / D converter 302 is written, and at least RG
Each B has a capacity of one frame. 304
Is a digital filter that applies edge enhancement or smoothing to the signal read from the memory 303, 305 is an enlargement interpolation circuit that enlarges the image using the signal filtered by the filter 304, and 306 is interpolated by the interpolation circuit 305. It is a complementary color conversion table for converting RGB signals into Y, M, C signals corresponding to the complementary colors.

Reference numeral 308 denotes a memory control circuit that controls reading, writing, refresh operation of the memory 303, and its address.
The control circuit 308 inputs FR through the interface 307.
The memory 303 is set to the write state according to the EEZE signal.

It should be noted that the control circuit 308 includes the V-side sync signals VDTV363, SYNC on the TV side.
The field discrimination signal FLDTV 364 generated from the circuit 321, the output of the switching circuit 309, the output of the SYNC signal circuit 310, and the output of the enlargement ratio selection switch 322 are input. The control circuit 308 also generates an area signal 366 which is a signal generated by being triggered by the SYNC signal 104 and which indicates the effective area of the memory 303. The switching circuit 309 includes the clock C / TTV361 on the TV side, the H synchronization signal HDTV362, the VCLK103 on the interface side, and
SYNC104 is input, and VCLK103 and SYNC104 are selected when the presence of SYNC is detected by the SYNC detection circuit 310, and CKTV and HDTV are selected when the absence of SYNC is detected.

311 is a gate for performing a logical operation of the area signal 366 and SYNC 104, 312 is a filter 304, a delay circuit for compensating the delay due to the latch of the data in the expansion interpolation circuit 305,
313 to 315 are delay circuits for compensating for the time delay due to the filtering performed by the above-mentioned filter 304,
313 has a delay time of 5H, and 314 has a delay time of 7 pixels. 315 is an AND gate. Reference numerals 316 to 318 are delay circuits for compensating the time delay due to the expansion interpolation operation performed by the expansion interpolation circuit 305 described above. 316 has a delay time of 1H and 317 has a delay time of 1 pixel. is doing. Reference numeral 318 is a delay circuit for compensating the delay due to the data latch in the complementary color conversion table 306.

The delay circuits 312, 313, 314, 316, 317 described above are
It is driven by VCK367 and DVHS368. Selection switch 3
If the enlargement ratio changes by 22, the DVCK and DVHS cycles also change accordingly, so the delay time of each delay circuit described above also changes.

An AND gate 320 outputs a logical product of the SYNC 104 and the output EN1 of the delay circuit 318.

Next, the operation of the embodiment configured as described above will be described. The video processor 3 receives the RGB signal a or the input RGB signal a from the FREEZE 102 signal sent from the video processing unit 2.
Any of the RGB signals 355 to 357 obtained by decoding the NTSC signal b by the NTSC decoder 300 is selected by the switching circuit 301 and the CKTV signal 361 obtained by the SYNC circuit 321. The A / D converter 302 digitally according to the timing. RG
In this embodiment, the number of pixels in the memory is
It has 640 x 480 pixels. The memory control circuit 308 controls the timings of reading, writing, and refresh operations of the RGB memory 303. When the SYNC signal 104 is not input from the video processing unit 12, the SYNC detection circuit 310 determines that there is no SYNC, and the sync switching circuit 309 sets the sync signal on the TV side, that is, CKTV3.
Select 61 and HDTV362. S from video processing unit 12
When the YNC signal 104 is input, the synchronization switching circuit 309 selects VCLK103 and SYNC104, and the RGB memory 303 is read out at the timing of VCLK103 and SYNC104 input via the interface.

The magnifying power of the video image to be embedded in the reflection original 999 is fixed to three kinds of 100%, 200% and 400%, and is selected by the magnifying power selecting switch 322. This signal enters the memory control circuit 308 and controls the reading of the RGB memory 303. In the case of 200%, the pixels in the same line are read twice, and in the case of 400%, the pixels in the same line are read four times. Also, RGB memory at 100%, 200%, and 400% expansion rate
The synchronization of 303, the filter circuit 304, and the expansion interpolation circuit 305 is created by the memory control circuit 308. DVCK365, DVHS
This is done by synchronizing to 366.

The signal read from the RGB memory 303 is used by the filter circuit 30.
The filter using the matrix operation of 5 × 7 pixels is applied by 4 and edge enhancement or smoothing is performed.
Interpolation interpolation is performed by the enlarging interpolation circuit 305 when enlarging by × 200% and × 400%, and the complementary color conversion table 306 converts the R, G, and B signals into C107, M106, and Y104 signals, respectively, and a reader interface circuit. Video processing unit 12 through 307
Passed to. In this embodiment, the RGB data read from the RGB memory 303 includes the filter circuit 304 and the expansion interpolation circuit 30.
5. Since the processing is performed by the so-called pipeline structure that passes through the complementary color conversion table 306, a time delay occurs between the input of data and the output of each circuit. That is, as described above, the video processing device 3 performs a plurality of stages of processing, and therefore, it takes a certain time from when the image output is instructed to when the image is actually output. In this embodiment for adjusting the delay time, the EN signal 108 is generated. Delay circuits 312, 314, 317, 318, line-direction delay circuits 313, 315, and gates 315, 318 perform delays equal to the delay times in the respective circuits 303, 304, 305, 306, and EN signals according to the period during which each C107, M106, Y105 signal outputs valid image data. 108 outputs a valid signal.

In the odor of this embodiment, the mesh ratio (aspect ratio of one pixel) of the video image is 1: 1 so that it is 640 × 480 pixels. Then, image data is output in order to magnify this by either 100%, 200%, or 400%. At this time, SYN input to interface 307
There is no guarantee that the C signal 104 will be input as a signal having the same size as the enlarged image data. For this reason, the memory control circuit 308 which controls the RGB memory 303 has a size of an image to be read by the SYNC signal 104, 640 × 480 pixels (or 1280 × 960 pixels at 200% enlargement, 2560 × 1 at 400% enlargement).
An image area signal 366 indicating 920 pixels) is output. Then, the area signal 366 and the SYNC signal 104 are logically ANDed by the gate 311, and at the same time, the output delayed by each delay circuit.
An EN1 signal 371 (output of the delay circuit 319) and the SYNC signal 104 are logically ANDed by the gate 320. As a result, when the area of the SYNC signal, that is, the area to be fitted is larger than the output area of the image, the image area signal 366 causes the EN signal 1
The area of 08 is limited, and conversely, when the area of the SYNC signal 104 is small, the area of the image is forcibly limited to the area of the SYNC signal even if there is still an image area. These operations are shown in FIGS. 8 (a) and 8 (b). In FIG. 8, (a) shows that when the SYNC signal has a larger time width than the area signal, that is, when the area to be fitted is larger than the size of the image to be fitted, (b) is fitted to the opposite. SYNC signal 104, area signal 366, ENo signal 370, EN signal when the area to be filled is larger than the image to be fitted
108 and image data 105 to 107 are shown.

The time indicated by D in FIGS. 8 (a) and 8 (b) is the time delayed by the delay means 212 to 318 in FIG.

As described above, the filter circuit 304 is provided with a window of 5 lines × 7 pixels, and the value of each pixel in this window is calculated to form a filter. Therefore, the effective screen area is reduced by one to several lines, but this is not a problem. The same applies to the delay circuits 316 and 317 and the gate 318 for the expansion interpolation circuit 305.

Next, referring to FIG. 9, description will be given on the print image output after the image combination is performed. The area into which the video image is fitted by the digitizer 16 is designated by two points a and b.
According to the designated area, the SYNC signal 104 is output from the video processing unit 12 to the video processing device 3. In the video processing device 3, the video images C107, M10 are displayed in this area.
6, Y105 signals are output to the video processing unit 12. At this time, when the area designated by the digitizer 16 is large as shown in FIG. 9 (a), the EN signal 10 indicating the effective area of the video image is transmitted.
8 is output by the video processing device 3 and the video processing unit 12
Then, the video image is embedded only in the area of the EN signal 108, and the area outside the area is the original placed on the color reader 1.
Print 999. Conversely, as shown in FIG. 9 (b),
When the area ab designated by the digitizer 16 is smaller than the effective area of the video image, the SYNC signal 104 defines the area to be embedded and combined. As a result, the video image is embedded and synthesized in the hatched area.

Further, since the RGB memory 303 of this embodiment uses a memory such as a D-RAM, an operation called refreshing is necessary to hold the stored contents. The RGB memory stores the video signal (RGB or NTSC signal) input while holding the normal memory contents or by the FREEZE signal 102.
When writing to the 303 or holding the written data, a refresh signal is created according to the timing of the HDTV signal 362, and the video processing unit 12 to the SYNC signal 10
When 4 is input and the memory is being read, a signal for refresh is produced according to the timing of the SYNC signal 104. At this time, the periods of the HDTV signal 362 and the SYNC signal 104 are significantly different (in the present embodiment, the HDTV signal 362
And the cycle of the SYNC signal 104 is about four times different). The number of refreshes per change is changed for each.

Next, the configuration of the memory control circuit 308 described above will be described in detail with reference to FIG.

In Fig. 12, SCK (SLECTFD CLOCK) SHS (SLECTFD H
ORIZONTAL SIGNAL) is a signal which is switched by the switching circuit 309 and is input to the memory control circuit 308. 370
Is a frequency divider in which the frequency division ratio for dividing SCK is changed according to the setting of the enlargement ratio setting switch 322 shown in FIG. 7, and 372 is a portion for changing the frequency division ratio in which SHS is divided like 370. It is a circulator. 3
74 is a quaternary counter for counting the output of the frequency divider 370, 376
Is a counter for counting addresses in the main scanning direction, 378
Is a counter for counting addresses in the sub-scanning direction, 380
Is a comparator for comparing the output of the counter 376 and the outlet of the area value 382, and 384 is a comparator for comparing the output of the counter 378 and the output of the area value 386. 382 and 386 are the image memory 303, respectively.
Values corresponding to the number of pixels in the horizontal and vertical directions are set in advance.

Therefore, when either of the outputs of the comparators 380 and 384 becomes L level, the output of the gate 388 also becomes L level and the area signal also becomes L level.

Reference numeral 390 is a logic circuit which produces the signals (B), (C) and (D) shown in FIG. 13A from the 2-bit output of the quaternary counter 374. In addition, (B) is RAS (Row Address Str
obe), (C) is CAS (Colum Address Strobe), (D)
Is a signal for switching the selector 391 described later. 391
Is a selector for switching one of the outputs of the output counter 378 of the counter 376 and outputting it as a memory address in accordance with the above-mentioned (D) signal, and 392 is the above-mentioned (B), (C) signal or FIG. 13 (b). For refreshing (C),
(D) A selector that outputs a signal to the memory 303. 393
Is a D-FF that takes in the SHS signal from the switching circuit 309 via the inverter 397, and its output is connected to the enable terminal of the quaternary counter 395. 395 is a quaternary counter that counts the SCK signal from the switching circuit 309, and 394 is a logic circuit that produces the signals (C) and (D) shown in FIG. 13B from the 2-bit output of the counter 395. is there.
Reference numeral 396 is a counter that is enabled according to the output of the quaternary counter 395. When the SYNC detection circuit 310 detects that SYNC is present, "32" is set and it is detected that there is no SYNC. At this time, "8" is set, which is a counter that counts down according to the SCK signal, and the counter output is connected to the clear terminal of D-FF393.
AND gate 398,400 and inverter 399 are controllers
Depending on the write / read signal / W from W (W when the FREEZE signal 102 is H) and the FLD signal from the SYNC circuit 321 shown in FIG. 7, whether to enable the JK-FF368 is switched. An OR gate 401 takes the OR of the output Q or / W of JK-FF368 and inputs it to the enable terminal of the counter 378.

The operation of the memory control circuit 308 configured as above will be described.

First, the case where the controller 13 issues a write instruction will be described. In this case, the / W signal from the controller 13 is at H level, the counter 378 is enabled, and the output Q of JK-FF368 is determined according to the level of FLD signal. JK-FF368 indicates the vertical address of the memory 308 together with the counter 378.
Is output to the least significant bit of vertical address, counter 378
Other bits are assigned to the output of each. Therefore, when the FLD signal is at L level, that is, an odd field, the output Q of JK-FF is fixed at H level, and only the odd-numbered address is output as the vertical address. On the contrary, when the FLD signal is H level, that is, even field, the output Q of JK-FF368 is fixed to L level,
Only even addresses are output as vertical addresses.

On the other hand, a horizontal address is generated by the frequency dividing circuit 370, the quaternary counter 374, and the counter 376.

The horizontal and vertical addresses generated in this way are stored in the logic circuit 390.
Is output by the selector 391 in accordance with the output of the. In synchronization with the horizontal and vertical addresses thus generated, RAS and CAS are generated as shown in FIG. 13 (a), and writing is performed. In this case, the selector 392 outputs the signal on the logic 390 side to the memory 303.

Next, the case where a signal for reading is generated from the controller 13 will be described.

In such a case, the / W signal becomes L level, and JK-FF368
The output of JK-FF368 and counter 378 does not depend on the FLD signal.
Will make up one counter. Therefore, unlike the case of writing, the vertical address is incremented by "1".

When the SHS signal falls during the read operation and the read blanking period starts, the output of D-FF393, that is, ▲
The / refresh signal is inverted to the H level, and the memory 303 is brought into the refresh state. In this case selector 392
Is the RASγ made in the logic circuit 394 for refreshing,
CASγ (shown in FIG. 13 (b)) is output to the memory 303. As a result, the memory 303 automatically performs the refresh operation.

Further, in this case, the counter 396 is set to a value corresponding to the signal from the SYNC detection circuit 310. As this value, for example,
When the SYNC detection circuit detects that SYNC is present, "32" is set, and when it is detected that SYNC is not present, "8" is set. This is because it is necessary to change the timing of the refresh operation due to the fact that the HDTV signal 362 and the SYNC signal 104 have different periods as described above.

Further, the frequency division ratio of the frequency dividers 370 and 372 becomes a value set according to the enlargement ratio at the time of reading, and the period of the pulse output to the counters 376 and 378 is increased at the time of enlargement. Further, the area signal 366 is output from the gate 388 in accordance with the comparison between the values from the area specifying values 382 and 386 from the digitizer and the outputs from the counters 376 and 378.

Next, the configuration of the color printer 2 for printing the image signal processed by the video processing unit 12 as described above will be described with reference to FIG. In FIG. 1, reference numeral 711 denotes a scanner, which is a laser output unit for converting an image signal from the color reader 1 into an optical signal, a polyhedral (eg, octahedral) polygon mirror 712, and a motor (not shown) for rotating the mirror 712.
And an f / θ lens (imaging lens) 713 and the like. Reference numeral 714 is a reflection mirror that changes the optical path of the laser light, and 715 is a photosensitive drum. The laser light emitted from the laser output unit is reflected by the polygon mirror 712, passes through the lens 713 and the mirror 714, and scans the surface of the photosensitive drum 715 like a cotton (raster scan) to form a latent image corresponding to the original image. .

Further, 717 is a primary charger, 718 is a full-face exposure lamp, 723 is a cleaner unit for collecting the untransferred residual toner, 72
4 is a pre-transfer charger, and these members are the photosensitive drum 715.
Is arranged around. 726 by laser exposure,
A developing unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715. 731Y (for yellow), 731M (for magezane), 731C (for cyan), and 731Bk are in direct contact with the photosensitive drum 715 for direct development. Developing sleeve, 730Y, 730M, 730C, 7
30Bk is a toner hopper that holds spare toner, 732
Is a screen for transferring the developer, and these sleeves 731Y to 731Bk, toner hoppers 730Y to 730Bk and screen 732 constitute a developing unit 726, and these members are arranged around the rotation axis P of the developing unit. It is set up. For example, when a yellow toner image is formed, yellow toner development is performed at the position shown in this figure, and when a magenta toner image is formed, the developing unit 726 is rotated about the axis P in the figure to expose the toner. A developing swivel 731M in the magenta developing machine is arranged at a position in contact with the body 715. Development of cyan and black works similarly.

Further, 716 is a transfer drum for transferring the toner image formed on the photosensitive drum 715 to a sheet, 719 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is to be in close proximity to the actuator plate 719. Is a position sensor for detecting that the transfer drum 716 has moved to the home position, 725 is a transfer drum cleaner, 727 is a paper pressing roller, 728 is a charge eliminator and 729 is a transfer charger, and these members 719, 720, 725, 727, 729 are Transfer roller 716
Is arranged around.

On the other hand, 735 and 736 are paper feed cassettes that contain paper (paper bodies), 737 and 738 are paper feed rollers that feed paper from the cassettes 735 and 736, and 739,740, and 741 are timing rollers that control the timing of paper feed and conveyance. The sheet that has been fed and conveyed is guided to a sheet guide 749, is wound around a transfer drum 716 while being supported by a gripper described later, and is transferred to an image forming process.

Further, 550 is a drum rotation motor, which synchronously rotates the photosensitive drum 715 and the transfer drum 716. After the image formation process, the 750
A peeling claw for removing the sheet from the transfer drum 716, 742 is a conveyor belt for conveying the removed sheet, 743 is an image fixing section for fixing the sheet conveyed by the conveyor belt 742, and the image fixing section 743 is a pair. Heat pressure rollers 744 and 745.

According to the above configuration, the photosensitive drum 715 is first irradiated with laser light.
A Y latent image is formed on the upper surface, is developed by the developing unit 731Y, and is then transferred to the paper on the transfer drum.
Next, the developing unit 726 rotates about the axis P in the figure. Next, an M latent image is formed on the photosensitive drum by laser light,
The same operation is performed thereafter. This operation is similarly repeated for C and Bk, and when the image forming process is completed, the peeling claw 75
At 0, the paper is peeled off, the image fixing unit 743 fixes the paper, and the printing of the color image ends.

In the embodiment described above, the means for synthesizing the first input image signal and the second input image signal is the switching circuit 100 for synthesizing the image from the video processing unit 3 and the image from the original scanning unit 11. The present invention is not limited to this, and is of course effective when combining two images.

Further, the means for generating the instruction signal for switching between the first input image signal and the second input image signal is the generation circuit 51 for generating the area signal according to the instruction of the digitizer 16, but this is not limited to the digitizer. Needless to say, a mouse or the like may be used instead.

Further, the control means for switching the synthesizing state of the synthesizing means after a predetermined time delay from the instruction signal is the circuit indicated by 312 to 320 in the video processing device 3. That is, in this embodiment, the instruction signal 105 for switching to the video processing unit 3 is output, and the processing in the video processing unit 3 is performed based on the instruction.
Image data is actually output after a predetermined time, and the EN signal 108 for switching is output from the unit 3 to the switching circuit 100 together with the output. The present invention is not limited to this, and it is possible to directly input EN from the generation circuit 51 without passing through the video processing unit.
A signal corresponding to the signal 108 may be output.

〔The invention's effect〕

As described above, according to the present invention, when the output of the image to be combined with the image to be combined is switched after the instruction signal for instructing the supply of the image to be combined is generated, the predetermined image processing is performed on the image to be combined in the previous period. The switching is performed with a delay corresponding to the processing time of applying.

Therefore, even if the image output to be combined in the combination area is delayed by the predetermined image processing, there is no image-free area in the peripheral portion of the combination area, and an excellent combined image can be obtained. .

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic internal configuration of a color image forming system to which the present invention is applied, and FIG. 2 is a block diagram showing a configuration of a document scanning unit 11 and a video processing unit 12 shown in FIG. 1, and FIG. Is an external view of the digitizer 16 shown in FIG. 1, FIG. 4 is a view showing a fitting area, and FIG. 5 is a FREEZE signal 102, VCLK103, SYNC signal 104 output from the video interface 101 to the video processing device 3.
FIG. 6 is a timing chart showing the two types of gamma characteristics of the RAM 52 shown in FIG. 2, FIG. 7 is a block diagram showing the configuration of the video processing device 3 shown in FIG. 1, and FIG. (A) and (b) are video processing devices 3 shown in FIG.
9 (a) and 9 (b) are diagrams for explaining a print image output after screen composition is performed in the apparatus of the present embodiment, and FIG. 10 is FIG. 11 is a block diagram showing the internal structure of the switching circuit shown in FIG. 11, FIG. 11 is a timing chart for explaining the operation of the controller 13 shown in FIG. 1, and FIG. 12 is a timing chart of the memory control circuit 308 shown in FIG. Block diagrams showing the configuration, and FIGS. 13 (a) and 13 (b) are memory control circuits 30 shown in FIG.
8 is a timing chart for explaining the operation of FIG. 1 ... Color reader, 2 ... Color printer, 13 ... Controller.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasumichi Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Yoshinori Ikeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Toshio Honma 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (1)

[Claims] 1. An image processing apparatus for forming a composite image by switching and outputting a first image and a second image, comprising: first supply means for supplying the first image; Second supplying means for supplying the first image supplied by the first supplying means, and a specifying means for specifying a combination area on the first image when the second image is combined with the first image supplied by the first supplying means. A signal generating means for generating an instruction signal for instructing the second supplying means to supply the second image so as to combine the second image with the combining area; and an instruction signal generated by the signal generating means. Image processing means for subjecting the second image signal supplied from the second supplying means to predetermined image processing according to the above, a time delay corresponding to the processing time by the image processing means from the signal generation by the signal generating means. The first image and the The image processing apparatus according to an outputting means for switching and outputting the second image image-processed by the image processing means.