JPH06104883A - System for monitoring transmitter - Google Patents

Abstract

PURPOSE:To prevent the generation of warning information inside a device by a parity error due to unsettled reception clock when the signal input is interrupted or the synchronizing step-out is occured in monitoring the inside of a device by the parity check of the former stage of a synchronizing circuit. CONSTITUTION:The system is provided with a synchronizing circuit 300 inputting a reception signal 10 and a reception clock 20 and outputting a frame signal 40 and an error signal 50, parity check arithmetic circuit 100 inputting the reception signal 10 and the reception clock 20 and outputting a parity signal 30, and parity check circuit 200 inputting the reception signal 10, reception clock 20, parity signal 30, and error signal 50 and outputting a parity alarm 60. Further, it is provided with an OR circuit 400 inputting the frame signal 40 and the error signal 50 and outputting the reset signal 70, R-S flip-flop 50 inputting the parity alarm 60 and the reset signal 70 and outputting an alarm integration signal 80, and a 3-frame delay circuit 600 inputting the alarm integration signal 80, frame signal 40, and error signal 50 and outputting a warning 90 inside the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system monitoring system, and more particularly to a transmission system monitoring system for monitoring the operation between a signal receiving unit and a synchronizing circuit.

[0002]

2. Description of the Related Art A conventional transmission system monitoring system is a parity arithmetic circuit 11 for inputting a reception signal 11 and a reception clock 21 and outputting a parity signal 31, as shown in FIG.
A parity check for inputting 0, the reception signal 11, and the reception clock 21 and the synchronization circuit 310, the reception signal 11, the reception clock 21, and the parity signal 31 and outputting a parity alarm as the alarm information 61 in the device. And a circuit 210.

Next, the operation of the conventional example will be described. The parity calculation circuit 110 receives the received signal 11 and the received clock 2
1 is input, the parity is calculated perpendicularly to the time axis with respect to the received signal 11, and the parity signal 31 is output. The parity check circuit 210 uses the received signal 11 and the received clock 2
1 and the parity signal 31 are input, the parity is checked perpendicularly to the time axis, and the abnormality of the received signal 11 is output as a parity alarm (warning information) 61.

[0004]

In this conventional monitoring method for a transmission device, an input signal is disconnected or out of synchronization due to an abnormality in the opposite device or an abnormality in the transmission path (hereinafter referred to as RE).
C state), the reception clock 21 becomes indefinite, and the phase state and parity check between the reception signal 11 input to the parity operation circuit 110, the reception clock 21 and the parity signal 31 output. Circuit 2
Since a phase difference occurs between the received signal 11, the received clock 21, and the parity signal 31 input to 10, the parity alarm 6 output from the parity check circuit 210
There is a problem that 1 is output as alarm information in the device regardless of the abnormality in the device.

[0005]

According to a monitoring method of a transmission apparatus of the present invention, frame synchronization is established at a condition N stages of frame synchronization cancellation of a reception signal by a reception clock, and the frame signal and the signal are disconnected or out of synchronization. A synchronous circuit that outputs an erroneous signal that indicates, a parity calculation circuit that inputs the reception clock and signal, calculates a parity perpendicular to the time axis with respect to the signal, and outputs the parity signal, and a reception clock, signal, and A parity check circuit that inputs the parity signal and performs a parity check on the parity signal by the error signal and the received signal and outputs a parity alarm when there is an error, and a reset signal by a logical sum of the frame signal and the error signal. And a logical sum circuit that outputs the It is reset with the serial reset signal R-
It has an S flip-flop and a delay circuit for delaying the alarm integration signal by N stages of the frame signal and outputting it as alarm information.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of this embodiment.

The synchronizing circuit 300 inputs the received signal 10 and the received clock 20, establishes the frame synchronization, outputs the frame signal, and protects the three stages at the time of releasing the frame synchronization to disconnect the input signal or lose the synchronization signal. 50 (hereinafter referred to as an erroneous signal) is output. The parity calculation circuit 100 inputs the reception signal 10 and the reception clock 20, and calculates the parity with respect to the reception signal 10 so that the parity signal 30 of the reception signal 10 is perpendicular to the time axis at the same time,
The parity signal 30 is output.

The parity check circuit 200 includes a received signal 10, a received clock 20, a parity signal 30, and an erroneous signal 5.
By inputting 0, the parity check of the parity signal 30 existing at the same time as the received signal 10 is performed, and if it is incorrect, a parity alarm 60 is output only for the time of the incorrect signal. Further, the erroneous signal 50 is input to the reset terminal of the parity check circuit 200, and the parity check circuit 200 is reset in the case of an error state (indicating an input disconnection or a loss of synchronization state).

The logical sum circuit 400 inputs the frame signal 40 and the erroneous signal 50 to obtain a logical sum, and the reset signal 7
Outputs 0. The RS flip-flop 500 inputs the parity alarm 60 to the set (S) and inputs the reset signal 70 to the reset. That is, the RS flip-flop 500 outputs the alarm integration signal 80 by an operation that is set when the parity alarm 60 is generated and is reset when the frame signal 40 is output or when an error occurs.

The three-frame delay circuit 600 inputs the alarm integration signal 80, the frame signal 40, and the error signal 50, delays the alarm integration signal 80 by three frames of the frame signal 40, and outputs the alarm information 90 in the apparatus. Output as. Also, the REC signal 50 is a 3-frame delay circuit 6
00 reset terminal, and the 3-frame delay circuit 600 is reset in the error state.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. Time t ₁ between the received signal 10 is T ₁ from the time T ₀ from the time T ₀ elapses time to T ₁₀
When the parity alarm 60 is generated for B _{1 of No. 1} and is output by the parity check circuit 200, the RS flip-flop 500 is set and is not reset until the frame signal 40 at time T ₁ is output. , Alarm integration signal 80 is output. Alarm integrated signal 80 output, from the time T _1, is outputted from the time T ₄ as warning information 90 in the apparatus at time T ₄ because it is delayed by 3 frame delay circuit 600 of the T _5.

Next, since the parity alarm 60 is not generated between the times T ₁ and T ₂ , the alarm information 90 is not output between the devices between the times T ₅ and T ₆ . The next parity alarm 60 for B _{2 at} time t ₂ between times T ₂ and T ₃ is output between times T ₆ and T ₇ . Here, if an abnormality of the transmission line occurs between time T ₄ and time T ₅ , an indefinite state may occur in the reception signal 10, and the parity alarm 60 generated during the indefinite state is set to B ₃ (time t ₃ ) and B ₄ (time t ₄ ).

In this way, in order for B ₃ and B ₄ to be output as the alarm information 90 in the apparatus, the time T ₅ and T 4
It should be output at time T ₈ and T ₉ delayed by 3 frames from ₆ , but since it enters the protection to the REC state from time T ₅ and becomes the error state after time T ₈ after the protection of three stages, the reset signal Since 70 is output and the 3-frame delay circuit 600 is reset, the alarm information 90 in the device is not output at times T ₈ and T ₉ .

[0014]

As described above, according to the present invention, a parity check circuit that performs a parity check on a parity signal and outputs a parity alarm when there is an error, and a logical sum of an erroneous signal indicating a signal break or loss of synchronization and a frame signal are used. An OR circuit that outputs a reset signal, an RS flip-flop that sets the parity alarm, outputs an alarm integration signal, and resets the reset signal, and alarm information by delaying the alarm integration signal by N stages of the frame signal. By having a delay circuit that outputs as
It is possible to prevent a parity alarm from being output as an abnormality in the device due to an indefinite reception clock when the input signal is disconnected or out of synchronization due to an abnormality in the transmission path or an abnormality in the opposite device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional monitoring method for a transmission device.

FIG. 3 is a timing chart for explaining the operation of the present embodiment.

[Explanation of symbols]

 10, 11 Received signal 20, 21 Received clock 30, 31 Parity signal 40 Frame signal 50 Loss of input or loss of synchronization signal (erroneous signal) 60, 61 Parity alarm 70 Reset signal 80 Alarm integration signal 90 Alarm information in device 100, 110 Parity operation circuit 200,210 Parity check circuit 300,310 Synchronous circuit 400 Logical sum circuit 500 RS flip-flop 600 3 Frame delay circuit

Claims (1)

[Claims] 1. A synchronization circuit that establishes frame synchronization at a condition N stages of frame synchronization cancellation of a reception signal by a reception clock and outputs a frame signal and an erroneous signal indicating disconnection or loss of synchronization of the frame signal and the reception circuit. A parity operation circuit that inputs a clock and a signal, calculates a parity perpendicularly to the time axis with respect to the signal, and outputs the parity signal, and the reception clock, the signal, and the parity signal, and inputs the error signal and the reception signal. And a parity check circuit that outputs a parity alarm when there is an error in the parity signal and a logical sum circuit that outputs a reset signal according to the logical sum of the frame signal and the error signal, and the parity alarm is set by the parity alarm. An RS flip-flop that outputs an alarm integration signal and resets with the reset signal And a delay circuit for delaying the alarm integration signal by N stages of the frame signal and outputting it as alarm information.