JPH06104196A - Manufacturing method for semiconductor device - Google Patents

Abstract

PURPOSE:To provide a doping method for doping different impurities into different regions selectively in a simple process. CONSTITUTION:In a vacuum chamber 11 having an atmosphere including an impurity for one conductivity, a laser beam is cast through a quartz window 13 to a semiconductor 19 to be doped as a sample on a highly accurate XYZ- type stage 14. When a laser beam is cast through a mask 16 in a pattern, the impurity with one conductivity is doped selectively in the semiconductor 19 as a sample.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a MOS type semiconductor device,
The present invention relates to a technique of locally doping impurities into a semiconductor required in a manufacturing process of a semiconductor device such as a CMOS semiconductor device, and selectively doping different impurities into different regions by a simple process. It provides a technology that can.

[0002]

2. Description of the Related Art When manufacturing a semiconductor device such as a MOSFET or a CMOS type device, a step of selectively controlling the resistivity by locally adding an impurity imparting one conductivity type to a local portion of the semiconductor Is essential.

In the conventional process, first, a shield film is formed on the semiconductor surface to prevent the intrusion of impurities,
After that, a shield film in a region to be doped is removed by a photolithography process to form a mask, and thereafter, necessary impurities are doped by thermal diffusion or ion implantation.

[0004]

The doping method used in the conventional process as described above has the following problems.

(1) When attempting to dope impurities into a semiconductor by the thermal diffusion method, there is a problem that a high temperature process is required. For example, taking a silicon semiconductor as an example, the sample silicon semiconductor is 1000 to 12
Since it has to be heated to 00 degrees, it is difficult to form a shallow impurity layer required for high-density IC, and redistribution of impurities and defects due to a high temperature process are problems.

(2) In the impurity doping method by the ion implantation method, post heat treatment is required at a temperature of 600 to 950 ° C. for activation of impurities and recovery of defects, and therefore, it is described in the above (1). The same problem as the thermal diffusion method occurred.

Further, as a common problem between the thermal diffusion method and the ion implantation method described in the above (1) and (2), there is a problem that a high temperature process far exceeding 600 degrees is required. For example, in the case of an active matrix type liquid crystal display device, which has been attracting attention in recent years, since a MOS type thin film transistor (TFT) is formed on a glass substrate, when an inexpensive glass substrate having a heat resistant temperature of about 600 to 700 degrees is used, It was difficult to use the thermal diffusion method and the ion implantation method in the process.

Further, when selective doping is to be performed, a mask must be formed as described above, and a photolithography process is required in this process. It is well known that the photolithography process requires a complicated process and the yield is reduced due to the photolithography process.

As described above, in the conventional impurity doping method, a high temperature process is required, and further, a mask forming process requiring a photolithography process is required to perform selective dope. There was a problem.

[0010]

In order to solve the above problems in the conventional impurity doping method, the present invention provides a mask on the surface of a semiconductor placed in an atmosphere containing an impurity imparting one conductivity type. And irradiating the semiconductor surface with laser light through the mask, thereby diffusing the impurity having the one conductivity type into a local region of the semiconductor and reducing the resistivity of the region. In a method for manufacturing a semiconductor device and a method for selectively doping impurities imparting different conductivity types, P or N
A mask is placed on the surface of the semiconductor placed in an atmosphere containing impurities imparting the conductivity type of the type, and the semiconductor surface is irradiated with laser light through the mask, whereby the first region of the semiconductor is exposed. The step of diffusing the impurity imparting the one conductivity type, the atmosphere after the step of switching to the atmosphere containing the impurity imparting the N or P conductivity type, and the position of the mask being changed to the semiconductor through the mask And a step of diffusing an impurity imparting an N or P type conductivity type into the second region of the semiconductor by irradiating the surface with laser light. .

In the above structure of the present invention, the impurity imparting one conductivity type is a trivalent element for imparting P-type and a pentavalent element for imparting N-type assuming that the semiconductor is silicon. Refers to the element. An atmosphere containing an impurity imparting one conductivity type means that if the conductivity type is P type,
PH ₃ which is a reactive gas containing B (boron), which is a trivalent impurity imparting P-type conductivity, can be generally used. When the conductivity type is N type, B ₂ H ₆ which is a reactive gas containing P (phosphorus) which is a pentavalent impurity imparting the N type conductivity type can be generally used.

As the semiconductor, a silicon semiconductor is generally used, but other semiconductors may be used. Impurity of impurities in the semiconductor may be changed by irradiation with laser light in an atmosphere containing an impurity element to be doped. The basic configuration of the present invention called diffusion is not limited to the type of semiconductor. Needless to say, the crystal structure of the semiconductor may be single crystal or non-single crystal.

As the mask, it is suitable to use a mask having a pattern formed of a refractory metal such as chromium on a quartz plate. The quartz plate is necessary for transmitting the laser beam, and the reason why the pattern is made of a refractory metal is that the pattern is not melted by the laser beam. Therefore,
If the energy density of the laser light is low, the mask may be formed using aluminum or the like.

As the laser light, XeF excimer laser (wavelength 351 nm), ArF excimer laser (wavelength 193 nm), KrF excimer laser (wavelength 248) are used.
nm) or the like can be used. As a kind of laser, a pulse oscillation type excimer laser which has a large peak power and melts and solidifies a non-irradiated surface within an extremely short time is suitable.

The present invention utilizes the phenomenon that the impurity element contained in the atmosphere diffuses into the semiconductor from the surface of the semiconductor which is instantaneously melted by the irradiation of the laser beam, but another characteristic of this method. Another point is that doping of impurities and activation of impurities can be performed at the same time, and when the semiconductor is an amorphous semiconductor, polycrystallization of the amorphous semiconductor can be performed at the same time.

The present invention utilizes the above phenomenon to selectively perform impurity doping, and further, dope different impurities continuously and selectively without a photolithography process. A CMOS in which a P-channel type MOS transistor and an N-channel type MOS transistor are configured to be complementary by using the configuration of the present invention.
Type semiconductor device can be formed by a simpler process than before.

[0017]

【Example】

[Embodiment 1] This embodiment is an example of performing selective doping using a mask with a laser beam having the structure of the present invention in a manufacturing process of a silicon gate N-channel MOSFET. In addition, the examples described in this specification are known semiconductor devices using all silicon semiconductors.

First, FIG. 1 shows a laser doping system used in this embodiment. In FIG. 1, 11 is a vacuum chamber, which is provided with a high vacuum exhaust system 12.
The high-vacuum exhaust system 12 has a rotary pump and a turbo-molecular pump connected in series, and when the atmosphere in the vacuum chamber 11 is switched, a high vacuum is once drawn to prevent unnecessary impurities from remaining in the vacuum chamber 11. I am doing it. Reference numeral 17 is a system for introducing a reactive gas or a diluent gas,
From here, PH ₃ or B ₂ H _6, which is a reactive gas containing an element imparting one conductivity type, is introduced. It is also possible to use hydrogen as the diluent gas. Further, an introduction system of nitrogen or argon which is an inert gas is provided as needed.

Reference numeral 13 is a quartz window for introducing laser light from the outside of the chamber 11. Numeral 14 is an XYZ stage, which is arranged in the XYZ three-dimensional direction as shown in FIG.
The position can be controlled with the accuracy of μm.
Of course, an XYZ stage or X- with higher accuracy
Using the Y stage is useful for increasing the accuracy of doping. A heater 15 heats the sample to a desired temperature. Reference numeral 16 is a mask, and the mask pattern 10 is formed of chrome on a quartz plate. Reference numeral 18 denotes a laser beam to be irradiated, which is KrF in this embodiment.
An excimer laser (wavelength 248 nm) was used. Reference numeral 19 is a sample, on which a semiconductor which is a sample to be doped is installed.

FIGS. 2A and 2B show the Si according to this embodiment.
A basic manufacturing process of a gate N channel type MOS transistor is shown. The gist of the present invention relates to the doping of impurities, and does not limit the structure or the manufacturing process of the electrode formation, the insulating film, the wiring, and the like, and therefore will not be described here.

The Si gate N channel type MOS transistor whose manufacturing process is shown in FIG. 2 uses a P type single crystal silicon substrate to which B (boron) is added as the substrate 21. This is the same as that used in a normal Si gate N channel MOS transistor. A silicon oxide film serving as a gate insulating film is formed on this substrate 21 by a known thermal oxidation method to a thickness of 1000Å, and B, which is a trivalent impurity, is ion-implanted into the channel formation region to control the threshold voltage. . Next, a polycrystalline silicon film or an amorphous silicon film to be a gate electrode is formed by thermal CVD or plasma CVD to a thickness of 7,000 Å. Then, the gate insulating film 22 and the gate electrode 23 were simultaneously formed by patterning by a known photolithography process. Up to this point is a conventional technical field.

In this state, the substrate 21 was maintained in a PH ₃ normal pressure atmosphere diluted with hydrogen in order to diffuse P (phosphorus), which is an impurity having an N-type conductivity, to a predetermined position on the substrate. It was installed in the vacuum chamber 11 shown in FIG. The XYZ stage 14 shown in FIG.
Alignment is performed by using, to irradiate a laser beam to dope the P element into a predetermined region which is not masked by a mask, activate P, and when the gate electrode 23 is amorphous silicon, the Crystallization was also performed at the same time. Then, the source region 25 and the drain region 26
(Of course, the reverse is also possible), and the channel forming region 24
Were simultaneously formed. Here, in order to control the resistivity, the PH ₃ gas dilution ratio or the atmosphere pressure may be changed to change the doping concentration, or the number of laser light irradiations and the power density of the laser light may be changed. Good. Specifically, if the dilution rate of the doping gas is high, the pressure of the atmosphere is low, or the power density of the laser light is low, the concentration of doping is low. If this condition is reversed, the doping concentration will increase.

In this step, since the channel forming region 24 under the gate and the source 25 and drain 26 regions on both sides thereof are formed in self-alignment (self-alignment), the alignment accuracy of the mask 16 is several. Allowed in the allowable range of μm. That is, a mask may be installed so that the source / drain regions and the gate electrode portions aligned in a line are irradiated with the laser light. Although the channel length is 5 μm, the allowable limit of fine processing to which the configuration of the present invention can be applied is limited by the operation accuracy of the XYZ stage 14.

In the subsequent steps, the conventional technique is used to form an interlayer insulator, electrodes, and wiring to form a MOS.
Type transistor FIG. 2B was completed. In FIG. 2B, 27 is an interlayer insulating film, 28 is a drain electrode, 29 is a source electrode, and 291 is a protective film.

In the above process, the distance between the mask 16 and the sample was 2 mm. This is because the reactive gas containing the impurity element to be doped is present between the mask and the sample surface. Considering the scattering and diffraction phenomena of laser light, the distance between the mask and the sample should be small, but if there is almost no gap, the reactive gas cannot enter and doping will not be performed efficiently. . Therefore, a suitable interval between the mask and the sample is about 0.1 mm to 5 mm. In addition, even if a mask pattern is enlarged to a desired size by using an enlarged mask pattern and an optical system instead of the full-scale mask pattern, the laser beam passing through the mask is reduced in size. Good.

When the laser is irradiated, the sample is
Doping can be efficiently performed by heating to about 0 to 500 degrees. Furthermore, in this embodiment,
Although P (phosphorus) and B (boron), which are impurities imparting one conductivity type, were used to change the resistivity of a specific place, in an N (nitrogen) atmosphere to insulate the specific place. By irradiating the laser light with, it is possible to diffuse N to a specific place and partially insulate it. Of course, oxygen or carbon can be doped at a selectively controlled concentration by using an atmosphere of oxygen gas or carbide gas as another impurity.

By adopting the structure of this embodiment, it is possible to selectively and efficiently dope a silicon gate without forming a mask by a photolithography process and without causing thermal damage to an unnecessary portion. An N-channel MOS type transistor could be obtained. In this embodiment, the P channel type MOSFET is formed by changing the doping atmosphere to B ₂ H _6.
It goes without saying that the source and drain regions can be formed.

Further, the doping technique using laser light as described in this embodiment is also applied to form the source and drain regions of the amorphous silicon TFT and the polycrystalline silicon TFT provided on the glass substrate. Therefore, it is possible to solve the problem of heat damage, which is the most problematic when manufacturing a TFT (thin film transistor) on a glass substrate, and it is possible to obtain a high-performance TFT.

[Embodiment 2] This embodiment is a C / TFT in which an N channel type MOSTFT (hereinafter referred to as NTFT) and a P channel type MOSTFT (hereinafter referred to as PTFT) provided on a glass substrate are formed in a complementary type. An example in which the configuration of the present invention is used in the step of producing The semiconductor used in this example is also a silicon semiconductor. Needless to say, the impurity doping technique described in this embodiment can be applied to the case where a CMOS integrated circuit is formed on a silicon substrate.

The manufacturing process of this embodiment is shown in FIG. Figure 3
(A) is a completed top view of this embodiment, in which PTFT and NT
An element having a CMOS structure in which FT and FT are provided in a complementary manner on a glass substrate is shown. (Hereinafter referred to as C / TFT) In FIG. 3, 39 and 392 are input wirings of C / TFT,
Reference numeral 393 is an output wiring, and reference numeral 391 is a gate electrode wiring. Further, 394, 395, 396, 397 are contacts between electrodes and wirings. Further, 31 is a source region of the NTFT, 35 is a gate electrode, and 33 is a drain region. 36 is a source region of the PTFT, 37 is a gate electrode, and a channel forming region of the PTFT is formed thereunder via a gate insulating film.
38 is a drain region.

FIG. 3B shows a dotted line ab of FIG. 3A.
A sectional view of a portion indicated by is shown. FIG. 3B is a sectional view of an NTFT having a very basic structure in which electrodes, wirings, interlayer insulating films, etc. are not formed. Therefore, the input wiring 3 shown in FIG.
9, 392, output wiring 393, gate electrode wiring 391,
And these contacts 396, 397 are shown in FIG.
Not shown in (B).

PTFT and NT shown in FIG.
The difference from FT is the source and drain regions. That is, the source region 3 of the NTFT in FIG.
1, the conductivity type of the drain region 33 is N type, and PTFT
The difference is that the conductivity type of the source region 36 and the drain region 38 is P type.

In order to control the threshold voltage, the channel forming region may be doped with an impurity imparting an N-type conductivity type in the case of PTFT and an impurity imparting a P-type conductivity type in the case of NTFT. There are some differences. In any case, the PTFT and the NTFT can be made separately by changing the kind of impurities at the time of doping.

Conventionally, in order to form a CMOS TFT (C / TFT) circuit in which PTFT and NTFT are formed in a complementary form, one TFT is doped with impurities while the other TFT is made of silicon oxide. A film or a silicon nitride film must be used as a mask, and a complicated process is required to form and remove this mask.

The structure of the present invention is characterized in that PTFT and NTFT can be separately formed by moving the XYZ stage 14 shown in FIG. 1 and changing the atmosphere in the vacuum chamber 11.

In FIG. 3, a portion which becomes an NTFT by a known TFT manufacturing process using a silicon semiconductor is shown in FIG.
It is formed into a shape as shown in FIG. At this time, this NT
The part which becomes FTFT adjacent to the part which becomes FT is shown in FIG.
Needless to say, it is formed similarly to (B).
What is important here is that the PTFT and the NTFT cannot be distinguished yet before the impurity doping. In this embodiment, the channel formation region (indicated by 32 in the case of NTFT) is not doped with impurities.

FIG. 4 shows the positional relationship of masks when impurity doping is actually performed on the TFTs arranged side by side using the structure of the present invention. Here, a cross-sectional view of a portion indicated by a dotted line ab in FIG. 3 corresponds to FIG. Figure 4 (A)
Is the installation position of the mask when forming the NTFT,
FIG. 4B shows a mask installation position when forming a PTFT. Although the mask is set here, the substrate that is the sample is actually moved by the XYZ stage, and the mask remains fixed.

In FIG. 4, chromium is provided in the shaded portion, and the laser light is masked in this portion. Also, in FIG. 4, the size of the mask is written small in relation to the drawing, but it is actually larger, so it is before the sample is moved with respect to the mask and after the sample is moved. In both 4 (B), the edge of the mask and the TFT
The positional relationship of is shown as almost the same. The doping process in this embodiment will be described below.

First, by performing known steps, the process shown in FIG.
When the shape of (B) is obtained, the sample is moved into the vacuum chamber shown in FIG. 1, the atmosphere is once evacuated to a high vacuum, and then the atmosphere is switched to the PH ₃ normal pressure atmosphere, as shown in FIG. 4 (A). As described above, the mask is installed so that the laser beam is applied to a predetermined position. And by laser irradiation NT
The portion to be FT is doped with P (phosphorus), which is an impurity imparting an N-type conductivity, as in the first embodiment. As shown in FIG. 4, a mask (hatched portion) is not formed in the portion to be the NTFT, and this portion is transmitted through the quartz plate and the sample is irradiated with laser light.

Next, after evacuating to a high vacuum once, as shown in FIG.
The XYZ stage shown in FIG. 4 is moved, and as shown in FIG. 4B, the position of the mask, that is, the portion where the pattern for transmitting the laser light for doping is formed is relatively moved to the portion to be the PTFT of the sample. Let Then, the atmosphere is a B ₂ H ₆ normal pressure atmosphere, and laser light irradiation is performed in the same manner as in the case of manufacturing the NTFT to form a PTFT. At this time, since both the PTFT and the NTFT are formed in self-alignment as in the first embodiment, it is useful that some mask alignment error can be allowed if the mask is aligned with the region where the TFT is formed. Further, the doping gas was not diluted in this example.

In this way, by simply moving the position of the mask relative to the sample and changing the atmosphere, P
It was possible to selectively form the TFT and the NTFT. After this, one output of the PTFT and NT are formed by a known process.
One output of the FT, that is, the drains are connected to each other by aluminum wiring to form the output wiring 393 in FIG. Then, the source electrode wirings 39 and 392 are formed, and the gate electrode wiring 391 is further provided to complete the C / TFT.

By adopting the structure of the present invention as described above, conventionally, a step (including a photolithography step) of masking a portion to be one of the TFTs is required to form a CMOS or C / TFT. It was possible to do it with an extremely simple process. As a result, it is possible to omit two photolithography processes as compared with the conventional manufacturing process.
It was possible to obtain a very useful effect in high-fine processing that the step corresponding to the photolithography step once, that is, the step of manufacturing PTFT and NTFT can be performed in the same vacuum chamber.

In this embodiment, one C / TFT is formed, but if the C / TFT is periodically formed on the substrate, the mask pattern as shown in FIG. The laser irradiation may be performed by using a mask that is formed as a mask and shifting it.

[0044]

INDUSTRIAL APPLICABILITY By irradiating a laser beam through a mask in an atmosphere containing an element of an impurity imparting one conductivity type, which is a constitution of the present invention, a region corresponding to a mask pattern is selectively irradiated from the surface of a semiconductor. Doping can be performed, and particularly when forming a C / TFT in which CMOS or NTFT and PTFT are provided in a complementary type, the N-channel MOS transistor and the P-channel MOS transistor can be changed by changing the mask position and atmosphere. Or PT
FT and NTFT can be selectively made separately, and defects caused by the conventional photolithography process can be reduced.

[Brief description of drawings]

FIG. 1 shows a laser irradiation apparatus for carrying out the present invention.

2A to 2D show steps of manufacturing a MOS transistor manufactured in Example 1. FIG.

3A and 3B show a manufacturing process and a completed drawing of the C / TFT manufactured in Example 2. FIG.

FIG. 4 shows a positional relationship of masks in a second embodiment.

[Explanation of symbols]

 11 vacuum chamber 12 high-vacuum exhaust system 17 gas introduction system 13 quartz window 14 XYZ stage 15 heater 16 mask 10 mask pattern 18 laser light 19 sample 21 substrate 22 gate insulating film 23 gate electrode 24 channel formation region 25 source region 26 drain region 27 Interlayer insulating film 28 Drain electrode 29 Source electrode 291 Protective film 39,392 C / TFT input wiring 393 C / TFT output wiring 391 C / TFT gate wiring 394, 395, 396, 397 contact 31 NTFT source region 32 NTFT Formation region 33 drain region of NTFT 34 gate insulating film of NTFT 35 gate electrode of NTFT 36 source region of PTFT 37 gate electrode of PTFT 38 drain region of PTFT

Claims (2)

[Claims] 1. A local area of the semiconductor is provided by placing a mask on the surface of the semiconductor placed in an atmosphere containing impurities imparting one conductivity type, and irradiating the semiconductor surface with laser light through the mask. A method for manufacturing a semiconductor device, comprising: diffusing an impurity imparting one conductivity type into a region to reduce the resistivity of the region. 2. A mask is provided on the surface of a semiconductor placed in an atmosphere containing an impurity imparting P or N type conductivity, and the semiconductor surface is irradiated with laser light through the mask, Diffusing an impurity imparting the one conductivity type into a first region of the semiconductor, and after the step, switching an atmosphere to an atmosphere containing an impurity imparting an N or P conductivity type, and Irradiating a laser beam to the semiconductor surface through the mask by changing the position, and diffusing an impurity imparting N or P type conductivity type to the second region of the semiconductor. Method for manufacturing a semiconductor device.