JPH06103228A - Processing system - Google Patents

Abstract

PURPOSE:To provide a processing system capable of automatically connecting signals in the same system through a prescribed data bus independently of the data bus specification of a device in respect of a processing system for connecting a device with a 1st data bus specification for applying the 1st system byte signal and a 2nd system byte signal respectively to upper 8 bits and lower 8 bits to a device for down-loading firmware to the device when a power supply is turned on according to the 1st data bus specification or the 2nd data bus specification for applying signals in the reversed systems respectively to the upper 8 bits and the lower 8 bits. CONSTITUTION:The data bus specification is written in the head of firmware, a data bus for the upper 8 bits of a 1st device 1 and a data bus for its lower 8 bits are respectively connected to the common sides of respectively selectors 5, 6 and a data bus for the upper 8 bits of the 2nd or 3rd device 2 and a data bus for its lower 8 bits are respectively connected to the switching sides of the selectors 5, 6. In addition, the processing system is also provided with a bus connection switching signal generating part 7 for inputting the data bus specification written on the head of the firmware and switching the connection of the common sides and switching sides of the selectors 5, 6 so that signals of respective systems are passed through the prescribed 8-bit data buses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an image processor having a 68-system CPU (Motorola system), which is a 68-system or 86-system image processor.
When a power supply is turned on for a device having the first data bus specification, such as an image processing system connected to a personal computer or a workstation, which has a CPU (Intel system) of a system and downloads the firmware of the image processor when the power is turned on. The present invention relates to improvement of a processing system for connecting to a device of a first data bus specification or a device of a second data bus specification for downloading firmware for the first device to the first device.

68 system CPU (Motorola system) and 86 system
Figure 4 shows the data bus of the CPU (Intel system)
As shown in (A) and (B), the 68-system CPU uses the upper 8 bits (D1) of the 16-bit data bus as shown in (A).
5 to D8), the first-system byte signal is passed through the data bus, and the second 8-bit (D7 to D0) data bus is connected to the second byte.
System byte signals, the 86-system CPU sends the upper 8 bits (D15 to D15-) of the 16-bit data bus as shown in (B).
The data bus for passing the signal is inverted such that the byte signal of the second system is passed through the data bus of D8) and the byte signal of the first system is passed through the data bus of the lower 8 bits (D7 to D0). .

That is, in the 68-system CPU, as shown in (C), a circle signal is placed in the lower 8 bits on the upper 8-bit data bus.
Assuming that a triangular signal is passed through the bit data bus, if connecting to the same 68 series CPU, the upper and lower 8-bit data buses should be connected to the upper and lower 8-bit data buses. , (D), a circular signal passes through the upper 8-bit data bus and a triangular signal passes through the lower 8-bit data bus, but when connecting to a 86-system CPU, as shown in (E). The upper and lower 8-bit data buses must be connected so that the triangular signal is passed through the upper 8-bit data bus and the lower 8-bit data bus is passed through the circular signal.

In the case of such a connection, it is desired to provide a processing system that does not require any trouble.

[0005]

2. Description of the Related Art FIG. 3 is a block diagram of an image processing system according to an example, and FIG. 5 is a block diagram of a data bus connecting portion of a bus adapter according to a conventional example.

The image processing system shown in FIG. 3 comprises an image processor 1 and a personal computer (or workstation) 2.
The image processor 1 has a 68-system CPU 11, the personal computer 2 has a 68-system or 86-system CPU 19, and the firmware used by the image processor 1 is stored in the disk 20 of the personal computer 2. The firmware is read out, passed through the bus interface 21 and the bus adapter 16 and downloaded to the RAM 12 of the image processor 1 for use.

The image signal from the camera 17 is converted into a digital signal by the A / D converter 13, and the frame memory 1
4 is displayed on the CRT 18 and is band-compressed by the data compression / expansion unit 15 and sent to the disk 20 via the bus adapter 16 and the bus interface 21 for storage.

When the stored image data is displayed on the CRT 18, if the image data is read from the disk 20 and sent via the bus interface 21 and the bus adapter 16, the data compression / expansion unit 15 expands the image data to the CRT 18. Is displayed.

In this image processing system, a 68-system CP is used.
Since the image processor 1 having U11 must be connected to the personal computer 2 having the 68-system CPU or the 86-system CPU 19, the data bus connection of the bus adapter 16 is conventionally configured as shown in FIG.

That is, the lower 8 bits (D0 to D7) of the 16-bit data bus on the image processor 1 side are set to the common side of the switch 9 and the upper 8 bits (D8 to D15) are set to the switch 1
0 is connected to the common side, and the lower 8 bits (D0 to D7) and the upper 8 bits (D) of the 16-bit data bus of the personal computer 2 are connected.
8 to D15) are connected to the switching sides of the switches 9 and 10.

The image processor 1 and the personal computer 2 are both 68
When using the CPU of the system, switch 9,1 manually
0 is connected to the dotted line side, and the image processor 1 is a 68 series CP
When the U was used and the personal computer 2 used the CPU of the 86 series, it was done by manually connecting the switches 9 and 10 to the solid line side.

[0012]

However, the 8-bit data bus for passing the first system signal and the 8-bit data bus for passing the second system signal of the image processor 1 are the signals of the first system of the personal computer 2. Even if it is compatible with the 8-bit data bus that passes through and the 8-bit data bus that passes the signal of the second system, or the 8-bit data bus that passes the signal of the second system of the personal computer 2 and the signal of the first system Even if it is compatible with an 8-bit data bus to be passed, in order to pass a signal of a predetermined system, it is necessary to manually operate the switches 9 and 10, which is troublesome. There is.

According to the present invention, the 8-bit data bus for passing the first system signal of the first device and the 8-bit data bus for passing the second system signal pass the first system signal of the partner device. 8-bit data bus that passes the second-system signal of the partner device or 8-bit that passes the first-system signal It is an object of the present invention to provide a processing system capable of automatically connecting a signal of a predetermined system to each 8-bit data bus even if it is compatible with the above data bus.

[0014]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the byte signal of the first system is passed through the upper 8 bits of the 16-bit data bus and the lower 8 bits.
The first device 1 having the first data bus specification that allows the second system byte signal to pass through the bit, and the firmware for the first device 1 having the first data bus specification and being powered on A second device for downloading to the first device 1 or a second device for passing a second system byte signal through the upper 8 bits and a first system byte signal through the lower 8 bits of the 16-bit data bus. When the data bus specification is used and the power is turned on, the firmware for the first device 1 is downloaded to the first device 1
In the processing system connected to the third device 2 to be downloaded to the first device, the own device has the first data bus specification or the second data bus specification at the head of the firmware of the second or third device 2. Signal indicating the data bus specification is written, and the first and second selectors 5 and 6 are also written.
Is provided, the upper 8-bit data bus of the first device 1 is connected to the common side of the first selector 5, and the lower side of the first device 1 is connected to the common side of the second selector 6. An 8-bit data bus is connected, and an upper 8-bit data bus and a lower 8-bit data bus of the second or third device 2 are connected to the switching sides of the first and second selectors 5 and 6. In addition, when a signal indicating the specification of the first data bus of the firmware is input from the 8-bit data bus and input, the connection between the common side and the switching side in the first and second selectors 5 and 6 is
A bus connection switching signal generator that sends a signal for connecting the byte signal of the first system and the byte signal of the second system so as to pass through a predetermined 8-bit data bus to the first and second selectors 5 and 6. 7 is provided.

[0015]

According to the present invention, when the power is turned on, when the firmware is downloaded from the second or third device 2 to the first device 1, it is stored at the head of the firmware.
Alternatively, when the data bus specification of the third device 2 is input to the bus connection switching signal generation section 7, the bus connection switching signal generation section 7 sends a signal for controlling connection according to the data bus specification to the first and second selectors 5, 5. 6 to the first device 1 and the second or third
The upper and lower 8-bit data buses of the device 2 are connected so that signals of a predetermined system pass through.

That is, the upper and lower 8-bit data buses of the first device 1 for passing the signals of the first and second systems are the second and the second, respectively.
Or, even if it corresponds to the upper and lower 8-bit data buses of the third device 2 for passing the signals of the first and second systems, or the lower ones for the signals of the first and second systems, Even if it is inverted with respect to the upper 8-bit data bus, it is possible to automatically connect to each 8-bit data bus so as to pass a predetermined system signal.

[0017]

2 is a block diagram of a data bus connecting portion of a bus adapter according to an embodiment of the present invention.

The image processing system of the present invention also has a configuration shown in FIG. 3, but the difference from the conventional image processing system is that the head of the firmware for the image processor 1 stored in the disk 20 of the personal computer 2 in FIG. Since the data bus specifications of the personal computer 2 are written and the data bus connection portion of the bus adapter 16 of the image processor 1 is as shown in FIG. 2, the different points will be mainly described below.

At the head of the firmware for the image processor 1 stored in the disk 20 of the personal computer 2 in FIG.
A data bus specification indicating whether the data bus of the personal computer 2 is of 68 system or 86 system is written.

The common sides of the selectors 5 and 6 in FIG.
A data bus of lower 8 bits (D0 to D7) and a data bus of higher 8 bits (D8 to D15) of the image processor 1 are connected, and the lower 8 bits (D0 of the personal computer 2 (D0 To D7) and upper 8 bits (D8 to D15) data bus are connected.

The lower 8 bits (D0 to D of the personal computer 2
The data bus 7) (which may be a data bus of higher 8 bits) is also input to the bus connection switching signal generator 7, and the address buses (A0 to A15) are input to the address recorder 8.

When the power is turned on, the address bus of the personal computer 2 sends an address for the following operation to the address recorder 8, and the address recorder 8 opens the circuit to the bus connection switching signal generator 7 and inputs from the data bus. The data bus specifications to be stored and a command for generating a connection switching signal are given.

Then, the bus connection switching signal generator 7 stores the data bus specifications sent from the lower 8 bits (D0 to D7) of the data bus. When the personal computer 2 has a CPU of 86 system, it outputs a signal for connecting the upper and lower 8-bit data buses of the image processor 1 to the upper and lower 8-bit data buses of the personal computer 2, respectively. Outputs and connects signals for connecting the upper and lower 8-bit data buses of the image processor 1 to the lower and upper 8-bit data buses of the personal computer 2.

That is, the upper and lower 8-bit data buses of the image processor 1 for passing the signals of the first and second systems are
Even if the personal computer 2 is compatible with the upper and lower 8-bit data buses that pass the signals of the first and second systems, or
Even though the second system signal is passed through the lower and upper 8-bit data buses, each 8-bit data bus can be automatically connected to pass the predetermined system signal. become.

[0025]

As described in detail above, according to the present invention, an 8-bit data bus for passing a first system signal and an 8-bit data bus for passing a second system signal of a first device are provided.
8-bit data bus that passes the 1st system signal of the partner device and 8-bit data bus that passes the 2nd system signal, or 8-bit data that carries the 2nd system signal of the partner device Even if the bus and the 8-bit data bus for passing signals of the first system are supported, there is an effect that each 8-bit data bus can be automatically connected so as to pass signals of a predetermined system.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a data bus connection portion of a bus adapter according to an embodiment of the present invention,

FIG. 3 is a block diagram of an example image processing system,

FIG. 4 is a diagram showing a difference between data buses of 68 series and 86 series CPUs in one example;

FIG. 5 is a block diagram of a data bus connection portion of a conventional bus adapter.

[Explanation of symbols]

 1 is a first device, an image processor, 2 is a second or third device, a personal computer, 5 and 6 are selectors, 7 is a bus connection switching signal generator, 8 is an address recorder, 11 is a 68-system CPU, and 12 is RAM, 13 is an A / D converter, 14 is a frame memory, 15 is a data compression / expansion unit, 16 is a bus adapter, 17 is a camera, 18 is a CRT, 19 is a 68 series or 68 series CPU, 20 is a disk, 21 is a Indicates a bus interface.

Claims (1)

[Claims] 1. A first device (1) of a first data bus specification, wherein a high-order 8 bits of a 16-bit data bus pass a first-system byte signal and a low-order 8 bits pass a second-system byte signal. ) Is a second device that downloads the firmware for the first device (1) to the first device (1) when the power supply is turned on with the first data bus specification, or 1
A 6-bit data bus has the second data bus specification in which the upper 8 bits pass the second-system byte signal and the lower 8 bits pass the first-system byte signal. In the processing system for connecting the third device (2) to download the firmware for the first device (1) to the first device (1), the firmware for the second or third device (2) A signal indicating the data bus specification of whether the device itself is the first data bus specification or the second data bus specification is written at the head, and first and second selectors (5, 6) are provided. , The data bus of the upper 8 bits of the first device (1) is connected to the common side of the first selector (5), and the first bus is connected to the common side of the second selector (6).
Device (1) is connected to the lower 8-bit data bus, and the switching side of the first and second selectors (5, 6) is connected to the upper 8-bit data of the second or third device (2). A data bus and a lower 8-bit data bus are connected, and a signal indicating the first data bus specification of the firmware is input from the 8-bit data bus, and when input, the first and second selectors (5, 6) The signal for connecting the common side and the switching side of the first side byte signal and the second side byte signal through the predetermined 8-bit data bus
A processing system comprising a bus connection switching signal generator (7) for sending to a second selector (5, 6).