JPH06103147A - Degeneration store controller - Google Patents

Abstract

PURPOSE:To decrease the request given to a main storage by increasing the cases where plural write requests are degenerated into a single request. CONSTITUTION:An address buffer 2 is provided to store the write request addresses given to a main storage together with a buffer writing pointer register 12 which designates the word to store the request addresses, a buffer reading pointer register 11 which designates the word to read out the request addresses, an address writing register 1 which supplies the request addresses, and a degeneration detecting circuit 3 which detects the propriety of the degeneration store. Furthermore a degeneration opposite party pointer generating circuit 5 is added to generate the value of the buffer pointer storing the degeneration opposite party together with a degeneration opposite party pointer buffer 6, a pointer coincidence detecting circuit 7 which detects the coincidence of pointers, a degeneration store pointer generating circuit 8 which generates the value of the pointer storing the degeneration store, a selection circuit 13 which selects the register 11 or the circuit 8, and a degeneration suppressing circuit 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a degenerate store control device, and more particularly, it has a buffer of three words or more for storing a write request to the main memory of an information processing device, and a plurality of write requests to the same word of the main memory can be stored in one buffer. The present invention relates to a degenerate store control device that degenerates to a write request.

[0002]

2. Description of the Related Art Conventionally, a degenerate store control device of this type is
If the address of the store request B to be registered in the store buffer is compared with the address of the store request A last registered in the store buffer, and if degeneracy is possible in the store for the same word, the information is stored. Is added to the store request B and registered in the store buffer. Then, the store request A of the degeneration partner is read from the buffer and set in the buffer read register, at the same time, the buffer read pointer register is updated, and the store request B with the degeneration information is read as a subsequent request. At the next timing, the store request A set in the read register is converted based on the degeneracy information attached to the store request B, and the store requests A and B are sent to the main memory as one store request. .

[0003]

In the above-described conventional degenerate store control device, a store request to be registered in the store buffer will be degenerate only for the last store request registered in the store buffer. It is possible, and degenerate store cannot be performed for other requests in the buffer. Therefore, there is a problem that there are few cases where degeneration is possible.

[0004]

An apparatus of the present invention has a buffer composed of entries of 3 words or more for storing a write request for a main memory of an information processing apparatus, and stores a plurality of write requests for the same word in the main memory. In a degenerate store control device that degenerates into one write request, an address buffer that stores a write request address and a valid bit for the main memory of the information processing device, and a buffer that specifies a word that stores a request address in the Adolus buffer A write pointer register, a buffer read pointer register that specifies a word for reading a request address in the address buffer, and an address write register that supplies a main memory write address to the address buffer,
A degeneracy detection circuit that compares the output of the address write register with the address in each word of the address buffer to detect whether degeneracy store is possible, and a buffer pointer that receives the address comparison result from the degeneracy detection circuit and stores the degeneracy partner. A degenerate destination pointer generation circuit for generating a value, a degenerate destination pointer buffer with a valid bit having a plurality of entries for storing the output of the degenerate destination pointer generation circuit, the buffer read pointer register, and the degenerate destination pointer A pointer match detection circuit that compares the pointers in each word of the buffer to detect a match, and a degenerate store storage pointer generation circuit that receives the comparison result of the pointer match detection circuit and generates a pointer value in which the degenerate store is stored. Of the buffer read pointer register Degenerate store control device characterized by having a selection circuit for selecting the output of the force and the degenerate store storage pointer generation circuit.

[0005]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a degenerate store control processing device according to a first embodiment of the present invention.

The address write register 1 outputs the buffer registration address 101 to the address buffer 2 as a main memory write address. Address Haffa 2 is
In the buffer of 6 words, the buffer registration address 101 is stored by the buffer write pointer 124 and the valid bit is set. In addition, the valid bit is cleared at the same time when it is read by the buffer read pointer 125. Also, the main memory write address stored in words 0 to 5 in the address buffer 2 and the valid bit 1
02 to 107 are always output to the degeneration detection circuit 3.

The degeneracy detection circuit 3 compares the address supplied from the address buffer 2 with each of the valid bits 102 to 107 and the buffer registration address 101, and outputs an address comparison result signal 108 and a degeneracy permission signal 109. The degenerate destination pointer generation circuit 5 inputs and decodes the address comparison result signal 108, and outputs the degenerate destination pointer and the valid bit 110.

The degenerate destination pointer buffer 6 is a 6-word buffer, and stores the degenerate destination pointer and the valid bit 110 output from the degenerate destination pointer generation circuit 5 by the buffer write pointer 124, and the degenerate destination pointer valid bit. The valid signal is cleared by the clear signal 117. Further, the pointer and valid bits 111 to 117 in this buffer are constantly output to the pointer coincidence detection circuit 7.

The pointer coincidence detection circuit 7 compares the buffer read pointer 125, the degenerate destination pointer buffer words 0 to 5 pointers and each of the valid bits 111 to 116, and degenerates the degeneration flag 118, the pointer comparison result signal 119 and the degeneracy. Destination pointer valid bit clear signal 1
17 is output. Degenerate store storage pointer generation circuit 8
Inputs the pointer comparison result signal 119, decodes it, and outputs the degenerate pointer 120. The degeneration flag register 9 receives the degeneration flag 118 and inputs the degeneration flag 121.
Is output. The degenerate pointer register 10 inputs the degenerate pointer 120 and outputs the degenerate pointer 122.

Buffer read pointer register 11
Is incremented by 1 at the timing of reading one request from the main buffer 11 and the buffer read pointer 123
Is output. Also, if the request is read while the pointer value is 5, it returns to 0.

Buffer write pointer register 12
Outputs a buffer write pointer 124 which is incremented by 1 at the timing of registering one request in this buffer. When the pointer value is 5, the request is registered and the request returns to 0. The selection circuit 13 uses the degenerate pointer 122.
Buffer read pointer 1 is selected by the degeneration flag 121.
25 is output.

Next, the operation of this embodiment will be described with reference to FIGS. 3 and 4. First, the case where the degenerate store is possible will be described.

As shown in FIG. 3 (A), valid addresses "B0", "" for words 1, 2, 3 in the address buffer 2, respectively.
C0 "and" D0 "are stored, and it is assumed that all the words in the degenerate destination pointer buffer 6 are invalid. That is, the valid bits are all the words" 0 ". Further, the buffer read pointer 125 is the word 1 in the buffer. It is assumed that the buffer write pointer 124 points to word 4 in the buffer, and this timing is T0 timing.

In the T0 timing, when the address "C1" is set in the address write register 1, the degeneracy detection circuit 3 causes the buffer registration address 101, the addresses of the address buffer words 0 to 5 and the valid bit 10.
Compare with each of 2-107. As a result, the value "C1" of the buffer registration address 101 and the value "C0" of the address 104 of the address buffer word 2 point to the same word, and the valid bit of the address 104 of the address buffer word 2 is "1". Therefore, it is determined that degeneration is possible, and the degeneration permission / inhibition signal 109 and the address comparison result signal 108 with degeneration information are output. The degenerate destination pointer generation circuit 5 receives and decodes the address comparison result signal 108, and indicates the degenerate destination pointer interface and the pointer value "2" that indicates the word in which "C0" is stored in the valid bit 110, the valid bit value. Outputs "1".

At the T1 timing, as shown in FIG. 3B, the value "C1" of the buffer registration address 101 and the valid bit "1" are stored in the word 4 of the address buffer 2, and the word of the degenerate destination pointer buffer 6 is stored. 4 is stored with the degenerate destination pointer, the pointer value “2” of the valid bit 110, and the valid bit value “1”, and at the same time, the buffer write pointer register 12 is incremented by 1, and the buffer write pointer 124 indicates the word 5 in the buffer. As expected.

At timing T2, as shown in FIG. 3C, the address "B0" of word 1 in the address buffer 2 is reached.
Is read, the buffer read pointer register 11 is incremented by 1, and the buffer read pointer 123
Becomes the value "2". The selection circuit 13 selects the buffer read pointer 123, and the buffer read pointer 12
5 indicates word 2 in the puffer.

The pointer match detection circuit 7 compares the buffer read pointer 125, the degenerate destination pointer buffer words 0-5 pointers, and the valid bits 111-116, respectively. The value of the buffer read pointer 125 is "2"
Since the value of the degenerate destination pointer buffer word 4 pointer is "2" and the valid bit value is "1", the address "C" of words 2 and 4 in the address buffer 2 is
It can be seen that degeneracy of 0 "and" C1 "can be performed.
The degeneration flag 118 is output as "1" and the pointer comparison result signal 119 is also output. The degenerate store storage pointer generation circuit 8 receives the pointer comparison result signal 119, decodes it, and outputs the degenerate pointer 12 as "4".

At timing T3, as shown in FIG. 3D, the address "C0" of the word 2 in the address buffer 2 is read.
At the same time that the valid bit is cleared, the buffer read pointer register 12 is incremented by 1,
The value of the buffer read pointer 123 becomes “3”. The value of the degeneration flag 118 is stored in the degeneration flag register 9
1 ”is set, the value of the degeneration flag 121 becomes“ 1 ”, and the value of the degeneration flag 118 is“ 1 ”in the degeneration pointer register 10, so the degeneration pointer 120 is set,
The value of the degeneration pointer 122 becomes "4".

Since the value of the degeneration flag 121, which is the selection signal, is "1", the selection circuit 13 selects the degeneration pointer 122 and the value of the buffer read pointer 125 becomes "4", and the word in the buffer is selected. Point 4 The pointer match detection circuit 7 outputs a degenerate destination pointer valid bit clear signal 117 in order to clear the valid bit of word 4 of the degenerate destination pointer buffer 6.

At timing T4, as shown in FIG. 3E, the address "C1" of the word 4 in the address buffer 2 is read.
Is read and the requests for words 2 and 4 in the buffer are degenerated, and at the same time, word 4 in address buffer 2
Is cleared, and the valid bit of word 4 in the degenerate destination pointer buffer 6 is cleared by the degenerate destination pointer valid bit clear signal 117. Further, since the value of the degeneration flag 121 returns to “0”, the selection circuit 13
Then, the buffer read pointer 123 is selected, and the buffer read pointer 125 points to word 3 in the buffer. The above is the operation at the time of degenerate store.

Second, the case of suppressing the degenerate store will be described. When the present invention is applied to an information processing apparatus that only degenerates two requests, the degenerate store suppressing operation described below is required.

As shown in FIG. 4 (A), valid addresses "A0", "" are provided in words 0, 1, 2 in the address buffer 2, respectively.
B0 "and" A1 "are stored, and a valid pointer value" 0 "is stored in word 2 in the destination pointer buffer 6. That is, words 0 and 2 in the buffer can be degenerated. The buffer read pointer 125 points to the word 0 in the buffer, and the buffer write pointer 124 points to the word 4 in the buffer, and this timing is T0.

When the address "A2" is set in the address write register 1 at the T0 timing, the degeneration detection circuit 3 causes the buffer registration address 101, the address buffer words 0 to 5 and the valid bit 102.
1 to 107. The value of the buffer registration address 101 is "A2", and the values of the address buffer word 0 and 2 addresses 102 and 104 are "A0" and "A", respectively.
There are two degeneration request candidates because the valid bits are both "1" and "1". The degeneration destination pointer generation circuit 5 receives and decodes the address comparison result signal 108. At this time, two degeneration requests are generated. In order to give priority to the request that occurs earlier in time among the candidates, the degenerate destination pointer and the valid bit 110 are output as the pointer value “0” and the valid bit value “1”.

At the T1 timing, as shown in FIG. 4B, the value "A2" of the buffer registration address 101 and the valid bit "1" are stored in the word 3 of the address buffer 2, and the word of the degenerate destination pointer buffer 6 is stored. At the same time that the degenerate destination pointer and the value of the valid bit 110 are stored in 3, the buffer write pointer register 12 is incremented by 1, and the buffer write pointer 124 points to word 4 in the buffer.

The pointer coincidence detection circuit 7 also includes a buffer read pointer 125, a degenerate destination pointer buffer word 0 to 5 pointers, and valid bits 111 to 116.
Compare with each. The value of the buffer read pointer 125 is “0”, the pointer values of the degenerate destination pointer buffer words 2 and 3 are “0”, and the valid bit value is “0”.
1 ", so words 0 and 2 in address buffer 2
Addresses "A0", "A1", and "A2" of 3 and 3 can be degenerated.

When the present invention is applied to an information processing apparatus that degenerates three or more requests, "A0", "A"
Although degeneration of 1 "and" A2 "is performed, in the present embodiment, it is assumed that only degeneration of two requests is supported in order to simplify the control. However, this applies to two application ranges of the present invention. The present invention is not limited to the information processing device that supports only request degeneration.

In this embodiment, the degeneracy of "A0" and "A1" must be performed and the degeneracy of "A2" must be suppressed. First, degenerate “A0” and “A1”, and degenerate flag 11
8 is output as "1" and the pointer comparison result signal 119 is also output. Degenerate store storage pointer generation circuit 8
Receives the pointer comparison result signal 119, decodes it, and outputs the degenerate pointer 120 as "2". In this case, the comparison result of word 3 is also the same, but because the word whose address is close to "A0" is preferentially decoded, "
2 "is output.

At the T2 timing, as shown in FIG. 4C, the address "A0" of the word 0 in the address buffer 2 is read.
At the same time that the valid bit is cleared, the buffer read pointer register 12 is incremented by 1,
The buffer read pointer 123 has the value “1”. The value of the degeneration flag 118 is stored in the degeneration flag register 9
1 ”is set, the value of the degeneration flag 121 becomes“ 1 ”, and since the value of the degeneration flag 118 is“ 1 ”in the degeneration pointer register 10, the degeneration pointer 120 is set.
The value of the degeneration pointer 122 becomes “2”.

Since the value of the degeneration flag 121, which is the selection signal, is "1", the selection circuit 13 selects the degeneration pointer 122 and sets the buffer read pointer 125 to "2", and the word in the buffer is selected. Point 2 The pointer coincidence detection circuit 7 outputs a degenerate destination pointer valid bit clear signal 117 in order to clear the valid bits of the words 2 and 3 of the degenerate destination pointer buffer 6.

At timing T3, as shown in FIG. 4D, the address "A1" of word 2 in address buffer 2 is reached.
Is read and the requests for words 0 and 2 in the buffer are degenerated, and at the same time, word 2 in address buffer 2
Is cleared by the degenerate destination pointer valid bit clear signal 117. Also,
The value of the degeneration flag 121 returns to "0", the buffer read pointer 123 is selected in the selection circuit 13, and the buffer read pointer 125 points to word 1 in the buffer. The above is the operation when the degenerate store is suppressed.

FIG. 2 is a block diagram of a degenerate store control device according to a second embodiment of the present invention. The present degenerate store control device has the same configuration as that of the embodiment shown in FIG. 1 except that the degeneration inhibiting circuit 14 inputs the degeneration destination pointer and the valid bit 110 and outputs the degeneration inhibiting signal 126.

Next, the operation of this embodiment will be described with reference to FIGS. First, the case where the degenerate store is possible will be described.

As shown in FIG. 5 (A), valid addresses "B" are assigned to words 1, 2, 3 in the address buffer 2 respectively.
0 "," F0 ", and" D0 "are stored, and it is assumed that all the words in the degenerate destination pointer buffer 6 are invalid.
Buffer read pointer 125 is word 1 in the buffer
It is assumed that the buffer write pointer 124 points to word 4 in the buffer. Then, this timing is referred to as T0 timing.

When the address "C1" is set in the address write register 1 at the timing T0, the degeneracy detection circuit 3 causes the buffer registration address 101, the addresses of the address buffer words 0 to 5 and the valid bit 1.
Compare each with 02-107. As a result, the value "C1" of the buffer registration address 101 and the value "C0" of the address buffer word 2 address 104 point to the same word, and the address 1 of the address buffer word 2
Since the effective bit of 04 is "1", it is determined that degeneration is possible, and the degeneration permission / inhibition signal 109 with degeneration information and the address comparison result signal 108 are output. The degenerate destination pointer generation circuit 5 receives the address comparison result signal 108, decodes it, and sets it to the degenerate destination pointer and the valid bit 110.
Pointer value that points to the word where C0 "is stored"
2 "and valid bit value" 1 "are output.

Further, the degeneration inhibiting circuit 14 compares the degenerate partner pointer, the valid bit 110, the degenerate partner pointer buffer words 0-5 pointers, and the valid bits 111-116, respectively. Since all valid bit values of the degenerate destination pointer buffer word 0 to 5 pointers and valid bits 111 to 116 are "0", there is no degenerate store in the buffer. Therefore, the degeneration inhibiting signal 126 is output as "1". That is, degeneration is possible.

At the T1 timing, as shown in FIG. 5B, the value "C1" of the buffer registration address 10 and the valid bit "1" are stored in the word 4 of the address buffer 2,
The degenerate destination pointer, the pointer value "2" of the valid bit 110 and the degeneration inhibiting signal 126 value "1" are stored in word 4 of the degenerate destination pointer buffer 6, and at the same time, the buffer write pointer register 12 is incremented by 1. The buffer write pointer 124 points to word 5 in the buffer.

At the T2 timing, as shown in FIG. 5C, the address "B0" of the word 1 in the address buffer 2
Is read, the buffer read pointer register 11 is incremented by 1, and the buffer read pointer 123
Becomes the value "2". The selection circuit 13 selects the buffer read pointer 123, and the buffer read pointer 12
5 refers to word 2 in the buffer.

The pointer coincidence detecting circuit 7 compares the buffer read pointer 125, the degenerate destination pointer buffer word 0 to pointer 5 and each of the valid bits 111 to 116. Value of buffer read pointer 125 "
2 ", the pointer value of the degenerate destination pointer buffer word 4 and the valid bit 115 is" 2 "and the valid bit is" 1 ". Therefore, the addresses" C0 "of the words 2 and 4 in the address buffer 2, It can be understood that the degeneracy of "C1" can be performed, so that the degeneracy flag 118 is output as "1" and the pointer comparison result signal 119 is also outputted.The degenerate store storage pointer generation circuit 9 receives the pointer comparison result signal 119 and decodes it. Then, the degenerate pointer 120 is output as "4".

At timing T3, as shown in FIG. 5D, the address "C0" of word 2 in address buffer 2 is reached.
Is read, the valid bit is cleared and the buffer read pointer register 11 is incremented by 1,
The buffer read pointer 123 has the value “3”. In addition, the value of the degeneration flag 118 is stored in the degeneration flag register 10.
1 ”is set and the value of the degeneration flag 121 becomes“ 1 ”, and the degeneration pointer 120 is set in the degeneration pointer register 11 because the value of the degeneration flag 118 is“ 1 ”.
The value of the degeneration pointer 122 becomes "4".

Since the value of the degeneration flag 122, which is the selection signal, is "1", the selection circuit 14 selects the degeneration pointer 122, and the value of the Huffer read pointer 125 becomes "4", and the word in the buffer is selected. Point 4 Further, since the pointer match detection circuit 7 clears the valid bit of the word 4 of the degenerate destination pointer buffer 6,
The degenerate destination pointer valid bit clear signal 117 is output.

At the timing T4, as shown in FIG. 5E, the address "C1" of the word 4 in the address buffer 2 is read.
Is read and the requests for words 2 and 4 in the buffer are degenerated, and at the same time, word 4 in address buffer 2
Is cleared, and the valid bit of word 4 in the degenerate destination pointer buffer 6 is cleared by the degenerate destination pointer valid bit clear signal 117. Further, the value of the degeneration flag 121 returns to "0", the buffer read pointer 123 is selected in the selection circuit 13, and the buffer read pointer 125 points to the word 3 in the buffer. The above is the operation at the time of degenerate store.

Second, the case of suppressing the degenerate store will be described. When the present invention is applied to an information processing device that only degenerates two requests, the degenerate store suppressing operation described below is required.

As shown in FIG. 6 (A), valid addresses "A0", "" are provided in words 0, 1, 2 in the address buffer 2, respectively.
B0 "and" A1 "are stored, and a valid pointer value" 0 "is stored in word 2 in the destination pointer buffer 6. That is, words 0 and 2 in the buffer can be degenerated. The buffer read pointer 125 points to the word 0 in the buffer, and the buffer write pointer 124 points to the word 4 in the buffer, and this timing is T0.

When the address "A2" is set in the address write register 1 at the timing T0, the degeneration detection circuit 3 causes the buffer registration address 101, the address buffer words 0 to 5 and the valid bit 102.
1 to 107. The value of the buffer registration address 101 is "A2", and the values of the address buffer word 0 and 2 addresses 102 and 104 are "A0" and "A", respectively.
When the valid bit is "1", both valid bits are "1", and there are two degenerate request candidates.
Then, the address comparison result signal 108 is received and decoded. At this time, in order to give priority to the request that occurs earlier in time among the two candidates for the degeneration request, the degeneration destination pointer and the valid bit 110 are output as the pointer value “0” and the valid bit value “1”.

The degeneration inhibiting circuit 14 compares the degenerate partner pointer, the valid bit 110, the degenerate partner pointer buffer words 0 to 5 pointers, and the valid bits 111 to 116, respectively. Degenerate destination pointer buffer word 2 The valid bit of the pointer 113 is "1" and the pointer value is "
Since it is "0", the words 0 and 2 in the buffer have already been subjected to the degenerate store. Therefore, since the degeneration for the address "A2" must be suppressed, the degeneration suppressing signal 126
Is output as "0".

At the T1 timing, as shown in FIG. 6B, the value "A2" of the buffer registration address 101 and the valid bit "1" are stored in the word 3 of the address buffer 2, and the word of the degenerate destination pointer buffer 6 is stored. 3, the degenerate destination pointer, the pointer value “0” of the valid bit 110 and the value “0” of the degeneration suppression signal 126 are stored, and at the same time, the buffer write pointer register 13 is incremented by 1,
The buffer write pointer 124 is the word 4 in the buffer.
Point After that, "A0" and "A1" are degenerated by the same operation as when the degenerate store is not suppressed. The above is the operation when the degenerate store is suppressed.

In this embodiment, the number of words in the store buffer is 6, but the operation is the same in the store buffer having an arbitrary number of words of 3 or more.

[0049]

As described above, according to the present invention, since a store request to be registered in the store buffer and a valid request in the store buffer can be subject to the degenerate store, the degenerate store can be performed more often than before. As a result, the number of requests to the main memory can be reduced, which has the effect of reducing the occupation time of one EPU for the main memory.

Further, in the information processing apparatus which only degenerates two requests, it is possible to prevent degeneration of the third and subsequent requests for the same word in the main memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a diagram for explaining an operation of the embodiment shown in FIG. 1 when degeneration is possible.

FIG. 4 is a diagram for explaining an operation when suppressing a degenerate store in the embodiment shown in FIG.

FIG. 5 is a diagram for explaining an operation in the case where degeneration is possible in the embodiment shown in FIG.

FIG. 6 is a diagram for explaining an operation when suppressing a degenerate store in the embodiment shown in FIG. 2;

[Explanation of symbols]

1 Address Write Register 2 Address Buffer 3 Degeneration Detection Circuit 4 Command Buffer 5 Degeneration Destination Pointer Generation Circuit 6 Degradation Destination Pointer Buffer 7 Pointer Match Detection Circuit 8 Degradation Store Storage Pointer Generation Circuit 9 Degeneration Flag Register 10 Degeneration Pointer Register 11 Buffer Read Pointer register 12 Buffer write pointer register 13 Selection circuit 14 Degeneration suppression circuit 101 Buffer registration address 102 Address buffer word 0 address and valid bit 103 Address buffer word 1 address and valid bit 104 Address buffer word 2 address and valid bit 105 Address buffer word 3 Address and Valid Bit 106 Address Buffer Word 4 Address and Valid Bit 107 Address Buffer Word 5 Address Respond and valid bit 108 Address comparison result signal 109 Degeneration enable / disable signal 110 Degenerate destination pointer and valid bit 111 Degenerate destination pointer Buffer word 0 pointer and valid bit 112 Degenerate destination pointer Buffer word 1 pointer and valid bit 113 Degenerate destination pointer Buffer word 2 pointer and valid bit 114 Degenerate destination pointer Buffer word 3 pointer and valid bit 115 Degenerate destination pointer Buffer word 4 pointer and valid bit 116 Degenerate destination pointer Buffer word 5 pointer and valid bit 117 Degenerate destination pointer valid bit Clear signal 118 Degeneration flag 119 Pointer comparison result signal 120 Degeneration pointer 121 Degeneration flag signal 122 Degeneration pointer signal 123 Buffer read pointer 124 Buffer Pointer 125 buffer read pointer 126 degenerate inhibit signal narrowing see § statement.

Claims (2)

[Claims] 1. A degenerate store control for reducing a plurality of write requests for the same word in the main memory into a single write request, the buffer having a buffer of three or more words for storing a write request for the main memory of the information processing apparatus. In the device, an address buffer for storing a write request address and a valid bit for the main memory of the information processing device, a buffer write pointer register for designating a word for storing the request address in the Adors buffer, and an address buffer in the address buffer. A buffer read pointer register for designating a word for reading a request address, an address write register for supplying a main memory write address to the address buffer, an output of the address write register and the add Degenerate detection circuit that compares the address in each word of the buffer to detect whether degenerate store is possible, and a degenerate destination pointer generation that receives the address comparison result from the degenerate detection circuit and generates a buffer pointer value in which the degenerate partner is stored. A circuit, a degenerate destination pointer buffer with a valid bit that stores the output of the degenerate destination pointer generation circuit, and a buffer read pointer register and pointers in each word of the degenerate destination pointer buffer are compared. A pointer match detection circuit for detecting a match, a degenerate store storage pointer generation circuit for receiving a comparison result of the pointer match detection circuit and generating a pointer value in which a degenerate store is stored, an output of the buffer read pointer register and the Of the degenerate store storage pointer generation circuit A degenerate store control device having a selection circuit for selecting between output and. 2. A degeneration inhibiting circuit is provided for comparing the output of the degenerate destination pointer generation circuit with the pointers in each word of the degenerate destination pointer buffer and inhibiting degeneration when they match. The degenerate store control device according to item 1.