JP2009140324A - Memory access controller and memory access control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory access controller capable of avoiding processing suppression of a processor and discarding of a request packet and capable of efficiently and reliably executing processing, and to provide a memory access control method. <P>SOLUTION: A request packet which can omit an access to a common memory is canceled among the request packet accumulated by an input buffer and a request packet accumulated by an access buffer. For example, when a write request packet of an address identical to that of a read request packet accumulated by the input buffer is present, data written to the common memory by the write request packet are transmitted to a processor as the result of execution of the read request packet, and the read request packet in the input buffer is canceled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory access control device and a memory access control method for controlling access to a shared memory shared by a plurality of processors.

  In the field of supercomputers and the like, a parallel processor system is widely applied in which a single task is distributed and processed in parallel by using a plurality of processors to increase the processing speed of the entire system. In this parallel processor system, data matching is achieved by sharing one shared memory among a plurality of processors, writing data to the shared memory, and reading data stored in the shared memory. In parallel processor systems, a common bus configuration in which a plurality of processors are connected to a shared memory via a single common bus has been common. However, in recent years, each of a plurality of processors is connected via a separate bus. Thus, a one-to-n connection structure connected to a shared memory has been adopted.

  FIG. 1 is a schematic configuration diagram of a parallel processor system having a one-to-n type connection configuration.

  A parallel processor system 100 shown in FIG. 1 includes a shared memory device 101 including a shared memory 110, and a plurality of processors 102_0, 102_1,..., 102_n each connected to the shared memory device 101 via individual buses. Yes.

  The processors 102_0, 102_1,..., 102_n read the write request request packet including the address of the shared memory 110 and the write request for writing data to the shared memory 110, and the address of the shared memory 110 and the data stored in the shared memory 110. One of the request packets 103 of the read request request packet including the read request is transmitted to the shared memory device 101. In FIG. 1, the number before the number shown in the request packet 103 represents each processor 102_0, 102_1,..., 102_n, and the number after the number from each processor 102_0, 102_1,. Indicates the serial number of the transmitted request packet.

  The shared memory device 101 includes transmission / reception units 104_0, 104_1, ..., 104_n and input buffers 105_0, 105_1, ..., 105_n corresponding to the plurality of processors 102_0, 102_1, ..., 102_n, and a plurality of processors 102_0, 102_1, respectively. .., 102_n are provided with an arbitration circuit 106, an access buffer 107, an access register 108, a cache memory 109, and a shared memory 110.

  The transmission / reception units 104_0, 104_1, ..., 104_n receive the request packets 103 transmitted from the processors 102_0, 102_1, ..., 102_n, and store the received request packets 103 in the input buffers 105_0, 105_1, ..., 105_n. To do.

  The arbitration circuit 106 sequentially selects a plurality of request packets 103 stored in the input buffers 105_0, 105_1,..., 105_n one by one according to a predetermined arbitration rule, and the selected request packets 103 are accessed by the access buffer 107. To accumulate. The request packets 103 accumulated in the access buffer 107 are sequentially sent to the access register 108.

  In the access register 108, a read request or a write request included in the stored request packet 103 is executed. When the write request request packet is stored in the access register 108, the target data is written in the storage area indicated by the address in the request packet 103 in the shared memory 110. When the read request request packet is stored in the access register 108, the cache memory 109 is accessed before the shared memory 110. When the target data is stored in the cache memory 109, the data stored in the cache memory 109 is read and returned to the processors 102_1, 102_2,..., 102_n that transmitted the read request request packet. When the target data is not stored in the cache memory 109, the data stored in the storage area indicated by the address in the request packet 103 in the shared memory 110 is read, and the processor 102_1 that has transmitted the read request request packet , 102_2,..., 102_n.

  As described above, according to the parallel processor system having the one-to-n type connection configuration, it is possible to avoid the problem that the shared bus is occupied by one processor and the processing of the entire system stops, The number of processors can be increased without increasing the electrical load applied to one bus, and the efficiency of distributed / parallel processing can be improved. Furthermore, even if a failure occurs in some of the plurality of buses connecting the processors 102_1, 102_2,..., 102_n and the shared memory device 101, the processors connected by other buses Then, since the shared memory 110 can be accessed, there is an advantage that the fault can be easily isolated.

In many cases, the shared memory is provided with a storage area that can be accessed from any processor and a storage area that is permitted to be accessed only by a specific processor. In this regard, Patent Document 1 sets an inaccessible area that prohibits access from another processor to the shared memory at the start of the operation of each processor, and accesses the inaccessible area from the other processor. It describes a shared memory access method for stopping execution of an access request when a request is transmitted. By applying the access method described in Patent Document 1, even if the number of processors connected to the shared memory is increased or changed, data in a storage area that is not permitted to be accessed is erroneously stored. Problems such as overwriting can be avoided.
Japanese Patent Laid-Open No. 08-16529

  By the way, in recent years, the processing speed of the entire parallel processor system has been improved with the improvement of the performance of the processor. On the other hand, when the request packets 103 transmitted from each of the plurality of processors 102_1, 102_2,..., 102_n are concentrated, the arbitration processing of the request packet 103 by the arbitration circuit 106 cannot catch up, and the transmission / reception units 104_1, 104_1 The request packets 103 successively received by 104_2,..., 104_n may not be stored in the input buffers 105_1, 105_2,. In this case, a stop request (Back Pressure signal 116) of the request packet 103 is issued toward each processor 102_1, 102_2,..., 102_n, and the processing of each processor 102_1, 102_2,. The processing speed of the entire system is reduced. Further, if the bursty traffic continues, the request packet 103 overflowing in the input buffers 105_1, 105_2,..., 105_n and the access buffers 107_1, 107_2, ..., 107_n may not be processed and discarded. There is also a problem that the reliability of the parallel processor system is lowered.

  In view of the above circumstances, an object of the present invention is to provide a memory access control device and a memory access control method that can efficiently and reliably execute processing while avoiding processor processing suppression and request packet discarding. And

The memory access control device of the present invention that achieves the above object is a memory access control device that controls access to a shared memory shared by a plurality of processors.
A plurality of input buffers for storing, for each of the plurality of processors, a request packet including a distinction between a write request and a read request and a shared memory address, which is issued from each of the plurality of processors and requests access to the shared memory. When,
An access buffer that stores request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer, the search unit uses the write request request packet having the same address in the access buffer. The data to be written to the shared memory is taken out from the access buffer, sent to the processor that issued the read request request packet with the same address among the plurality of processors, and the preceding processing unit that cancels the read request request packet with the same address; It is characterized by having.

  According to this memory access control device, when a write request request packet having the same address as the read request request packet stored in the input buffer exists in the access buffer, the data written to the shared memory by the write request request packet is The read request request packet is sent to the processor as an execution result, and the read request request packet in the input buffer is canceled. For this reason, after the data is written to the shared memory by the write request request packet accumulated in the access buffer, the read request request packet accumulated in the input buffer is further selected by the arbitration unit and stored in the access buffer. A series of processes in which the same data written by the previous write request request packet is read from the shared memory can be omitted, and the processing speed and the processing efficiency can be improved. In addition, request packets that accumulate in the input buffer and access buffer decrease due to improvements in processing efficiency and processing speed, so that the request packets overflow and request packets that cannot be processed are discarded. And the reliability of the entire apparatus can be improved.

A memory access control device of the present invention that achieves the above object is a memory access control device that controls access to a shared memory shared by a plurality of processors.
A plurality of input buffers for storing, for each of the plurality of processors, a request packet including a distinction between a write request and a read request and a shared memory address, which is issued from each of the plurality of processors and requests access to the shared memory. When,
An access buffer that stores request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer, a write request request packet having the same address in the access buffer is detected. And a preceding processing unit to cancel.

  According to the memory access control device, when a write request request packet having the same address as the write request request packet stored in the input buffer exists in the access buffer, the write request request packet in the access buffer is canceled. . If multiple write request request packets that write data to the same address are detected, the previous write request request packet is canceled and only the subsequent write request request packet is executed, thereby saving unnecessary processing. The processing speed can be increased.

A memory access control device of the present invention that achieves the above object is a memory access control device that controls access to a shared memory shared by a plurality of processors.
A plurality of input buffers for storing, for each of the plurality of processors, a request packet including a distinction between a write request and a read request and a shared memory address, which is issued from each of the plurality of processors and requests access to the shared memory. When,
An access buffer that stores request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
Search for request packets stored in the input buffer across multiple input buffers, and use the same address as the read request request packet stored in one of the multiple input buffers. A search unit for detecting whether there is a write request request packet selected prior to the read request request packet by the unit;
A write request request packet that is selected by the search unit prior to the read request request packet and having the same address as the read request request packet stored in one of the plurality of input buffers. Is detected from among the plurality of processors, and the read request request packet with the same address is issued from among the plurality of processors. And a preceding processing unit for canceling the read request request packet with the same address.

  According to this memory access control device, a write request request packet having the same address across a plurality of input buffers and selected before a read request request packet is searched, and written to the shared memory by the write request request packet Data is sent to the processor as the execution result of the read request request packet, and the read request request packet is canceled. As described above, since a read request request packet that can omit access to the shared memory is canceled among a plurality of input buffers, the processing load in the arbitration unit can be reduced and the processing performance of the entire system can be improved. it can.

A memory access control device of the present invention that achieves the above object is a memory access control device that controls access to a shared memory shared by a plurality of processors.
A plurality of input buffers for storing, for each of the plurality of processors, a request packet including a distinction between a write request and a read request and a shared memory address, which is issued from each of the plurality of processors and requests access to the shared memory. When,
An access buffer that stores request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
Search for request packets stored in the input buffer across multiple input buffers, and use the same address as the write request request packet stored in one of the multiple input buffers. A search unit for detecting whether there is a write request request packet selected prior to the write request request packet by the unit;
A second address that is selected by the search unit before the write request request packet by the arbitrating unit and has the same address as the write request request packet stored in any one of the plurality of input buffers. And a preceding processing unit that cancels the second write request request packet when it is detected that a write request request packet exists.

  According to this memory access control device, when a plurality of write request request packets for the same address are searched across a plurality of input buffers, the second write selected first among those write request request packets. Since the request request packet is canceled, useless processing can be surely omitted.

In addition, the memory access control method of the present invention that achieves the above object is characterized in that a write request and a read request are issued separately from a write request and a read request that are issued from each of a plurality of processors and are shared by a plurality of processors. A plurality of input buffers for storing a request packet including a shared memory address for each of the plurality of processors;
An access buffer that stores request packets in the order of access to the shared memory;
A memory access control method in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in an input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer; Because
A search step of searching the access buffer and detecting whether or not a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When the search step detects that a write request request packet with the same address as the read request request packet existing in the input buffer exists in the access buffer, the write request request packet with the same address in the access buffer Data to be written to the shared memory is extracted from the access buffer, sent to the processor that issued the read request request packet with the same address, and the execution processing step for canceling the read request request packet with the same address. It is characterized by having.

  According to this memory access control method, the execution result of the read request request packet in the input buffer is confirmed in advance using the write request request packet stored in the access buffer, and the read request request packet in the input buffer is canceled. Therefore, the processing efficiency of the entire system can be improved.

In addition, the memory access control method of the present invention that achieves the above-described object provides a method for requesting access to a shared memory that is shared by a plurality of processors and that is issued from each of a plurality of processors, and separates and shares a write request and a read request. A plurality of input buffers for storing a request packet including a memory address for each of the plurality of processors;
An access buffer that stores request packets in the order of access to the shared memory;
A memory access control method in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in an input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer; Because
A search step of searching the access buffer and detecting whether or not a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer;
If the search step detects that there is a write request request packet having the same address as the write request request packet existing in the input buffer in the access buffer, the write request request packet having the same address in the access buffer is And an execution processing step for canceling.

  According to this memory access control method, when a write request request packet with the same address exists in both the access buffer and the input buffer, the write request request packet in the previously selected access buffer is canceled. The processing load in the processing unit can be reduced.

In addition, the memory access control method of the present invention that achieves the above-described object provides a method for requesting access to a shared memory that is shared by a plurality of processors and that is issued from each of a plurality of processors, and separates and shares a write request and a read request. A plurality of input buffers for storing a request packet including a memory address for each of the plurality of processors;
An access buffer that stores request packets in the order of access to the shared memory;
A memory access control method in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in an input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer; Because
Search for request packets stored in the input buffer across multiple input buffers, and use the same address as the read request request packet stored in one of the multiple input buffers. A search step for detecting whether or not there is a write request request packet selected prior to the read request request packet by the unit;
A write request request packet having the same address as the read request request packet stored in any one of the plurality of input buffers by the detection step, and selected before the read request request packet by the arbitration unit Is detected from among the plurality of processors, and the read request request packet with the same address is issued from among the plurality of processors. And an execution processing step for canceling a read request request packet with the same address.

  According to this memory access control method, an omissible read request request packet is searched across a plurality of input buffers, and the retrieved read request request packet is canceled, so that the processing load by the arbitration unit can be reduced. The processing speed of the entire system can be increased.

In addition, the memory access control method of the present invention that achieves the above-described object provides a method for requesting access to a shared memory that is shared by a plurality of processors and that is issued from each of a plurality of processors, and separates and shares a write request and a read request. A plurality of input buffers for storing a request packet including a memory address for each of the plurality of processors;
An access buffer that stores request packets in the order of access to the shared memory;
A memory access control method in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in an input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer; Because
Search for request packets stored in the input buffer across multiple input buffers, and use the same address as the write request request packet stored in one of the multiple input buffers. A search step for detecting whether or not there is a write request request packet selected before the write request request packet by the unit;
The detection step has a second address that is the same address as the write request request packet stored in any one of the plurality of input buffers and is selected by the arbitrating unit prior to the write request request packet. An execution processing step for canceling the second write request request packet when it is detected that the write request request packet exists.

  According to this memory access control method, it is searched whether there is an omissible write request request packet across a plurality of input buffers, and the second write request request packet is canceled. Efficiency can be improved.

  According to the present invention, it is possible to efficiently and reliably execute processing by avoiding processor processing suppression and request packet discarding.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a schematic configuration diagram of a parallel processor system to which an embodiment of the present invention is applied.

  A parallel processor system 200 shown in FIG. 2 is a parallel processor system having a one-to-n connection structure in which a plurality of processors are connected to one shared memory by individual buses. The parallel processor system 200 includes a shared memory device 201 and a plurality of processors 202_0, 202_1,..., 202_n. The shared memory device 201 corresponds to each of the plurality of processors 202_0, 202_1,. 204_n, a plurality of input buffers 205_0, 205_1, ..., 205_n, and a plurality of input registers 206_0, 206_1, ..., 206_n and a plurality of processors 202_0, 202_1, ..., 202_n. An arbitration unit 221, a buffer search control unit 230, an access buffer 222, an access register 223, a cache memory 224, and a shared memory 240.

  The processors 202_0, 202_1,..., 202_n direct the request packet 300 (see FIG. 3) including a write request to write data to the shared memory 240 and a read request to read data stored in the shared memory 240 to the shared memory device 201. To send.

  FIG. 3 is a conceptual configuration diagram of a request packet.

  In the request packet 300, “0 (waiting for access to the shared memory 240)” is set as an initial value, and “1 (R / W request cancellation)” is set when a read request or a write request is canceled. The flag 301, the CPU ID 302 that is the identification number of the processor 202_0, 202_1,..., 202_n that has transmitted the request packet 300, and the R / W information 303 indicating one of the read request (R) and the write request (W). And an address 304 indicating a storage area of the shared memory 240 and data 305 in which write data written by a write request and read data read by a read request are set. The request packet 300 corresponds to an example of a request packet according to the present invention. In FIG. 2, the numbers before the numbers shown in the request packet 300 represent the processors 202_0, 202_1,..., 202_n, and the numbers after the processors 202_0, 202_1,. Indicates the serial number of the transmitted request packet.

  The request packet 300 transmitted from the processors 202_0, 202_1,..., 202_n is received by the transmission / reception units 204_0, 204_1,.

  The request packet 300 received by the transmission / reception units 204_0, 204_1,..., 204_n is temporarily stored in the input buffers 205_0, 205_1,. The request packets 300 accumulated in the input buffers 205_0, 205_1,..., 205_n are transmitted to the input registers 206_0, 206_1,. The input buffers 205_0, 205_1,..., 205_n correspond to an example of the input buffer referred to in the present invention.

  The buffer search control unit 230 includes a search request unit 401, a result determination unit 501, and an address comparison unit 234. The address comparison unit 234 includes a plurality of storage buffers 222_0 and 222_1 that constitute the access buffer 222. ,..., 222_XX, each of which includes a plurality of comparison units 601_0, 601_1,.

  The search request unit 401 transmits a plurality of request packets 300 acquired from the input buffers 205_0, 205_1,..., 205_n to the address comparison unit 234.

  The address comparison unit 234 includes request packets 300 stored in a plurality of storage buffers 222_0, 222_1,..., 222_XX that constitute the access buffer 222, and request packets 300 stored in input buffers 205_0, 205_1,. The request packet 300 that can omit the access to the shared memory 240 is searched. The search result is transmitted to the result determination unit 501.

  The result determination unit 501 sets “1 (cancel R / W request)” to the cancellation flag 301 of the request packet 300 searched by the address comparison unit 234, and requests acquired from the input buffers 205_0, 205_1,. The packet 300 is sent to the input registers 206_0, 206_1,..., 206_n, and the request packet 300 transmitted from the access buffer 222 is sent to the access buffer 222.

  The buffer search control unit 230 corresponds to an example of a preceding processing unit according to the present invention. The processing in the buffer search control unit 230 will be described in detail later.

  The input registers 206_0, 206_1,..., 206_n direct the request packet 300 in which “1 (R / W request cancel)” is set in the cancel flag 301 illustrated in FIG. 3 to the corresponding processors 202_0, 202_1,. While replying, the request packet 300 is canceled.

  The arbitration unit 221 sequentially selects the request packets 300 stored in the plurality of input registers 206_0, 206_1,..., 206_n according to a predetermined selection rule and stores them in the access buffer 222. In the present embodiment, a round robin method in which request packets 300 stored in a plurality of input registers 206_0, 206_1,..., 206_n are selected one by one in order from the left side of the drawing is applied as a selection rule. The arbitration unit 221 corresponds to an example of an arbitration unit referred to in the present invention.

  The access buffer 222 includes a plurality of accumulation buffers 222_1, 222_2,..., 222_XX, and the request packets 300 selected by the arbitration unit 221 are sequentially stored. The request packet 300 stored in the access buffer 222 is first extracted from the previously stored packet and sent to the access register 223. The access buffer 222 corresponds to an example of the access buffer according to the present invention.

  The access register 223 cancels the request packet 300 when “1 (R / W request cancellation)” is set in the cancel flag 301 of the stored request packet 300. If the cancel flag 301 of the request packet 300 is “0 (waiting for access to the shared memory 240)”, the request packet 300 is executed to access the shared memory 240. That is, when the R / W information 303 shown in FIG. 3 in the request packet 300 is a write request “W”, the document set in the data unit 305 at the address 304 included in the request packet 300 in the shared memory 240. Embedded data is written. When the R / W information 303 shown in FIG. 3 in the request packet 300 is a read request “R”, the cache memory 224 is accessed before the shared memory 240. When the cache memory 224 stores the data of the address 304 included in the request packet 300 of the shared memory 240, the data stored in the cache memory 224 is read and the target data is stored in the cache memory 224. If not, the data of the address 304 included in the request packet 300 in the shared memory 240 is read. The read data is set in the data part 305 in the request packet 300, and the request packet 300 in which the read data is set is sent to the processors 202_0, 202_1,.

  Basically, access to the shared memory 240 is executed as described above.

  Here, in the present embodiment, the buffer search control unit 230 sets “1 (R / W request cancel)” to the cancel flag 301 of the request packet 300 that can omit access to the shared memory 240, The request packet 300 is cancelled.

  4 is a functional block diagram of the search request unit 401, FIG. 5 is a functional block diagram of the result determination unit 501, and FIG. 6 is a functional block diagram of the comparison units 601_0, 601_1,..., 601_XX.

  FIG. 7 is a flowchart showing a flow of a series of processes for canceling the request packet 300.

  In the following, a series of processing for canceling the request packet 300 will be described by explaining the constituent elements of the buffer search control unit 230 using FIG. 4, FIG. 5, and FIG. 6 according to the flowchart of FIG.

  As illustrated in FIG. 4, the search request unit 401 of the buffer search control unit 230 has functions as a search request selector 402, an address extraction unit 403, and a search arbitration unit 404.

  The search arbitration unit 404 obtains an arbitration signal 231 indicating a selection rule for selecting the request packet 300 from the input buffers 205_0, 205_1,..., 205_n from the arbitration unit 221 shown in FIG. 2 (step S11 in FIG. 7). The acquired arbitration signal 231 is transmitted to the search request selector 402 and also transmitted to the result determination unit 501 as a search arbitration signal 232.

  Prior to the arbitration unit 221, the search request selector 402 extracts request packets 300 one by one from the input buffers 205_0, 205_1,..., 205_n in the order according to the selection rule indicated by the arbitration signal 231 (step in FIG. 7). S12). The selected request packet 300 is transmitted to the address extraction unit 403.

  The address extraction unit 403 extracts the R / W information 303 and the address 304 in the request packet 300 transmitted from the search request selector 402. The post-extraction request packet 300_1 is transmitted to the address comparison unit 234 shown in FIG.

  As shown in FIG. 6, each of the comparison units 601_0, 601_1,..., 601_XX constituting the address comparison unit 234 has functions as an address comparison / R / W confirmation unit 602 and a cancel flag addition unit 603. Yes.

  In the address comparison / R / W confirmation unit 602, the extracted request packets 300_1 are sequentially transmitted from the address extraction unit 403 of the search request unit 401 shown in FIG. 4 one by one, and each comparison unit 601_0 in the access buffer 222 is transmitted. , 601_1,..., 601_XX, the request packet 300 is transmitted from the accumulation buffers 222_0, 222_1,..., 222_XX (step S13 in FIG. 7).

  Further, the address comparison / R / W confirmation unit 602 determines whether the address 304 of the request packet 300 acquired from the access buffer 222 is the same as the address 304 of the extracted request packet 300_1 transmitted from the address extraction unit 403. Determination is made (step S14 in FIG. 7).

  When the address 304 of the request packet 300 and the extracted request packet 300_1 do not match (step S14 in FIG. 7: mismatch), the next extracted request packet 300_1 is acquired from the address extracting unit 403 of the search request unit 401, The request packet 300 is obtained again from the access buffer 222 (step S13 in FIG. 7), and the new post-extraction request packet 300_1 and the address 304 of each new request packet 300 are compared (step S14 in FIG. 7).

  When the address 304 of the request packet 300 and the extracted request packet 300_1 match (step S14 in FIG. 7: match), the R / W information 303 in the request packet 300 is confirmed (step S13 in FIG. 7).

  When the R / W information 303 in the request packet 300 acquired from the access buffer 222 is “R (read request)” (step S15: Read in FIG. 7), a new post-extraction request packet 300_1 and a new A plurality of request packets 300 are acquired (step S13 in FIG. 7), the address 304 is compared (step S14 in FIG. 7), and the R / W information 303 is confirmed (step S15 in FIG. 7).

  Further, the R / W information 303 in the request packet 300 acquired from the access buffer 222 is “W (write request)” (step S15: Write in FIG. 7), and the R / W information in the post-extraction request packet 300_1. If 303 is “R (read request)” (step S16 in FIG. 7: Read), the read request request packet 300 in the input buffers 205_0, 205_1,... Access to the shared memory 240 is omitted. That is, after the data is written by the write request request packet, the read request request packet that reads the data at the same address is canceled.

  First, in the address comparison / R / W confirmation unit 602 shown in FIG. 6, the write data set in the data unit 305 in the write request request packet 300 transmitted from the access buffer 222 is acquired, and the extracted request packet 300_1 is extracted. A response request packet 300_2 with write data added to is generated. The generated response request packet 300_2 is transmitted to the result determination unit 501 shown in FIG. 5 (step S17 in FIG. 7).

  As shown in FIG. 5, the result determination unit 501 has functions as a latest data selection unit 502, a cancel flag addition unit 503, and a request source selection unit 504.

  The response request packet 300_2 transmitted from the address comparison / R / W confirmation unit 602 is acquired by the latest data selection unit 502. In this embodiment, since the comparison processing of each of the plurality of request packets 300 accumulated in the access buffer 222 and the extracted request packet 300_1 is performed in parallel, the latest data selection unit 502 includes one post-extraction The response request packet 300_2 may be transmitted from the plurality of comparison units 601_1, 601_2, ..., 601_XX to the request packet 300_1. In the latest data selection unit 502, when a plurality of response request packets 300_2 are acquired for one post-extraction request packet 300_1, the latest response request packet 300_2 (most recently among the plurality of response request packets 300_2) is acquired. The response request packet 300_2) to be executed is selected. The selected response request packet 300_2 is transmitted to the cancel flag adding unit 503.

  In the cancel flag adding unit 503, the cancel flag 301 is added to the response request packet 300_2, and “1 (R / W request cancel)” is set in the cancel flag 301. The response request packet 300_2 to which the cancel flag 301 is added is transmitted to the request source selection unit 504.

  In the request source selection unit 504, the response request packet 300_2 is overwritten on the request packet 300 that is the source of the extraction request packet 300_1, and a new request packet 300 is added to the processors 202_0, 202_1,... Indicated by the DPUID 302 in the request packet 300. , 202_n are transmitted to the input registers 206_0, 206_1,..., 206_n (step S18 in FIG. 7).

  At this time, among the request packets 300 stored in the input registers 206_0, 206_1,..., 206_n, a read request request packet in which a write request request packet for the same address exists in the access buffer 222 is displayed in the cancel flag 301 as “ 1 (R / W request cancellation) ”is set, and the write data of the write request request packet is set in the data portion 305.

  In the input registers 206_0, 206_1,..., 206_n, the request packet 300 in which “1 (R / W request cancellation)” is set in the cancel flag 301 is transmitted to the transmission / reception units 204_0, 204_1,. In the transmission / reception units 204_0, 204_1,..., 204_n, the request packets 300 transmitted from the input registers 206_0, 206_1, ..., 206_n are processor units 202_0, 202_1,. 202_n is returned (step S19 in FIG. 7).

  Further, in the input registers 206_0, 206_1,..., 206_n, the execution of the request packet 300 is canceled by discarding the request packet 300 in which “1 (R / W request cancel)” is set in the cancel flag 301. (Step S20 in FIG. 7).

  FIG. 8 is a conceptual diagram showing the flow of a request packet until the read request request packet is canceled.

  The request packet 300 (1) transmitted from each of the processors 202_0, 202_1,..., 202_n and accumulated in the input buffers 205_0, 205_1, ..., 205_n is transferred to the input registers 206_0, 206_1,. Is done. Further, the arbitration signal 231 (2) acquired from the arbitration unit 221 is transmitted to the result determination unit 501 through the search request unit 401.

  The request packets 300 (3) received by the search request unit 401 are transmitted to the comparison units 601_0, 601_1,... 601_XX one by one in the order according to the arbitration signal 231 (2). Further, the comparison units 601_0, 601_1,..., 601_XX acquire the request packet 300 (4) stored in the accumulation buffers 222_0, 222_1,..., 222_XX of the access buffer 222, and read “Read request request packet in the input buffer”. Is searched for in the access buffer having the same address. In the example shown in FIG. 8, the R / W information 303 of the request packet 310 stored in the left input buffer 205_0 is “R (read request)”, and the address 304 is “address A”. For this read request request packet 310, the R / W information 303 of the request packet 330 stored in the second buffer 222_02 in the access buffer 222 is “W (write request)”, and the address 304 is “address A”. It is determined that the write request request packet 330 matches the search condition.

  The response request packet (5) that is the search result is transmitted to the result determination unit 501. Further, the read request answer data 320 generated based on the response request packet (5) is transmitted to the transmission / reception units 204_0, 204_1,..., 204_n via the input registers 206_0, 206_1,. 202_1, ..., 202_n are returned. In the example of FIG. 8, in the result determination unit 501, “1 (R / W request cancellation)” is set in the cancellation flag 301, and “data” set in the data unit 305 of the write request request packet 330 is stored in the data unit 305. Read request answer data 320 in which “I” is set is generated, and the read request answer data 320 is transmitted to the transmission / reception unit 204_0 via the input register 206_0 and returned to the processor 202_0.

  As described above, according to the present embodiment, when a request packet stored in the access buffer includes a write request request packet for writing data to the same address as the read request request packet stored in the input buffer. Since the write data written by the write request request packet is returned as the return data of the read request request packet and the read request request packet is canceled, access to the shared memory 240 can be omitted. In addition, by canceling the read request request packet with the input register, it is possible to reduce the load of selection processing in the arbitration unit 221 and to increase the processing speed of the entire system.

  The read request request packet is canceled as described above.

  Further, in step S15 in FIG. 7, the R / W information 303 in the request packet 300 acquired from the access buffer 222 is “W (write request)” (step S15: Write in FIG. 7), and the extracted request packet When the R / W information 303 in 300_1 is also “W (write request)” (step S16 in FIG. 7: Write), access to the shared memory 240 by the write request request packet 300 acquired from the access buffer 222 is performed. Omitted. That is, among the plurality of write request request packets that write data to the same address, the write request request packet that is executed first is canceled.

  First, in the address comparison / R / W confirmation unit 602 shown in FIG. 6, the write request request packet 300 acquired from the access buffer 222 is transmitted to the cancel flag addition unit 603.

  In the cancel flag addition unit 603, “1 (R / W request cancel)” is set in the cancel flag 301 of the write request request packet 300 transmitted from the address comparison / R / W confirmation unit 602 (step S21 in FIG. 7). A new write request request packet 300 is transmitted to the access buffer 222.

  At this time, among the request packets 300 stored in the plurality of accumulation buffers 222_0, 222_1,..., 222_XX of the access buffer 222, write request request packets to the same address 304 are stored in the input buffers 205_0, 205_1,. For existing write request request packets, “1 (R / W request cancel)” is set in the cancel flag 301.

  Request packets 300 stored in the access buffer 222 are sent to the access register 223 one by one. In the access register 223, the request packet 300 in which “0 (waiting for access to the shared memory 240)” is set in the cancel flag 301 is executed, and “1 (R / W request cancel)” is set in the cancel flag. The request packet 300 is discarded and the execution of the request packet 300 is canceled (step S22 in FIG. 7).

  FIG. 9 is a conceptual diagram showing the flow of a request packet until the write request request packet is canceled.

  First, as in the case of canceling the read request request packet shown in FIG. 8, the search request unit 401 uses the request packet 300 (1) in the input buffers 205_0, 205_1,..., 205_n and the arbitration signal 231 (2). Is acquired. The comparison units 601_0, 601_1,..., 601_XX obtain the request packet 300 (3) in the input buffers 205_0, 205_1,..., 205_n and the request packet 300 (4) in the access buffer 222. When canceling the write request request packet, the comparison units 601_0, 601_1,..., 601_XX search for “write request request packet in the access buffer having the same address as the write request request packet in the input buffer”. In the example shown in FIG. 9, the R / W information 303 of the request packet 340 stored in the left input buffer 205_0 is “W (write request)”, and the address 304 is “address A”. For this read request request packet 310, the R / W information 303 of the request packet 330 stored in the second buffer 222_02 in the access buffer 222 is “W (write request)”, and the address 304 is “address A”. It is determined that the write request request packet 330 matches the search condition.

  In the comparison unit 601_2 in which the write request request packet 330 is searched, “1 (R / W request cancel)” is set in the cancel flag of the write request request packet 330, and the new write request request packet 330 is overwritten in the buffer 222_2. The

  As described above, according to the present embodiment, when the request packet stored in the access buffer includes a write request request packet for writing data to the same address as the write request request packet stored in the input buffer. Since the write request request packet in the access buffer to be executed first is canceled, useless processing can be omitted and the processing efficiency can be improved. In addition, because the request packets accumulated in the access buffer and input buffer decrease due to the improvement in processing efficiency, it is possible to avoid the problem that the request packets overflow and the request packets that can not be processed are discarded, The processing can be executed reliably.

  Above, description of 1st Embodiment of this invention is complete | finished and 2nd Embodiment of this invention is described. The second embodiment of the present invention is different from the first embodiment in the configuration of the buffer search control unit, but otherwise has the same configuration as in the first embodiment, so FIG. Only the differences from the first embodiment will be described using the description.

  FIG. 10 is a configuration diagram of the buffer search control unit in the present embodiment.

  Similar to the buffer search control unit 230 of the first embodiment shown in FIG. 2, the buffer search control unit 1001 in this embodiment includes a search request unit 1101, a result determination unit 1003, and an address comparison unit 1004. The address comparison unit 1004 includes a plurality of comparison units 1301_0, 1301_1,..., 1301_XX corresponding to the plurality of storage buffers 222_0, 222_1,. The result determination unit 1003 is different from the first embodiment in that a plurality of determination units 1401_0, 1401_1,..., 1401_n corresponding to the plurality of input buffers 205_0, 205_1,.

  FIG. 11 is a functional block diagram of the search request unit 1101.

  The search request unit 1101 of the present embodiment includes an address comparison / R / W confirmation unit 1201 and a plurality of address extraction units 1103_0, 1103_1,..., 1103_n corresponding to the plurality of input buffers 205_0, 205_1,. The function is provided.

  A plurality of request packets 300 acquired one by one from each of the plurality of input buffers 205_0, 205_1,..., 205_n are respectively address extraction units 1103_0, 1103_1, ..., 1103_n corresponding to the respective input buffers 205_0, 205_1,. And also to the address comparison / R / W confirmation unit 1201.

  The address extraction units 1103_0, 1103_1,..., 1103_n generate a post-extraction request packet 300_1 in which the R / W information 303 and the address 304 in the request packet 300 are extracted. The generated post-extraction request packet 300_1 is sent simultaneously from each of the address extraction units 1103_0, 1103_1,..., 1103_n to each of a plurality of comparison units 1301_0, 1301_1, ..., 1301_XX constituting the address comparison unit 1004. That is, a plurality of post-extraction request packets 300_1 acquired from the plurality of input buffers 205_0, 205_1,..., 205_n are transmitted to the comparison units 1301_0, 1301_1,.

  FIG. 12 is a functional block diagram of the comparison units 1301_0, 1301_1,..., 1301_XX in the present embodiment.

  Each of the comparison units 1301_0, 1301_1,..., 1301_XX includes a cancel flag addition unit 1303 and a plurality of address comparison / R / W confirmation units 1302_0, 1302_1, respectively corresponding to the plurality of address extraction units 1103_0, 1103_1,. .., 1302_n are provided.

  In each of the comparison units 1301_0, 1301_1,..., 1301_XX, the request packets 300 stored in the corresponding storage buffers 222_0, 222_1,..., 222_XX in the access buffer 222 are acquired, and the address extraction unit illustrated in FIG. 1103_0, 1103_1, ..., 1103_n, a plurality of post-extraction request packets 300_1 are also acquired. The request packet 300 transmitted from the access buffer is acquired by all the address comparison / R / W confirmation units 1302_0, 1302_1,..., 1302_n, and after a plurality of extractions transmitted from the address extraction units 1103_0, 1103_1,. The request packet 300_1 is acquired by the corresponding address comparison / R / W confirmation unit 1302_0, 1302_1, ..., 1302_n.

  The address comparison / R / W confirmation units 1302_0, 1302_1,..., 1302_n determine whether or not the addresses set in the addresses 304 of the request packet 300 and the extracted request packet 300_1 match. In this embodiment, a plurality of comparison units 1301_0, 1301_1,..., 1301_XX corresponding to the plurality of storage buffers 222_0, 222_1,..., 222_XX constituting the access buffer 222 are provided, and each comparison unit 1301_0 is provided. , 1301_1,..., 1301_XX are provided with a plurality of address comparison / R / W confirmation units 1302_0, 1302_1,..., 1302_n corresponding to the plurality of input buffers 205_0, 205_1,. Therefore, in the address comparison unit 1004 as a whole, a plurality of request packets 300 accumulated in the access buffer 222 and a plurality of request packets 300 accumulated in the input buffers 205_0, 205_1,. And a post-extraction request packet 300_1 from which a part of the request packet is extracted is used at the same time.

  In the address comparison / R / W confirmation unit 1302_0, 1302_1,..., 1302_n, the request packet 300 acquired from the access buffer 222 and the post-extraction request packet 300_1 transmitted from the address extraction units 1103_0, 1103_1,. If the addresses match, the R / W information 303 of the request packet 300 and the extracted request packet 300_1 is confirmed.

  When the R / W information 303 of the request packet 300 is “W (write request)” and the R / W information 303 of the extracted request packet 300_1 is “W (write request)”, the request packet 300 has a cancel flag added. Part 1303. In the cancel flag adding unit 1303, “1 (R / W request cancel)” is set in the cancel flag 301 of the request packet 300 and the new request packet 300 is transmitted to the access buffer 222, as in the first embodiment. .

  In the access register 223 shown in FIG. 2, the request packet 300 in which “0 (waiting for access to the shared memory 240)” is set in the cancel flag 301 is executed, and “1 (R / W request cancel)” is set in the cancel flag. The request packet 300 for which “is set” is discarded, and the execution of the request packet 300 is cancelled.

  Further, in the address comparison / R / W confirmation units 1302_0, 1302_1,..., 1302_n, the request packet 300 acquired from the access buffer 222 and the post-extraction request packet 300_1 transmitted from the address extraction units 1103_0, 1103_1,. When the addresses match, the R / W information 303 of the request packet 300 is “W (write request)”, and the R / W information 303 of the extracted request packet 300_1 is “R (read request)”. Then, a response request packet 300_2 in which the write data set in the data part 305 in the request packet 300 is added to the post-extraction request packet 300_1 is generated. The generated response request packet 300_2 is transmitted to determination units 1401_0, 1401_1, ..., 1401_n corresponding to the address comparison / R / W confirmation units 1302_0, 1302_1, ..., 1302_n of the result determination unit 1003 shown in FIG. .

  FIG. 13 is a functional block diagram of the determination units 1401_0, 1401_1,..., 1401_n constituting the result determination unit 1003.

  Each determination unit 1401_0, 1401_1,..., 1401_n constituting the result determination unit 1003 is provided with a function as an answer data selection unit 1402 and a cancel flag addition unit 1403.

  The answer data selection unit 1402 acquires the response request packet 300_2 transmitted from each of the plurality of comparison units 1301_0, 1301_1, ..., 1301_XX. When a plurality of response request packets 300_2 are acquired, the latest response request packet 300_2 (the response request packet 300_2 to be executed last) is selected from among the plurality of response request packets 300_2, and a cancel flag is selected. This is transmitted to the addition unit 1403.

  In the cancel flag adding unit 1403, the data set in the data unit 305 of the response request packet 300_2 is set in the data unit 305 of the request packet 300 that is the origin of the response request packet 300_2, and “1 (R / W request cancel) ”is set, and a new request packet 300 is transmitted to the corresponding input registers 206_0, 206_1,.

  In the input registers 206_0, 206_1,..., 206_n, the request packet 300 in which “1 (R / W request cancellation)” is set in the cancel flag 301 is transmitted to the transmission / reception units 204_0, 204_1,. In 204_1,..., 204_n, the request packet 300 is returned as answer packet data to the corresponding processor units 202_0, 202_1,. Further, in the input registers 206_0, 206_1,..., 206_n, the request packet 300 transmitted to the transmission / reception units 204_0, 204_1,.

  As described above, according to the present embodiment, a plurality of request packets stored in each of a plurality of input buffers and a plurality of request packets stored in each of a plurality of access buffers are compared at the same time and can be omitted. Since the packet is searched, the processing can be speeded up.

  Here, in the above, in the search request unit 1101 shown in FIG. 11, the request packets 300 accumulated in the input buffers 205_0, 205_1,..., 205_n are acquired by the address extraction units 1103_0, 1103_1,. Although 300_1 is transmitted to the comparison units 1301_0, 1301_1,..., 1301_n of the address comparison unit 1004 and compared with the request packet 300 stored in the access buffer 222, the search request unit 1101 The request packet 300 transmitted from the buffers 205_0, 205_1,..., 205_n is also acquired by the address comparison / R / W confirmation unit 1201.

  FIG. 14 is a diagram showing a flow of processing in the address comparison / R / W confirmation unit 1201.

  The address comparison / R / W confirmation unit 1201 acquires a plurality of request packets 300 transmitted one by one from each of the plurality of input buffers 205_0, 205_1,..., 205_n, and from the arbitration unit 221 shown in FIG. The arbitration signal 231 indicating the selection rule for selecting the request packet 300 is also acquired from the input buffers 205_0, 205_1,.

  In the address comparison / R / W confirmation unit 1201, the plurality of acquired request packets 300 are compared in the order according to the selection rule indicated by the arbitration signal 231, and the addresses set in the address 304 are the same. A set of request packets 300 in which the R / W information 303 of the previously selected request packet 300 is a write request is searched. In the example shown in FIG. 14, the set (1) of the write request request packet 1202_0 stored in the input buffer 205_0, the read request request packet 1202_1 stored in the input buffer 205_1, and the input buffer 205_0. The write request request packet 1202_0 and the set (2) of the write request request packet 1202_n stored in the input buffer 205_n are searched.

  Subsequently, when a request packet 300 selected later is a read request request packet in the group of retrieved request packets 300, a write request previously selected in the data portion 305 of the read request request packet. The write data set in the data portion 305 of the request packet 300 is set, and “1 (R / W request cancel)” is set in the cancel flag 301 of the read request request packet. In the example shown in FIG. 4, “data I” set in the data part 305 of the write request request packet 1202_0 is set in the data part 305 of the read request request packet 1202_1, and “cancel” 301 is set in the cancel flag 301 of the read request request packet 1202_1. 1 "is set.

  In addition, when a request packet 300 selected later is a write request request packet in the set of searched request packets 300, the cancel flag 301 of the write request request packet 300 selected first is set to “1 ( R / W request cancellation) ”is set. In the example shown in FIG. 4, the write request request packet 1202_n stored in the input buffer 205_n is selected after the write request request packet 1202_0 stored in the input buffer 205_0. “1” is set in the cancel flag 301 of the request packet 1202_0.

  When the address comparison / R / W confirmation unit 1201 completes the comparison process, the request packet 300 is transmitted to the result determination unit 1003 shown in FIG.

  The request packet 300 transmitted to the result determination unit 1003 is acquired by the determination units 1401_0, 1401_1,..., 1401_n illustrated in FIG. 13 and further transmitted to the corresponding input registers 206_0, 206_1,.

  In the input registers 206_0, 206_1,..., 206_n, cancel processing of the request packet 300 in which “1 (R / W request cancel)” is set in the cancel flag 301 is executed.

  As described above, in the present embodiment, not only request packets in which access to the shared memory is duplicated between the access buffer and the input buffer, but also request packets that can be omitted between a plurality of input buffers are canceled. Furthermore, high-speed and efficient processing can be realized.

  Here, in the above description, an example has been described in which the round robin method is applied in the arbitration unit, and the request packets stored in the plurality of input registers are selected one by one in the order of numbers. For example, a request packet stored in an input buffer corresponding to a processor having a large processing load may be preferentially selected.

  In the above description, an example in which the request packet stored in the input buffer is canceled by the input register has been described. However, the memory access control device of the present invention cancels the request packet without checking the cancel flag in the input register. May be performed by an access register. However, by canceling the request packet stored in the input buffer using the input register, not only access to the shared memory but also arbitration processing in the arbitration unit can be omitted.

  Hereinafter, various embodiments of the present invention will be additionally described.

(Appendix 1)
In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer, the search unit stores the same address in the access buffer. The data to be written to the shared memory by the write request request packet is taken out from the access buffer, sent to the processor that issued the read request request packet of the same address among the plurality of processors, and the read request of the same address A memory access control device comprising a preceding processing unit for canceling a request packet.

(Appendix 2)
In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether or not a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer, the search unit stores the same address in the access buffer. A memory access control device comprising: a preceding processing unit that cancels a write request request packet.

(Appendix 3)
In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
The request packet stored in the input buffer across the plurality of input buffers is searched, and the same address as that of the read request request packet stored in any one of the plurality of input buffers is obtained. A search unit for detecting whether or not there is a write request request packet selected prior to the read request request packet by the arbitrating unit;
The search unit has the same address as the read request request packet stored in any one of the plurality of input buffers, and is selected by the arbitration unit before the read request request packet. When it is detected that a write request request packet exists, the data written to the shared memory by the write request request packet of the same address is taken out of the input buffer, and the same address of the plurality of processors And a preceding processing unit that cancels the read request request packet at the same address, and sends the read request request packet to the processor that issued the read request request packet.

(Appendix 4)
In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
The request packet stored in the input buffer across the plurality of input buffers is searched, and the same address as that of the write request request packet stored in any one of the plurality of input buffers is obtained. A search unit for detecting whether or not there is a write request request packet selected before the write request request packet by the arbitration unit;
The search unit has the same address as the write request request packet stored in any one of the plurality of input buffers, and is selected by the arbitration unit before the write request request packet. A memory access control apparatus comprising: a preceding processing unit that cancels a second write request request packet when it is detected that a second write request request packet exists.

(Appendix 5)
A request packet issued from each of a plurality of processors and requesting access to a shared memory shared by the plurality of processors, including a distinction between a write request and a read request and an address of the shared memory, Multiple input buffers to accumulate for each,
An access buffer for accumulating request packets in the order of access to the shared memory;
A memory in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in the input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer An access control method,
A search step of searching the access buffer and detecting whether or not a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When it is detected by the search step that a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer, the same address in the access buffer is stored. The data to be written to the shared memory by the write request request packet is taken out from the access buffer, sent to the processor that issued the read request request packet of the same address among the plurality of processors, and the read request of the same address A memory access control method comprising: an execution processing step for canceling a request packet.

(Appendix 6)
A request packet issued from each of a plurality of processors and requesting access to a shared memory shared by the plurality of processors, including a distinction between a write request and a read request and an address of the shared memory, Multiple input buffers to accumulate for each,
An access buffer for accumulating request packets in the order of access to the shared memory;
A memory in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in the input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer An access control method,
A search step of searching the access buffer and detecting whether or not a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer;
When it is detected by the search step that a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer, the same address in the access buffer is stored. A memory access control method comprising: an execution processing step for canceling a write request request packet.

(Appendix 7)
A request packet issued from each of a plurality of processors and requesting access to a shared memory shared by the plurality of processors, including a distinction between a write request and a read request and an address of the shared memory, Multiple input buffers to accumulate for each,
An access buffer for accumulating request packets in the order of access to the shared memory;
A memory in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in the input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer An access control method,
The request packet stored in the input buffer across the plurality of input buffers is searched, and the same address as that of the read request request packet stored in any one of the plurality of input buffers is obtained. A search step for detecting whether or not there is a write request request packet selected prior to the read request request packet by the arbitration unit;
The detection step has the same address as the read request request packet stored in any one of the plurality of input buffers, and is selected before the read request request packet by the arbitration unit. When it is detected that a write request request packet exists, the data written to the shared memory by the write request request packet of the same address is taken out of the input buffer, and the same address of the plurality of processors A memory access control method comprising: an execution processing step of canceling the read request request packet of the same address while sending the read request request packet to the processor that issued the read request packet.

(Appendix 8)
A request packet issued from each of a plurality of processors and requesting access to a shared memory shared by the plurality of processors, including a distinction between a write request and a read request and an address of the shared memory, Multiple input buffers to accumulate for each,
An access buffer for accumulating request packets in the order of access to the shared memory;
A memory in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in the input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer An access control method,
The request packet stored in the input buffer across the plurality of input buffers is searched, and the same address as that of the write request request packet stored in any one of the plurality of input buffers is obtained. A search step for detecting whether or not there is a write request request packet selected prior to the write request request packet by the arbitration unit;
The detection step has the same address as the write request request packet stored in any one of the plurality of input buffers, and is selected by the arbitration unit before the write request request packet. A memory access control method comprising: an execution processing step of canceling the second write request request packet when it is detected that the second write request request packet exists.

1 is a schematic configuration diagram of a parallel processor system having a 1: n connection configuration. FIG. 1 is a schematic configuration diagram of a parallel processor system to which an embodiment of the present invention is applied. It is a conceptual block diagram of a request packet. It is a functional block diagram of a search request part. It is a functional block diagram of a result judgment part. It is a functional block diagram of a comparison. It is a flowchart figure which shows the flow of a series of processes which cancel a request packet. It is a conceptual diagram which shows the flow of the request packet until a read request request packet is canceled. It is a conceptual diagram which shows the flow of the request packet until a write request request packet is canceled. It is a block diagram of the buffer search control part in 2nd Embodiment of this invention. It is a functional block diagram of the search request | requirement part in 2nd Embodiment of this invention. It is a functional block diagram of the comparison part in 2nd Embodiment of this invention. It is a functional block diagram of the determination part in 2nd Embodiment of this invention. It is a figure which shows the flow of a process in an address comparison and R / W confirmation part.

Explanation of symbols

200 parallel processor system 201 shared memory device 202_0, 202_1,..., 202_n processor 204_0, 204_1,. , 222_1,..., 222_XX storage buffer 223 access register 224 cache memory 230, 1001 buffer search control unit 234, 1004 address comparison unit 240 shared memory 300 request packet 401, 1101 search request unit 501, 1003 result determination unit 601_0, 601_1,. , 601_XX, 1004_0, 1004_1,..., 1004_XX comparison unit

Claims (4)

In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer, the search unit stores the same address in the access buffer. The data to be written to the shared memory by the write request request packet is taken out from the access buffer, sent to the processor that issued the read request request packet of the same address among the plurality of processors, and the read request of the same address A memory access control device comprising a preceding processing unit for canceling a request packet. In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
A search unit that searches the access buffer and detects whether or not a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer;
When the search unit detects that a write request request packet having the same address as the write request request packet existing in the input buffer exists in the access buffer, the search unit stores the same address in the access buffer. A memory access control device comprising: a preceding processing unit that cancels a write request request packet. In a memory access control device that controls access to a shared memory shared by a plurality of processors,
A request packet issued from each of the plurality of processors and requesting access to the shared memory, including a distinction between a write request and a read request, and an address of the shared memory is stored for each of the plurality of processors. Multiple input buffers,
An access buffer for accumulating request packets in the order of access to the shared memory;
An arbitration unit that sequentially selects the request packets stored in the input buffer according to a predetermined arbitration rule, and moves the selected request packets from the input buffer to the access buffer;
The request packet stored in the input buffer across the plurality of input buffers is searched, and the same address as that of the read request request packet stored in any one of the plurality of input buffers is obtained. A search unit for detecting whether or not there is a write request request packet selected prior to the read request request packet by the arbitrating unit;
The search unit has the same address as the read request request packet stored in any one of the plurality of input buffers, and is selected by the arbitration unit before the read request request packet. When it is detected that a write request request packet exists, the data written to the shared memory by the write request request packet of the same address is taken out of the input buffer, and the same address of the plurality of processors And a preceding processing unit that cancels the read request request packet at the same address, and sends the read request request packet to the processor that issued the read request request packet. A request packet issued from each of a plurality of processors and requesting access to a shared memory shared by the plurality of processors, including a distinction between a write request and a read request and an address of the shared memory, Multiple input buffers to accumulate for each,
An access buffer for accumulating request packets in the order of access to the shared memory;
A memory in a memory access control device comprising: an arbitration unit that sequentially selects request packets stored in the input buffer according to a predetermined arbitration rule and moves the selected request packets from the input buffer to the access buffer An access control method,
A search step of searching the access buffer and detecting whether or not a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer;
When it is detected by the search step that a write request request packet having the same address as the read request request packet existing in the input buffer exists in the access buffer, the same address in the access buffer is stored. The data to be written to the shared memory by the write request request packet is taken out from the access buffer, sent to the processor that issued the read request request packet of the same address among the plurality of processors, and the read request of the same address A memory access control method comprising: an execution processing step for canceling a request packet.

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