JPH059988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a signal readout circuit for a solid-state imaging device.

[Prior art]

FIG. 1 is a diagram showing the principle of a conventional CCD type solid-state imaging device. A photosensitive section 9 consisting of photodiodes 2 arranged in a matrix, and a vertical CCD 11 for reading out optical signals accumulated in the photodiodes.
It consists of a 1N and horizontal CCD 3 and an output AMP 4 that amplifies and outputs the transferred signal.

FIG. 2 is a circuit example of the output AMP4. 30 is a small capacitor Co that converts the signal charge amount Q _s transferred by the horizontal CCD 3 into a voltage amount, and 31 is a capacitor
Signal voltage generated between Co in proportion to signal charge Q _s
32 is a reset MOS FET for removing _the signal charge Q _S in the capacitor Co to the outside.

In the device having the structure shown in FIGS. 1 and 2, signals are read out in the following manner. That is, first, the signal charge accumulated in the photodiode 2 during one frame period is transferred to the CCD 11 in the vertical direction during the vertical retrace period.
Move within 1N. The vertical CCD transfers one line per horizontal retrace period, and the signal charge is transferred to the horizontal direction.
Transfer to CCD3 sequentially. horizontal retrace period
The signal charge transferred to the CCD is sequentially transferred into the capacitor Co by applying a clock pulse to the horizontal CCD during one subsequent horizontal period. l
The signal charge Q ^(l) _s transferred to the capacitor Co by the second clock pulse generates a voltage V ^(l) ₀ across the capacitor Co, and a signal pulse with a voltage amplitude V ( ^l) ₀ is generated from the source follower output terminal 33 (Fig. 3, 4l). Output. After that, the signal charge Q ^(l) _s is removed to the outside through the reset MOS type FET. Further, at the next l+1th clock pulse, the next signal charge Q ^(l+1) _s is transferred to the capacitor Co again, and a signal pulse ^{(l+1) of FIG. 3 with voltage amplitude V (l+1)} ₀ is output. By repeating the same operation, the signal is sequentially output as a signal pulse train (c) in FIG. 3 having a voltage amplitude V ^(l) ₀ proportional to the signal charge Q ^(l) _s .

FIG. 4 is an explanatory diagram of the frequency distribution of the output signal pulse train of FIG. 3c. In other words, a train of signal charges that modulates the amplitude of the output signal pulse train...Q ^(l+1) _s (t _l-1 ), Q ^(l+1
) _s
The frequency distribution of (t _l ), Q ^(l+1) _s (t _l+1 ), ... is shown in Figure 4a.
When the frequency distribution of the output signal pulse train of FIG. 3c is as shown in FIG. 4b, the frequency distribution of the output signal pulse train of FIG. 3c becomes as shown in FIG. In the figure, 50 is the baseband component, which has a frequency characteristic sinπτ/π (where τ=
Fig. 4a shows the frequency distribution obtained by multiplying the modulation signal of Fig. 4a by the pulse width). Further, 51 is a fundamental wave component, which consists of a carrier wave having the same frequency r as that of the reset pulse and its sidebands. Below, 5m is the m-th harmonic component of Fig. 3c, which consists of a carrier wave with frequency r times m and its sidebands.

To read the signal components from the output signal pulse train in Figure 3c, there are two methods: extracting the baseband component 50 of the frequency distribution in Figure 4b using an LPF, or extracting and detecting the fundamental wave component or harmonic component using a BPF. and so on.

By the way, in solid-state imaging devices, the first stage transistor of the output AMP (Fig. 2, 31) is generally a MOS type FET.
Consists of. Furthermore, the voltage-current conversion parameter gm of an IC-based MOS FET is as small as approximately 1 mV. Therefore, the output impedance r of the source and follower, which is determined by the reciprocal of gm, becomes large, reaching approximately 1KΩ. Therefore, even if it is a source follower, the output impedance r and external resistance R (Fig. 2, 35)
The attenuation of the output signal level caused by the voltage division effect R/R+r (1) cannot be ignored. In fact, for example, even if the solid-state imaging device output is received by a resistor R=2KΩ, the signal level is attenuated by about 2/3. Therefore, the signal level relative to external circuit noise is reduced, and the SN ratio of the read signal is degraded.

According to calculation formula (1), the amount of attenuation of the signal level can be suppressed to 10% or less by setting the external resistance R to a large value, for example, 10-odd KΩ. However, in an actual circuit, as shown in FIG. 2, there is a parasitic capacitance C of several pF due to wiring, etc., so if the resistance R is increased, the frequency characteristics of the output signal will be significantly degraded. Also, the gm of MOS type FET31
((Therefore, output impedance r) decreases (r increases) as its bias current decreases, so
A large power supply voltage is required to ensure a constant bias current. The former effect of frequency characteristic deterioration is particularly significant when a signal component is extracted from the fundamental wave component or harmonic component of the output signal pulse train.

[Purpose of the invention]

An object of the present invention is to provide the solid-state imaging device shown in FIG. 1 without attenuating the output signal level.
The present invention also relates to a signal reading circuit that can read signals without using a large power supply voltage.

[Summary of the invention]

In order to achieve the above object, the present invention provides an inductance L in parallel to the parasitic capacitance C instead of the external resistance R.
is inserted, and the resonance point o of these capacitance C and inductance L is set within the fundamental wave component band or harmonic component band of the output signal pulse train of the output AMP used for signal extraction.

[Embodiments of the invention]

FIG. 5 shows an embodiment of the present invention, which is a signal readout circuit for extracting a signal from the fundamental wave component or harmonic component of the output signal pulse train. In FIG. 5, 36 is an inductance L inserted in place of the external resistor 35 in FIG.
4) and the inductance L so that the resonance point o= ¹ ₂ 〓×1/√ (2) is within the fundamental wave component band or harmonic component band to be used. For example, a clock frequency c =
When driving the solid-state imaging device at 7.16MHz and extracting a signal from the fundamental wave component, the inductance L is set so that the resonance frequency o is approximately 7MHz.

When the inductance L is set as above, the load impedance Z of the source follower MOS FET31 becomes Z(f)=j×2π×L/1−(2π) ^{2 2} ×LC (3), and the resonant frequency _{is 0.} The value |Z| in the neighborhood is MOS
Since the value is sufficiently larger than the output impedance r of the type FET 31, the voltage dividing effect on the output voltage due to the resistor r and |Z| can be made very small. Further, the impedance to direct current (OHHz) that determines the bias current of the MOS FET 31 is Z(o)0 (4) from equation (3), and no voltage is generated between the impedances Z due to the bias current. Therefore, the required bias current can be secured even without a large power supply voltage.

FIG. 6 shows another embodiment of the present invention, which is a signal readout circuit in which the resonance Q value determined by equation (3) is adjusted. In other words, FIG. 6 shows an even larger resistance in parallel with the parasitic capacitance 34 and inductance 36 in FIG.
R' (Fig. 6, 37) is inserted. As is clear from equation (3), the external impedance Z in FIG. 5 exhibits a very sharp frequency characteristic that diverges from Z(fo) to ∞ at the point of resonance frequency o. Resistor 3 in Figure 6
7 was inserted to reduce the Q value indicating sharpness and smooth the frequency characteristics. The external impedance Z' in FIG. 6 can be expressed by the following equation.

Z′(f)=j×2πL/1−(2π) ^2
2 CL + j × 2πL/R' (5) Figure 7 shows another embodiment of the present invention, in which an inductance of 36
In this circuit, a resistor R'' (Fig. 7, 38) is inserted in series with the circuit. Impedance Z″ can be expressed by the following formula.

Z″(f)=R″+j×2πL/1−(2π
) ^{2 2} LC+j×2πCR''(6) However, the circuit shown in FIG. 7 requires a large power supply voltage to ensure the bias current of the MOS FET 31, depending on the size of the resistor R''.

The embodiments shown in FIGS. 5 and 6 have low impedance in the low frequency region, and cannot be applied to a signal readout method that extracts a signal from the baseband component of an output signal pulse train. However, in the embodiment shown in FIG. 7, the impedance Z(o)=R'' is obtained even in the low frequency region, for example =OHZ, so the resonance frequency o=1/2π1/√ in equation (6) is set to the baseband. Alternatively, by setting it within the fundamental wave component band, it can also be applied to a signal readout method that extracts a signal from the baseband component.

In addition, in the embodiments shown in FIGS. 5 to 7, an inductance 36 and resistors 37, 38 inserted outside
It is desirable to make it variable in order to adjust the resonance frequency and Q value.

〔Effect of the invention〕

According to the present invention, in a solid-state imaging device having an output AMP of the type that amplifies the power or voltage of the signal voltage appearing between the input end capacitance Co of the CCD type equal output AMP, without using a large power supply voltage,
It is possible to obtain a signal with a high signal-to-noise ratio without deterioration of frequency characteristics due to the parasitic capacitance C of the output line and external resistance R, or attenuation of the output signal level due to voltage division due to the output resistance r of the AMP and external resistance R. can.

In addition, the source follower MOS type FET31 is
This generates thermal noise proportional to the reciprocal of the gm (which increases with the bias current), but in the embodiments shown in Figures 5 and 6, the bias current can be arbitrarily selected without increasing the power supply voltage. The thermal noise itself can be reduced, and the signal-to-noise ratio can be further increased.

The above has been explained using the example of the output AMP circuit shown in FIG. 5, but the output AMP circuit, such as the output AMP circuit shown in FIG.
CCD type solid-state imaging device or MOS as shown in Figure 9
Solid-state imaging devices that combine type and CCD type
It can also be used to read signals from CCD line sensors, CCD delay lines, etc.

[Brief explanation of the drawing]

Figure 1 shows the principle of a conventional CCD solid-state imaging device.
Figure 2 is an example of the output AMP circuit, Figures 3 and 4 are the output signal waveform and its frequency distribution, Figures 5 to 7 are examples of the signal readout circuit according to the present invention, and Figure 8 is other than Figure 2. FIG. 9 is a principle diagram of an example of a solid-state imaging device other than a CCD type to which the present invention can be applied.

Claims (1)

[Claims] 1. The signal charge Q _s sent in a pulse is
AMP input capacitance composed of MOS type FET
AMP that amplifies the power or voltage of the signal voltage that is accumulated in C ₀ and appears between the capacitor Co and outputs the signal voltage.
A solid-state device having a circuit and an output AMP circuit for further amplifying the output of the AMP circuit,
The load impedance of the above output AMP circuit is
A solid state comprising an inductance L and a power supply connected in series with the inductance L for matching the voltage applied to the base of the AMP circuit composed of the MOS FET. Device signal readout circuit. 2. In the signal readout circuit for a solid-state device according to claim 1, the resonant frequency o determined by the inductance L and the parasitic capacitance C of the output line of the solid-state device is set to the output output from the output AMP circuit. A signal readout circuit for a solid-state device, characterized in that it is set within a harmonic region of m times a carrier frequency r used for extracting a signal from a signal.