JPH0595560A - Digital acc circuit - Google Patents

Abstract

PURPOSE:To enable amplitude control to speedily respond to the fluctuation of an inputted digital carrier chrominance signal. CONSTITUTION:This circuit is constituted of a burst amplitude detector 1, switch 2 to switch a burst amplitude value (c) and a digital carrier chrominace signal (a), multiplier 3 to control an amplification factor according to a control signal (i), subtracter 4 to obtain a differential signal (h) between a reference value (g) and an output (f) of the multiplier 3, and loop filter 5 to obtain the control signal (i) of the multiplier 3 from the differential signal (h). And an arithmetic loop constituted of the multiplier 3, subtracter 4 and loop filter 5 is operated for a period shown by a switching signal (d) according to internal logic (j) so as to generate the control signal (i). Thus, the number of times of the operation for generating the control signal (i) is increased, and high-speed amplitude control is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital ACC circuit in a digital color television receiver.

[0002]

2. Description of the Related Art In recent years, the trend toward digitalization in signal processing of televisions has been increasing with the improvement in image quality and multifunction of television receivers, and digital adjustment of the color saturation of carrier color signals has been performed. The ACC circuit is regarded as important.

A conventional digital ACC circuit will be described below with reference to FIGS. 3 and 4. FIG. 3 shows the configuration of a conventional digital ACC circuit. In FIG. 3, 2
0 is a multiplier, which is used to multiply the digital carrier color signal a. Reference numeral 21 denotes a burst amplitude detector, which detects the amplitude of the burst signal from the digital carrier color signal a and outputs the burst amplitude value d. A subtractor 22 subtracts the burst amplitude value d from the reference value e and outputs a difference signal f. A loop filter 23 creates a control signal g to be input to the multiplier 20 from the difference signal f.

Digital ACC constructed as described above
The operation of the circuit will be described below with reference to FIG. Then, the digital carrier color signal a is input to the multiplier 20,
The multiplication output b is input to the burst amplitude detector 21 during the period indicated by the burst flag c to detect the burst amplitude and output the burst amplitude value d, and the subtractor 22 changes the burst amplitude value d from the reference value e. Subtracting, outputting the difference signal f, the difference signal f through the loop filter 23,
A calculation is performed to correct the control signal g so that the difference signal f decreases, and the calculated signal is input as a new control signal g for the multiplier 20. Then, by repeating this operation every time the burst flag c is input, the burst amplitude value d is brought closer to the reference value e.

The state of changes in the differential signal f and the control signal g in the conventional digital ACC circuit will be described below with reference to FIGS. First, it is assumed that the difference signal f and the control signal g are in a converged state at time zero. Then, it is assumed that the burst amplitude of the input digital carrier color signal a changes at time ts. The difference signal f and the control signal g are recognized as a change in burst amplitude, and their values are changed. Then, the value converges with the lapse of time to reach the target color saturation.

[0006]

However, in the above configuration, one cycle of the digital carrier color signal, that is,
The control signal for controlling the multiplication factor of the multiplier can be calculated only once for one cycle of the burst flag.
As shown in (d) to (f), when the burst amplitude of the digital carrier color signal suddenly changes, the convergence period of the value of the control signal, that is, the period until the difference signal from the subtractor converges to zero becomes long. , The response of the ACC control was delayed, which was a problem.

The present invention has been made in consideration of the above-mentioned problems. By making it possible to calculate the control signal of the multiplier a plurality of times for one cycle of the burst flag, high-speed responsiveness is achieved. A digital ACC circuit having the same is provided.

[0008]

In order to solve the above-mentioned problems, a digital ACC circuit of the present invention comprises a burst amplitude detector and a switch capable of selecting an input of a burst amplitude value and a digital carrier color signal by a switching signal. ,
It is composed of a multiplier that controls the multiplication factor by a control signal, a subtractor that obtains a difference signal between a reference value and the output of the multiplier, and a loop filter that creates a control signal of the multiplier from the difference signal.

[0009]

According to the present invention, when the burst amplitude value is directly detected from the digital carrier color signal on the input side and the control signal of the multiplier is obtained by the above-mentioned structure, the switch is performed by the switching signal indicating the blank period of the digital carrier color signal. Set the input of to the burst amplitude value side, the multiplier, the subtractor,
By rotating the operation loop configured by the loop filter by the internal clock, it is possible to increase the number of operations for creating the control signal of the multiplier.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital ACC according to an embodiment of the present invention will be described below.
The circuit will be described with reference to FIGS. 1, 2, 4, and 5.

FIG. 1 shows a digital ACC circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a burst amplitude detector, which outputs a value obtained by averaging the amplitude values of the burst signals of the digital carrier color signal a during the period of the burst flag b as a burst amplitude value c. Reference numeral 2 denotes a switch for switching between the digital carrier color signal a and the burst amplitude value c, which outputs the burst amplitude value c when the switching signal d is at high level and outputs the digital carrier color signal a when it is at low level. A multiplier 3 multiplies the output signal e from the switch 2 and outputs a multiplication output f. A subtracter 4 subtracts the multiplication output f from the reference value g and outputs the difference signal h. A loop filter 5 outputs a control signal i for the multiplier 3.

Digital ACC constructed as described above
The operation of the circuit will be described below with reference to FIGS. 1 and 2.

FIG. 2 shows the timing relationship between the digital carrier color signal a, the burst flag b and the switching signal d. First, the burst flag b is set to High level in the burst signal portion of the digital carrier color signal a. The switching signal d is the digital carrier color signal a.
High level during the blank period.

The operation of creating a control signal will be described below with reference to FIG. First, the switching signal d becomes High level, and the switch 2 inputs the burst amplitude value c held by the burst amplitude detector 1 to the multiplier 3 as the switch output signal e. The multiplier 3 multiplies the value of the control signal i held by the loop filter 5 by the switch output signal e, and outputs a multiplication output f. The subtractor 4 is
The reference value g and the multiplication output f are input, the multiplication output f is subtracted from the reference value g, and the difference output h is output. The difference output h is
It is input to the loop filter 5 and the control signal i is created in synchronization with the internal clock j. Then, again, with the newly created control signal i, the switch output e is multiplied by the multiplier 3, the multiplication output f as a new multiplication result is output, and input to the multiplier 4 to obtain the reference value g. The difference signal h is output. Then, the difference signal h is input to the loop filter 5, synchronized with the internal clock j, and a new control signal i is added.
To create. This calculation is repeatedly performed in synchronization with the internal clock j while the switching signal d is at the high level. During this calculation, the burst amplitude detector 1 updates the burst amplitude value c with the burst flag b at the fall of the burst flag b. Therefore, until the update, the previous burst amplitude value c is calculated,
After the update, calculation is performed on the updated burst amplitude value c. Then, in this calculation, the switching signal d is L
It continues until it reaches the ow level. Then, once again, when the switching signal d becomes High level, the calculation is performed from the continuation thereof, and the calculation is performed until the next burst amplitude value c is updated. Therefore, when the burst amplitude value c is updated once, the number of times corresponding to the number of cycles of the internal clock j in the high level period of the switching signal d is calculated for one cycle of the burst flag b. Become.
Here, when the burst amplitude value c is updated, the control signal i is not cleared, and the value of the control signal i before the update is continuously used even after the update.

4 and 5, the convergence state of the differential signal and the control signal of the conventional digital ACC circuit, and as an example in the present embodiment, 5 times per burst flag cycle
The convergence states of the differential signal and the control signal when the calculation is performed twice are compared. As an example of the present embodiment, FIG. 5 is a diagram showing a state of convergence of the differential signal and the control signal when the calculation is performed five times in one cycle of the burst flag. Figure 4
Compared with the response of the conventional digital ACC circuit of (d) to (f), in FIGS. 5 (a) to (c), the same burst amplitude change converges in ⅕ time. .. This indicates that the convergence time of the value decreases in inverse proportion to the increase of the arithmetic circuit.

As described above, according to this embodiment, the burst amplitude detector, the switch for switching the burst amplitude value and the digital carrier color signal, the multiplier for controlling the multiplication factor by the control signal, the reference value and the multiplier. It is possible to increase the number of times of calculation of the control signal by using a subtracter that obtains a difference signal from the output and a loop filter that obtains the control signal of the multiplier from the difference signal.

[0017]

As described above, according to the present invention, the burst amplitude detector, the switch for switching the burst amplitude value and the digital carrier color signal, the multiplier for controlling the multiplication factor by the control signal, the reference value and the multiplier. It is possible to shorten the convergence period of the control signal value by increasing the number of times the control signal is calculated by using a subtracter that obtains the difference signal from the output and a loop filter that obtains the control signal of the multiplier from the difference signal. In addition, it is possible to respond at a high speed even to an amplitude variation of the carrier color signal, particularly a rapid amplitude variation such as a channel change.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital ACC circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of an input signal in the embodiment.

FIG. 3 is a block diagram showing a conventional digital ACC circuit.

FIG. 4 is a diagram showing a state of convergence of a differential signal and a control signal in a conventional digital ACC circuit.

FIG. 5 is a diagram showing a state of convergence of a differential signal and a control signal when an operation is performed five times in one cycle of a burst flag as an example in the embodiment.

[Explanation of symbols]

 1 Burst amplitude detector 2 Switch 3 Multiplier 4 Subtractor 5 Loop filter

Claims (1)

[Claims] 1. From the input digital carrier color signal,
A burst amplitude detector for detecting a burst amplitude and an output signal of the burst amplitude detector as a first input, the input digital carrier color signal as a second input, and either one of the inputs is output by a switching signal. A switch, a multiplier for inputting the output signal and the control signal of the switch and generating a multiplied digital carrier color signal output, and a reference value for subtracting the output signal of the multiplier from the output signal of the multiplier and the subtractor of the subtractor. A digital ACC circuit having a loop filter connected to an output terminal and outputting the control signal for setting a multiplication factor of the multiplier.