JPH0595120A - Manufacture of nonvolatile semiconductor storage element - Google Patents
Manufacture of nonvolatile semiconductor storage elementInfo
- Publication number
- JPH0595120A JPH0595120A JP28059491A JP28059491A JPH0595120A JP H0595120 A JPH0595120 A JP H0595120A JP 28059491 A JP28059491 A JP 28059491A JP 28059491 A JP28059491 A JP 28059491A JP H0595120 A JPH0595120 A JP H0595120A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sin film
- sih2cl2
- memory
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、異種絶縁膜界面に自然
発生的に生じる電荷捕獲部（以下トラップという）を利
用したＭＯＮＯＳ（Metal-Oxide-Nitride-Oxide-Semico
nductor ）型やＭＮＯＳ（Metal-Nitride-Oxide-Semico
nductor)型不揮発性記憶素子の製造方法、特にそのシリ
コン窒化膜（以下SiN 膜) の形成方法に関するものであ
る。BACKGROUND OF THE INVENTION The present invention relates to a MONOS (Metal-Oxide-Nitride-Oxide-Semico) which utilizes a charge trap portion (hereinafter referred to as a trap) that spontaneously occurs at the interface of different kinds of insulating films.
nductor) type and MNOS (Metal-Nitride-Oxide-Semico
and a method for forming a silicon nitride film (hereinafter referred to as SiN film).
【０００２】[0002]
【従来の技術】ＭＯＮＯＳ型不揮発性記憶素子は、ＭＮ
ＯＳ（Metal-Nitride-Oxide-Semiconductor ）型不揮発
性記憶素子を改良し薄膜化を図ったものであり、Si基板
上に電荷がトンネル可能なシリコン酸化膜（以下トンネ
ル酸化膜という）を積層し、この SiN膜を熱酸化し、Si
N 膜上に SiO2 膜（以下トップ酸化膜という）を形成
し、SiN 膜中およびSiN 膜とトップ酸化膜との界面に高
密度のトラップを形成させることによりメモリ機能を持
つ素子である。2. Description of the Related Art A MONOS type non-volatile memory element is an MN
This is a thin film of an OS (Metal-Nitride-Oxide-Semiconductor) type non-volatile memory element that is improved by stacking a silicon oxide film (hereinafter referred to as a tunnel oxide film) capable of tunneling charges on a Si substrate. This SiN film is thermally oxidized to form Si
A device having a memory function is formed by forming a SiO 2 film (hereinafter referred to as a top oxide film) on the N film and forming high-density traps in the SiN film and at the interface between the SiN film and the top oxide film.
【０００３】ここでＭＯＮＯＳ型不揮発性記憶素子の製
造に際し、SiN 膜は SiH2Cl2( ジクロルシラン) と NH3
を原料ガスとしてその流量比が 1:5〜15で、かつ650 ℃
〜800 ℃の温度範囲で LPCVD法によって形成されてい
て、SiN 膜中にもトラップは形成されるが、主に前述の
ようにSiN 膜とトップ酸化膜との界面に発生した多数の
トラップによってメモリ機能を果たしている。Here, in manufacturing a MONOS type nonvolatile memory element, the SiN film is composed of SiH 2 Cl 2 (dichlorosilane) and NH 3.
As a raw material gas with a flow rate ratio of 1: 5 to 15 and 650 ℃
It is formed by the LPCVD method in the temperature range of ~ 800 ° C, and traps are also formed in the SiN film. However, as described above, many traps are generated at the interface between the SiN film and the top oxide film. Plays a function.
【０００４】[0004]
【発明が解決しようとする課題】一方、トラップへの電
荷の注入、放出によってメモリ素子のしきい値電圧が変
化するが、このしきい値電圧の変化量が大きいほどメモ
リの "１", "０" 状態のしきい値電圧差△Vthが大きく
なるため、読出しの高速化、およびプログラムの高速化
が図れるが、この高速化が当業界で望まれている。本発
明は、前述の現状に鑑み、しきい値電圧差△ Vthを大き
くし、すなわちメモリウィンドウを大きくし、メモリを
高速化できるような半導体不揮発性記憶素子の製造方法
を提供するためになされたものである。On the other hand, the threshold voltage of the memory element changes due to the injection and discharge of charges into the trap. The larger the amount of change in the threshold voltage, the more "1", " Since the threshold voltage difference .DELTA.Vth in the 0 "state becomes large, the reading speed and the programming speed can be increased. However, this increase in speed is desired in the industry. The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor nonvolatile memory element capable of increasing the threshold voltage difference ΔVth, that is, increasing the memory window and speeding up the memory. It is a thing.
【０００５】[0005]
【課題を解決するための手段】本発明は、Si基板上に少
なくともシリコン酸化膜、シリコン窒化膜を積層してゲ
ート絶縁膜とした、不揮発性記憶素子の該シリコン窒化
膜をＬＰＣＶＤ法で形成するに際し、SiH2Cl2 ：NH3 ：
N2O ＝１：５〜１５：０．０５〜０．１のガス流量比
で、かつ６５０℃〜８００℃の温度範囲でシリコン窒化
膜を形成することを特徴とする半導体不揮発性記憶素子
の製造方法である。According to the present invention, at least a silicon oxide film and a silicon nitride film are laminated on a Si substrate to form a gate insulating film, and the silicon nitride film of a nonvolatile memory element is formed by an LPCVD method. In this case, SiH 2 Cl 2 : NH 3 :
N 2 O = 1: 5 to 15: 0.05 to 0.1 and a silicon nitride film is formed in a temperature range of 650 ° C. to 800 ° C. in a semiconductor nonvolatile memory element. It is a manufacturing method.
【０００６】[0006]
【作用】本発明の作用を以下に図１にしたがって説明す
る。ＭＯＮＯＳ型不揮発性記憶素子において、トンネル
酸化膜４の上部にSiN 膜３を積層するに際し、SiH2Cl2
とNH3 とN2O とを原料ガスとして流量比を１：５〜１
５：０．０５〜０．１の割合でチューブ内に供給する。
この結果、周知のとおり、 SiH2Cl2とNH3 との反応でSi
N 膜３が形成されるが、さらに同時にSiH2Cl2 とN2O と
の反応で、その内部にSiO2または SiOx ７が形成され
る。またN2O ガスが直接、SiN 膜を酸化してその内部に
SiO2または SiOx ７が形成される。The operation of the present invention will be described below with reference to FIG. In stacking the SiN film 3 on the tunnel oxide film 4 in the MONOS type nonvolatile memory element, SiH 2 Cl 2
And NH 3 and N 2 O as raw material gases with a flow rate ratio of 1: 5 to 1
5: Supply into the tube at a ratio of 0.05 to 0.1.
As a result, as is well known, SiH 2 Cl 2 and NH 3 react with each other to produce Si.
The N film 3 is formed, and at the same time, SiO 2 or SiO x 7 is formed in the inside by the reaction of SiH 2 Cl 2 and N 2 O. In addition, N 2 O gas directly oxidizes the SiN film and
SiO 2 or SiO x 7 is formed.
【０００７】そのようにして形成されたSiO2,SiOX がSi
N膜に内在し、その結果SiN とSiO2,SiOX との界面に高
密度にトラップ６”が発生する。したがって本発明によ
ると、SiN 膜とトップ酸化膜との界面にあるトラップ
６′に加えてSiN膜内にもトラップ６”が存在し、図3
に示す従来例に比べてトラップ密度が著しく増加してい
る。したがってこれらのトラップに電荷が注入、放出さ
れた場合のしきい値電圧差△ Vthは大きくなり、したが
ってメモリウィンドウが大きくなり、メモリの高速化が
達成できた。The SiO 2 and SiO X thus formed are Si
In the N film, as a result, a high density of traps 6 ″ is generated at the interface between SiN and SiO 2 , SiO X. Therefore, according to the present invention, the trap 6 ′ at the interface between the SiN film and the top oxide film is formed. In addition, there are traps 6 "in the SiN film.
The trap density is remarkably increased as compared with the conventional example shown in FIG. Therefore, the threshold voltage difference ΔVth when charges are injected into and discharged from these traps becomes large, and therefore the memory window becomes large, and the speeding up of the memory can be achieved.
【０００８】[0008]
【実施例】本発明の実施例を以下に説明する。ウエハが
配置されたチューブ中に SiH2Cl2 : NH3 : N2O＝１：５
〜１５：０．０５〜０．１のガス流量比でかつ６５０℃
〜８００℃の温度範囲で SiN膜を形成した。 一方、Si
H2Cl2 : NH3 ＝１：１０のガス流量比で７００℃でSiN
膜を形成し比較例とした。EXAMPLES Examples of the present invention will be described below. SiH 2 Cl 2 : NH 3 : N 2 O = 1: 5 in the tube where the wafer is placed.
-15: 0.05-0.1 at a gas flow ratio of 650 ° C
A SiN film was formed in the temperature range of ~ 800 ° C. On the other hand, Si
SiN at 700 ° C with a gas flow rate ratio of H 2 Cl 2 : NH 3 = 1: 10
A film was formed as a comparative example.
【０００９】この実施例、比較例について、夫々ゲート
電圧 Vg を±9Vの範囲で走査してヒステリシス曲線を描
いた結果が図２である。比較例のメモリウィンドウ幅は
H1,実施例のメモリウィンドウ幅は H2 であり、実施例
のメモリウィンドウ幅の方が著しく大きくなっている。
この実施例から明らかなように、本発明によるとメモリ
ウィンドウ幅が従来より大きくなりメモリのプログラ
ム、および読出しの高速化に寄与することができる。FIG. 2 shows the results obtained by scanning the gate voltage Vg in the range of ± 9 V and drawing a hysteresis curve for each of the examples and comparative examples. The memory window width of the comparative example is
H 1, the memory window width of the embodiment is H 2 , and the memory window width of the embodiment is significantly larger.
As is apparent from this embodiment, according to the present invention, the memory window width becomes larger than the conventional one, and it is possible to contribute to speeding up the programming and reading of the memory.
【００１０】[0010]
【発明の効果】本発明によると、メモリウィンドウが大
きく、メモリを高速化できる不揮発性記憶素子を製造す
ることができる。According to the present invention, a nonvolatile memory element having a large memory window and capable of speeding up the memory can be manufactured.
【図１】本発明に係るＭＯＮＯＳ型不揮発性記憶素子の
断面模式図である。FIG. 1 is a schematic cross-sectional view of a MONOS type nonvolatile memory element according to the present invention.
【図２】Vgと Vthとの関係を示す特性図である。FIG. 2 is a characteristic diagram showing a relationship between Vg and Vth.
【図３】従来のＭＯＮＯＳ型不揮発性記憶素子の断面図
である。FIG. 3 is a cross-sectional view of a conventional MONOS type nonvolatile memory element.
１． ゲート電極 ２． SiO2膜（トップ酸化膜） ３． シリコン窒化膜（SiN 膜) ４． シリコン酸化膜（トンネル酸化膜） ５． Si基板 ６′６”． トラップ ７． SiO2 または SiOX ８． ソース・ドレイン拡散層1. Gate electrode 2. SiO 2 film (top oxide film) 3. Silicon nitride film (SiN film) 4. Silicon oxide film (tunnel oxide film) 5. Si substrate 6'6 ". Trap 7. SiO 2 or SiO X 8. Source / drain diffusion layer
Claims (1)
シリコン窒化膜を積層してゲート絶縁膜とした、不揮発
性記憶素子の該シリコン窒化膜をＬＰＣＶＤ法で形成す
るに際し、 SiH2Cl2 ：NH3 ：N2O ＝１：５〜１５：０．０５〜０．
１のガス流量比で、かつ６５０℃〜８００℃の温度範囲
でシリコン窒化膜を形成することを特徴とする半導体不
揮発性記憶素子の製造方法。1. At least a silicon oxide film on a Si substrate,
When forming the silicon nitride film of the nonvolatile memory element by laminating a silicon nitride film as a gate insulating film by the LPCVD method, SiH 2 Cl 2 : NH 3 : N 2 O = 1: 5 to 15: 0. 05-0.
A method of manufacturing a semiconductor nonvolatile memory element, comprising forming a silicon nitride film at a gas flow rate ratio of 1 and in a temperature range of 650 ° C. to 800 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28059491A JPH0595120A (en) | 1991-10-01 | 1991-10-01 | Manufacture of nonvolatile semiconductor storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28059491A JPH0595120A (en) | 1991-10-01 | 1991-10-01 | Manufacture of nonvolatile semiconductor storage element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0595120A true JPH0595120A (en) | 1993-04-16 |
Family
ID=17627211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28059491A Pending JPH0595120A (en) | 1991-10-01 | 1991-10-01 | Manufacture of nonvolatile semiconductor storage element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0595120A (en) |
-
1991
- 1991-10-01 JP JP28059491A patent/JPH0595120A/en active Pending
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