JPH0595077A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0595077A
JPH0595077A JP25376491A JP25376491A JPH0595077A JP H0595077 A JPH0595077 A JP H0595077A JP 25376491 A JP25376491 A JP 25376491A JP 25376491 A JP25376491 A JP 25376491A JP H0595077 A JPH0595077 A JP H0595077A
Authority
JP
Japan
Prior art keywords
die pad
resin
lead frame
package
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25376491A
Other languages
Japanese (ja)
Inventor
Yoshiaki Maehira
芳明 前平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25376491A priority Critical patent/JPH0595077A/en
Publication of JPH0595077A publication Critical patent/JPH0595077A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent disconnection of a bonding wire and enhance contact properties with resin by providing a sheet-shaped groove on the outer periphery of a die pad in a plastic package. CONSTITUTION:A die pad 26 is fixed in resin with package resin 12. Then, it is press-punched in the shape of a lead frame by a press method. An outer periphery section of the die pad is grooved based on a press method by designing a suitable type of the sheet-shaped groove. The depth of the groove is preferably 1/2 to 2/3 the thickness of the die pad while its required width is about 1mm. In this operation, it is preferred that the grooves be provided as many as possible. This construction makes it possible to relax shear stress during a temperature cycle, prevent disconnections in a bonding wire, enhance contact properties with resin and hence embody separation prevention.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置、特に、表
面実装型プラスチックパッケージのリードフレームのダ
イ・パッド部の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a die pad portion of a lead frame of a surface mount type plastic package.

【０００２】[0002]

【従来の技術】従来の半導体装置のリードフレームは、
図３に示したようにリードフレームに加工を施さないも
の、図４のようなダイ・パッド下にディンプルを設け樹
脂とリードフレームの密着性を向上させたもの、図５の
ようなダイ・パッドに十字状の貫通穴を空けパッケージ
樹脂とリ−ドフレームの密着を向上させるとともに樹脂
が吸湿して気化膨張したとき発生する応力を緩和させた
ものが主流であった。2. Description of the Related Art The lead frame of a conventional semiconductor device is
As shown in FIG. 3, the lead frame is not processed, as shown in FIG. 4, dimples are provided under the die pad to improve the adhesion between the resin and the lead frame, and as shown in FIG. The mainstream method is to provide a cross-shaped through hole to improve the adhesion between the package resin and the lead frame and to relieve the stress generated when the resin absorbs moisture and evaporates and expands.

【０００３】[0003]

【発明が解決しようとする課題】しかし、前述の従来技
術図３においては、リードフレームとパッケージ樹脂の
密着強度が低いため吸湿したパッケージがリフロー炉を
通るときその水分が蒸気になって樹脂にクラックが出来
てその後の信頼性が著しく低下するという問題を有して
いた。However, in the above-mentioned prior art FIG. 3, since the adhesion strength between the lead frame and the package resin is low, when the moisture-absorbed package passes through the reflow oven, its moisture becomes vapor and cracks in the resin. However, there was a problem in that the reliability was significantly reduced thereafter.

【０００４】こうした不具合を低減するため図４に示し
たディンプル及び図５に示した十字状のスリットが開発
された。これは、パッケージ樹脂とリードフレームの接
する面積を大きくしたことにより、密着性の向上を図っ
たものであるが、ディンプルの場合形状が大きすぎると
エッジ部分がトリガーとなってパッケージクラックを引
き起こす可能性があるので、各々のパッケージ毎に形状
設計が必要となり、イニシャルコストが高くなる。又十
字状のスリットは穴が貫通しているため通常のチップ接
着剤では穴を防いでしまう可能性があるため接着剤の粘
度を制御しなければならず、量産性に向かない。さらに
ダイパッド外周部の応力に対しては考慮されておらず、
温度サイクルの時のせん断応力でボンディングワイヤー
の断線を引き起こすという問題を有していた。In order to reduce these problems, the dimple shown in FIG. 4 and the cross-shaped slit shown in FIG. 5 have been developed. This is to improve the adhesiveness by increasing the contact area between the package resin and the lead frame, but in the case of dimples, if the shape is too large, the edge part may trigger and cause package cracks. Therefore, the shape design is required for each package, and the initial cost becomes high. Further, since the cross-shaped slit has a hole penetrating therethrough, there is a possibility that the ordinary chip adhesive may prevent the hole, and therefore the viscosity of the adhesive must be controlled, which is not suitable for mass production. Furthermore, it is not considered for the stress of the outer periphery of the die pad,
There is a problem in that the shearing stress during the temperature cycle causes the breaking of the bonding wire.

【０００５】本発明はこのような問題点を解決するもの
であり、その目的とするところは、ダイ・パッドの外周
部にシート上の溝を加工することによって、温度サイク
ルの時のせん断応力を緩和させボンディングワイヤーの
断線防止を実現する。さらに樹脂との密着性を向上さ
せ、剥離防止を簡単に実現することである。The present invention solves such a problem, and an object thereof is to form a groove on a sheet in the outer peripheral portion of a die pad so as to reduce the shear stress during temperature cycling. It alleviates and prevents disconnection of the bonding wire. Further, it is to improve the adhesion with the resin and easily realize peeling prevention.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体装置は、
プラスチックパッケージのダイ・パッドの外周部にシー
ト上の溝を加工することを特徴とする。The semiconductor device of the present invention comprises:
It is characterized in that a groove on the sheet is processed on the outer peripheral portion of the die pad of the plastic package.

【０００７】[0007]

【作用】本発明のダイ・パッドの外周部にシート状の溝
を加工したダイ・パッドを用いて樹脂封止を行なえば、
温度サイクルの時の剪断応力を緩和させボンディングワ
イヤーの断線を防止できる。さらに樹脂とリードフレー
ムの密着性を上げパッケージの信頼性向上に寄与するこ
とが出来る。[Function] If the die pad of the present invention is formed with a sheet-shaped groove on the outer periphery of the die pad and resin sealing is performed,
It is possible to alleviate the shear stress during the temperature cycle and prevent the bonding wire from breaking. Furthermore, the adhesion between the resin and the lead frame can be increased, which contributes to the improvement of the reliability of the package.

【０００８】[0008]

【実施例】以下、本発明を実施例にもとづき説明してい
く。EXAMPLES The present invention will be described below based on examples.

【０００９】図１は本発明のパッケージ断面図であり、
１１は本発明のダイ・パッド、１２はパッケージ樹脂、
１３は半導体チップ、１４はボンディングワイヤー、１
５はリードフレームである。図２は本発明のダイ・パッ
ドを用いたリードフレームの平面図及び断面図である。
図２（ａ）のＡ−Ａ’断面図が図２（ｂ）であり図１の
パッケージ樹脂１２によりダイ・パッド２６は樹脂内に
固定される。FIG. 1 is a sectional view of the package of the present invention.
11 is the die pad of the present invention, 12 is the package resin,
13 is a semiconductor chip, 14 is a bonding wire, 1
5 is a lead frame. FIG. 2 is a plan view and a sectional view of a lead frame using the die pad of the present invention.
2A is a sectional view taken along the line AA ′ of FIG. 2A, and the die pad 26 is fixed in the resin by the package resin 12 of FIG.

【００１０】以下工程を追いながら説明していく。The process will be described below by following the steps.

【００１１】従来のリードフレームの工程と同様にプレ
ス法によりリードフレームの形状にプレス抜きを行な
う。In the same manner as the conventional lead frame process, the lead frame is pressed out by the pressing method.

【００１２】次に、図２のようなシート状の溝を型を工
夫する事によりプレス法でダイ・パッド外周部に加工す
る。この時、溝の厚さとしては、ダイ・パッド部を厚さ
方向に１／２〜２／３程度とし、幅としては、１ｍｍ程
度のものとしできるだけたくさん溝を加工することが望
ましい。理由としては、シート状の溝（凸凹）に入り込
んだ樹脂の機械的強度によって応力を緩和させることで
ありこれによって温度サイクルの時のせん断応力、さら
に樹脂とリードフレームの密着性効果をあげるためであ
る。Next, a sheet-like groove as shown in FIG. 2 is formed on the outer periphery of the die pad by a pressing method by devising a die. At this time, it is desirable that the thickness of the groove is about ½ to ⅔ in the thickness direction of the die pad portion and the width is about 1 mm, and as many grooves as possible are processed. The reason is that the stress is relieved by the mechanical strength of the resin that has entered the sheet-shaped grooves (roughness), and this increases the shear stress during temperature cycling and the effect of adhesion between the resin and the lead frame. is there.

【００１３】最近、実用化されたＴ−ＳＯＰ（スィン・
スモール・アウトライン・パッケージ）等の薄型パッケ
ージの場合は、ダイ・パッドが、０． ８μｍ迄薄くな
るため、リードフレームに対して悪い影響のでない範囲
でできる限り深く溝を多くとる。Recently, the T-SOP (Syn.
In the case of thin packages such as small outline packages), the die pad is Since the thickness is as thin as 8 μm, many grooves are formed as deep as possible within a range where the lead frame is not adversely affected.

【００１４】ここでは、リードフレームをプレスで抜い
た後、ダイ・パッド部分にシート状の溝を加工したが、
アッセンブル工程上、リードフレーム材のダイ・パッド
に溝を加工した後、リードフレームの形状にプレス抜き
する事も可能である。Here, after the lead frame was removed by a press, a sheet-like groove was formed in the die pad portion.
In the assembly process, it is also possible to machine the groove on the die pad of the lead frame material and then press-press it into the shape of the lead frame.

【００１５】次に、このリードフレームを用いて従来の
プラスチックパッケージの製造工程と同様、ダイボンデ
ィング、ワイヤーボンディング、トランスファーモール
ド工程を経て、図１のようなプラスチックパッケージを
製作する。Next, using this lead frame, a plastic package as shown in FIG. 1 is manufactured through the same die bonding, wire bonding, and transfer molding processes as in the conventional plastic package manufacturing process.

【００１６】尚、本実施例では、プレス法を上げたが、
エッチング法でも同様の溝を加工することが可能であ
る。Although the pressing method is used in this embodiment,
The same groove can be processed by the etching method.

【００１７】[0017]

【発明の効果】以上述べたように本発明によれば、ダイ
パッド裏面の外周部にシート状の溝を加工することによ
り、温度サイクルの時のせん断応力に対する強度向上、
さらに、リフローの時のパッケージ内部に発生した熱応
力を分散、樹脂とリードフレームの密着性の向上を図る
ことにより、内部クラック発生を防止し、パッケージの
信頼性を向上させるという効果がある。As described above, according to the present invention, by forming a sheet-like groove on the outer peripheral portion of the back surface of the die pad, the strength against the shear stress during the temperature cycle is improved,
Further, the thermal stress generated inside the package at the time of reflow is dispersed, and the adhesion between the resin and the lead frame is improved, so that an internal crack is prevented from occurring and the reliability of the package is improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による半導体装置の主要部の断面図。FIG. 1 is a sectional view of a main part of a semiconductor device according to the present invention.

【図２】本発明による．リードフレーム部分の平面図及
び断面図。FIG. 2 is according to the present invention. The top view and sectional drawing of a lead frame part.

【図３】従来のリードフレーム部分の平面図及び断面
図。FIG. 3 is a plan view and a sectional view of a conventional lead frame portion.

【図４】従来のリードフレーム部分の平面図及び断面
図。FIG. 4 is a plan view and a sectional view of a conventional lead frame portion.

【図５】従来のリードフレーム部分の平面図及び断面
図。FIG. 5 is a plan view and a sectional view of a conventional lead frame portion.

【符号の説明】 １１・・・ダイ・パッド １２・・・パッケージ樹脂 １３・・・半導体チップ １４・・・ボンディングワイヤー １５・・・リードフレーム ２１・・・ダイ・パッド ２５・・・リードフレーム ２６・・・ダイ・パッド ３５・・・リードフレーム ３１・・・ダイ・パッド ３６・・・ダイ・パッド ４５・・・リードフレーム ４１・・・ダイ・パッド ４６・・・ディンプル ５５・・・リードフレーム ５１・・・ダイ・パッド ５６・・・スリット[Explanation of Codes] 11 ... Die Pad 12 ... Package Resin 13 ... Semiconductor Chip 14 ... Bonding Wire 15 ... Lead Frame 21 ... Die Pad 25 ... Lead Frame 26・ ・ ・ Die pad 35 ・ ・ ・ Lead frame 31 ・ ・ ・ Die pad 36 ・ ・ ・ Die pad 45 ・ ・ ・ Lead frame 41 ・ ・ ・ Die pad 46 ・ ・ ・ Dimple 55 ・ ・ ・ Lead frame 51 ... Die pad 56 ... Slit

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 プラスチックパッケージのリードフレー
ムにおいて、ダイ・パッド外周部にはシート状の溝が形
成されたことを特徴とする半導体装置。1. A semiconductor device, wherein a lead frame of a plastic package is provided with a sheet-like groove on an outer peripheral portion of a die pad.
JP25376491A 1991-10-01 1991-10-01 Semiconductor device Pending JPH0595077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25376491A JPH0595077A (en) 1991-10-01 1991-10-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25376491A JPH0595077A (en) 1991-10-01 1991-10-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0595077A true JPH0595077A (en) 1993-04-16

Family

ID=17255818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25376491A Pending JPH0595077A (en) 1991-10-01 1991-10-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0595077A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2836281A1 (en) * 2002-02-20 2003-08-22 St Microelectronics Sa Flat conducting grid for semiconductor case, comprises a perforated zone made so to form the radially elongated legs between a central platform and a peripheral part
CN102790036A (en) * 2012-08-03 2012-11-21 无锡红光微电子有限公司 SOT89-5L encapsulation lead framework
US9076776B1 (en) * 2009-11-19 2015-07-07 Altera Corporation Integrated circuit package with stand-off legs
CN112530885A (en) * 2019-09-18 2021-03-19 江苏长电科技股份有限公司 Chip packaging structure and packaging method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2836281A1 (en) * 2002-02-20 2003-08-22 St Microelectronics Sa Flat conducting grid for semiconductor case, comprises a perforated zone made so to form the radially elongated legs between a central platform and a peripheral part
US6885088B2 (en) 2002-02-20 2005-04-26 Stmicroelectronics Sa Flat leadframe for a semiconductor package
US9076776B1 (en) * 2009-11-19 2015-07-07 Altera Corporation Integrated circuit package with stand-off legs
CN102790036A (en) * 2012-08-03 2012-11-21 无锡红光微电子有限公司 SOT89-5L encapsulation lead framework
CN112530885A (en) * 2019-09-18 2021-03-19 江苏长电科技股份有限公司 Chip packaging structure and packaging method

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