JPH04242966A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH04242966A JPH04242966A JP14903591A JP14903591A JPH04242966A JP H04242966 A JPH04242966 A JP H04242966A JP 14903591 A JP14903591 A JP 14903591A JP 14903591 A JP14903591 A JP 14903591A JP H04242966 A JPH04242966 A JP H04242966A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- resin
- semiconductor device
- chip element
- sealed semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 81
- 229920005989 resin Polymers 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract 3
- 238000007789 sealing Methods 0.000 claims description 22
- 230000000694 effects Effects 0.000 abstract description 13
- 238000004873 anchoring Methods 0.000 abstract description 10
- 230000035939 shock Effects 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 230000008602 contraction Effects 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000006227 byproduct Substances 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 20
- 238000005452 bending Methods 0.000 description 14
- 238000000465 moulding Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＴＯ外形を対象とした
シングルエンドタイプの樹脂封止形半導体装置に関する
。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-end type resin-sealed semiconductor device intended for a TO outer shape.
【０００２】0002
【従来の技術】まず、本発明の実施対象となるＴＯ外形
の樹脂封止形半導体装置の従来構造を図６に示す。図に
おいて、１は半導体チップ素子、２はチップ素子１をマ
ウントしたリードフレームの放熱板を兼ねるダイパッド
、３はダイパッド２の一端側より引出したリード、４は
チップ素子１とリード３との間を接続したワイヤ、５は
チップ素子１，ダイパッド２の周域を封止した樹脂パッ
ケージである。なお、ダイパッド２は平板状であり、そ
の板面上にはリード３と反対側の先端部にねじ止め用穴
２ａが穿孔されており、この穴２ａを利用して半導体装
置をヒートシンクなどにねじ締結するようにしている。
また、樹脂パッケージ５は（ｂ）図のように外形を全域
で同じ厚さにした平坦形状のもの、あるいは（ｃ）図の
ようにチップ素子１から先端側（リード３と反対側）の
領域で、ダイパッド２の表側で封止樹脂の層厚を縮小す
るように段差部５ａを形成した台形状のものがある。2. Description of the Related Art First, FIG. 6 shows a conventional structure of a resin-sealed semiconductor device having a TO outer shape, which is an object of the present invention. In the figure, 1 is a semiconductor chip element, 2 is a die pad that also serves as a heat dissipation plate of the lead frame on which the chip element 1 is mounted, 3 is a lead drawn out from one end of the die pad 2, and 4 is a line between the chip element 1 and the lead 3. The connected wire 5 is a resin package in which the periphery of the chip element 1 and die pad 2 is sealed. Note that the die pad 2 has a flat plate shape, and a screw hole 2a is drilled on the plate surface at the end opposite to the leads 3. This hole 2a is used to screw the semiconductor device to a heat sink, etc. I am trying to conclude the agreement. The resin package 5 may have a flat outer shape with the same thickness over the entire area as shown in FIG. There is a trapezoidal type in which a stepped portion 5a is formed on the front side of the die pad 2 so as to reduce the layer thickness of the sealing resin.
【０００３】ここで、ダイパッド２， リード３を形成
したリードフレームは熱伝導性の高い銅，アルミなどの
金属板をプレス加工して作られたものである。また、樹
脂パッケージ５は例えばトランスファモールド法で成形
され、半導体装置の放熱性を考慮してダイパッド２の裏
面側（シートシンクへの取付け面）の封止樹脂層の厚み
が、チップ素子１をマウントした表面側に比べて薄くし
てある。[0003] The lead frame on which the die pad 2 and leads 3 are formed is made by pressing a metal plate such as copper or aluminum having high thermal conductivity. Furthermore, the resin package 5 is molded by, for example, a transfer molding method, and the thickness of the sealing resin layer on the back side of the die pad 2 (the mounting surface to the sheet sink) is adjusted so that the chip element 1 is mounted in consideration of the heat dissipation of the semiconductor device. It is thinner than the surface side.
【０００４】かかる樹脂封止形半導体装置は次記のよう
にして製作される。まず、リードフレームのダイパッド
２に対しリード３に近い側のチップマウント部に半導体
チップ素子１をダイボンディングし、さらにリード３と
チップ素子１との間でワイヤボンディングを施して内部
配線する。次にチップ素子１とともにリードフレームを
トランスファモールドの金型にインサートし、ここに樹
脂を注入して樹脂パッケージ５を成形し、チップ素子１
， ダイパッド２の周域を樹脂封止する。Such a resin-sealed semiconductor device is manufactured as follows. First, the semiconductor chip element 1 is die-bonded to the chip mount portion on the side closer to the leads 3 with respect to the die pad 2 of the lead frame, and then wire bonding is performed between the leads 3 and the chip element 1 for internal wiring. Next, the lead frame and the chip element 1 are inserted into a transfer mold, resin is injected here to form a resin package 5, and the chip element 1 is inserted into the mold.
, The area around the die pad 2 is sealed with resin.
【０００５】[0005]
【発明が解決しようとする課題】ところで、前記した樹
脂封止形半導体装置の構造では、樹脂パッケージ５の成
形時，あるいは製品出荷前に行うヒートショック試験（
環境加速評価試験）に伴い次記のような不具合が発生す
る。すなわち、樹脂パッケージ５の成形時には、先記の
ようにダイパッド２の表面側（チップ素子１がマウント
されている側）と裏面側では封止樹脂層の厚さが異なる
ため、成形後の樹脂硬化過程で生じる樹脂の収縮量（収
縮量は樹脂層の厚みが厚いほど大となる）の差によりダ
イパッド２に曲げ応力が加わり、図６（ｂ）に鎖線で表
したようにダイパッド全体が弓形に湾曲するような反り
（図示では反りが誇張して描かれている）が生じる。同
様なダイパッド２の反りは、ヒートショック試験を実施
した際にも金属のダイパッドと封止樹脂との熱膨張，収
縮量の差が原因で発生する。また、図６（ｃ）のような
台形をなす樹脂パッケージ５では、ダイパッド２のチッ
プマウント部と先端側とで樹脂層の厚みが異なるために
、特に樹脂の層厚が変化する段差部５ａの境界部近傍で
、樹脂の収縮による応力がダイパッド２に集中するよう
になる。[Problems to be Solved by the Invention] However, in the structure of the resin-sealed semiconductor device described above, a heat shock test (
The following problems occur during the accelerated environmental evaluation test. That is, when molding the resin package 5, the thickness of the sealing resin layer is different between the front side (the side where the chip element 1 is mounted) and the back side of the die pad 2 as described above, so the resin hardening after molding is difficult. Due to the difference in the amount of resin shrinkage that occurs during the process (the amount of shrinkage increases as the thickness of the resin layer increases), bending stress is applied to the die pad 2, and the entire die pad becomes arched, as shown by the chain line in Figure 6(b). A curvature-like warpage (the warp is exaggerated in the illustration) occurs. Similar warping of the die pad 2 also occurs when a heat shock test is performed due to the difference in the amount of thermal expansion and contraction between the metal die pad and the sealing resin. Furthermore, in the resin package 5 having a trapezoidal shape as shown in FIG. 6(c), since the thickness of the resin layer differs between the chip mount part and the tip side of the die pad 2, especially at the step part 5a where the resin layer thickness changes. Stress due to resin contraction becomes concentrated on the die pad 2 near the boundary.
【０００６】一方、ダイパッド２に前記のような反りが
発生すると、ここににマウントされたチップ素子１にも
曲げ応力が加わり、これが原因でチップ素子１にクラッ
クが生じて破損することがある。なお、チップ素子１に
生じるクラックの発生状況について、発明者等が調査し
たところによれば、チップ素子の面積が大になるほどク
ラックの発生率が大きく、また、クラックの発生箇所は
図６（ａ）に点線Ｃで表すようにダイパッド２の中央側
に向いたチップ素子の端部に多く集中し、特に（ｃ）図
のような形状の樹脂パッケージではその段差部５ａの影
響によりクラック発生率が高い傾向を示すことが明らか
になった。On the other hand, when the die pad 2 is warped as described above, bending stress is also applied to the chip element 1 mounted thereon, which may cause the chip element 1 to crack and be damaged. According to the inventors' investigation into the occurrence of cracks occurring in the chip element 1, the larger the area of the chip element, the higher the rate of crack occurrence, and the locations of crack occurrence are shown in Figure 6 (a). ), as shown by the dotted line C, most of the cracks are concentrated at the edge of the chip element facing toward the center of the die pad 2, and especially in a resin package shaped like the one shown in FIG. It was revealed that a high trend was observed.
【０００７】さらに、樹脂と金属製のリードフレームと
の接着性は一般的に低く、ダイパッド２に前記のような
反りが生じると、ダイパッド２と樹脂パッケージ５の樹
脂層との間の境界面に剥離が生じ、これが原因で半導体
装置の耐湿性が低下する。Furthermore, the adhesion between the resin and the metal lead frame is generally low, and if the die pad 2 is warped as described above, the interface between the die pad 2 and the resin layer of the resin package 5 will be damaged. Peeling occurs, which reduces the moisture resistance of the semiconductor device.
【０００８】本発明は上記の点にかんがみなされたもの
であり、ＴＯ外形のシングルエンドタイプの樹脂封止形
半導体装置を対象に、樹脂パッケージの成形時，ないし
は製品のヒートショック試験の際に、前記したリードフ
レームのダイパッドに発生する反り，封止樹脂層とリー
ドフレームとの間の剥離、およびダイパッドの反りが原
因でチップ素子に発生するクラックを巧みに回避できる
ようにした樹脂封止形半導体装置を提供することを目的
とする。[0008] The present invention has been made in view of the above points, and is aimed at a single-end type resin-sealed semiconductor device with a TO external shape, when molding a resin package or during a heat shock test of a product. A resin-sealed semiconductor that can skillfully avoid the warping that occurs in the die pad of the lead frame, peeling between the sealing resin layer and the lead frame, and cracks that occur in the chip element due to the warping of the die pad. The purpose is to provide equipment.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に、本発明は樹脂封止形半導体装置を次記のように構成
するものとする。
（１）チップ素子のマウント部分を除いてダイパッドの
面上に多数の小径な貫通穴を分散穿孔する。
（２）ダイパッドのチップ素子マウント部とダイパッド
の先端部に穿孔したねじ止め用穴との間の領域に、局部
的な断面縮小部を形成する。そして、前記断面縮小部を
形成する実施態様として、ダイパッドの面上に小径穴を
分散穿孔する、ダイパッドの表， 裏両面にスリット状
の凹溝を切込み形成する、ダイパッドの左右側面に切欠
溝を切込み形成するなどの構成がある。
（３）また、特に樹脂パッケージが台形であるものに対
しては、樹脂パッケージの段差部に対応して、ダイパッ
ドにチップマウントより先端側の面域で板厚が薄くなる
段差部を形成する解決手段がある。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a resin-sealed semiconductor device configured as follows. (1) A large number of small diameter through holes are drilled in a distributed manner on the surface of the die pad, excluding the mounting area of the chip element. (2) A locally reduced section is formed in the region between the chip element mounting portion of the die pad and the screw hole drilled at the tip of the die pad. Examples of embodiments for forming the reduced cross-section portion include drilling small diameter holes distributed on the surface of the die pad, cutting slit-like grooves on both the front and back sides of the die pad, and cutting grooves on the left and right sides of the die pad. There are configurations such as forming a notch. (3) In addition, especially for trapezoidal resin packages, a solution is to form a step part on the die pad where the plate thickness is thinner in the area on the tip side of the chip mount, corresponding to the step part of the resin package. There is a means.
【００１０】0010
【作用】上記の（１）項に記した構成によれば、樹脂パ
ッケージの成形工程でモールド金型に注入した溶融樹脂
の一部は、金型内を流動する過程でダイパッドの面上に
多数穿孔した貫通穴に流入して穴を埋める。したがって
、貫通穴内に充填された樹脂の投錨効果により、ダイパ
ッドとその表，裏両面を封止する樹脂層との間に高い結
合力が得られる。これにより、樹脂パッケージの成形工
程での樹脂収縮に起因するダイパッドの反り，およびこ
の反りに伴うダイパッドと封止樹脂層との間の剥離の発
生が良好に抑えられる。[Operation] According to the configuration described in item (1) above, a portion of the molten resin injected into the mold during the resin package molding process is deposited on the surface of the die pad in large numbers during the process of flowing inside the mold. It flows into the drilled through hole and fills the hole. Therefore, due to the anchoring effect of the resin filled in the through hole, a high bonding force can be obtained between the die pad and the resin layer sealing the front and back surfaces of the die pad. As a result, warping of the die pad due to resin shrinkage during the resin package molding process and occurrence of peeling between the die pad and the sealing resin layer due to this warping can be effectively suppressed.
【００１１】また、（２）項に記した構成においては、
樹脂パッケージの成形工程の際に、断面縮小部を形成す
るようダイパッドに加工した穴，スリット状凹溝，切欠
溝などに溶融樹脂の一部が流入するので、前記と同様な
樹脂の投錨効果が得られるほか、ヒートショック試験な
どの際の熱的ストレスによりダイパッドに作用する曲げ
応力が前記の断面縮小部に集中するようになる。したが
って、当該断面縮小部から外れた位置にマウントされて
いるチップ素子に加わる曲げ応力が緩和されることにな
るので、チップ素子のクラック発生を良好に回避できる
。[0011] Furthermore, in the configuration described in item (2),
During the molding process of the resin package, a portion of the molten resin flows into the holes, slit-like grooves, notches, etc. formed in the die pad to form the reduced cross-section portion, so that the same anchoring effect of the resin as described above is achieved. In addition, bending stress acting on the die pad due to thermal stress during a heat shock test or the like becomes concentrated in the reduced cross-sectional area. Therefore, the bending stress applied to the chip element mounted at a position away from the reduced cross-section portion is alleviated, so that cracks in the chip element can be effectively avoided.
【００１２】さらに（３）に記した構成においては、台
形樹脂パッケージの形状（段差部）による樹脂成形時の
樹脂収縮量の差が原因でダイパッドに加わる応力は、チ
ップ素子のマウント位置から外れたダイパッドの段差部
に集中するようになるので、前記（２）と同様にチップ
素子に加わる曲げ応力が緩和される。Furthermore, in the configuration described in (3), the stress applied to the die pad due to the difference in the amount of resin shrinkage during resin molding due to the shape of the trapezoidal resin package (stepped portion) is caused by the stress being applied to the die pad when the chip element is removed from the mounting position. Since the bending stress is concentrated on the stepped portion of the die pad, the bending stress applied to the chip element is alleviated as in (2) above.
【００１３】[0013]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。なお、各実施例で図６に対応する同一部材には同じ
符号が付してある。
実施例１：図１は本発明の請求項１に対応する実施例を
示すものである。この実施例では、リードフレームのダ
イパッド２に対し、チップマウント部の面域を除いて樹
脂パッケージ５の封止樹脂と接し合う領域に多数の小径
な貫通穴６が分散して穿孔されている。なお、この貫通
穴６はリードフレームをプレス加工する際に同時に打ち
抜かれる。そして、ダイパッド２にチップ素子１をマウ
ントし、かつリード３との間にワイヤ４をボンディング
した後に、樹脂モールドを施して樹脂パッケージ５を形
成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to FIG. 6 are given the same reference numerals. Embodiment 1: FIG. 1 shows an embodiment corresponding to claim 1 of the present invention. In this embodiment, a large number of small-diameter through holes 6 are dispersedly drilled in the die pad 2 of the lead frame in the region that contacts the sealing resin of the resin package 5, excluding the surface area of the chip mount portion. Note that this through hole 6 is punched out at the same time when the lead frame is pressed. After mounting the chip element 1 on the die pad 2 and bonding the wire 4 to the leads 3, resin molding is performed to form the resin package 5.
【００１４】このようにして作られた樹脂封止形半導体
装置は、樹脂パッケージ５の成形工程でモールド金型に
注入した溶融樹脂がダイパッド２に穿孔した貫通穴６の
中にも充填され、その投錨効果によりダイパッド２の表
，裏両面側の封止樹脂層との結合力が高まる。これによ
りダイパッド２の反り，封止樹脂との間の剥離の発生、
並びにダイパッド２の反りに起因するチップ素子１のク
ラック発生が抑えられる。なお、貫通穴６による投錨効
果を十分に発揮させるためには、穴径の小さな貫通穴６
を広範囲に分散させて穿孔するのが好ましい。In the resin-sealed semiconductor device manufactured in this manner, the molten resin injected into the mold during the molding process of the resin package 5 is also filled into the through-hole 6 drilled in the die pad 2. The anchoring effect increases the bonding strength with the sealing resin layers on both the front and back sides of the die pad 2. This causes warping of the die pad 2, peeling from the sealing resin,
In addition, cracks in the chip element 1 due to warping of the die pad 2 are suppressed. In addition, in order to fully exhibit the anchoring effect of the through hole 6, it is necessary to use the through hole 6 with a small hole diameter.
It is preferable to disperse the holes over a wide range.
【００１５】実施例２：図２は本発明の請求項２，３に
対応する実施例を示す。この実施例では、ダイパッド２
の面上でチップ素子１のマウント部とダイパッドの先端
側に穿孔したねじ止め用穴２ａとの間の部分に、横一列
に並ぶ小径穴７を分散穿孔してこの部分に局部的な断面
縮小部８を形成している。この小径穴７は樹脂パッケー
ジの成形時にモールド金型へ注入した封止樹脂で充填さ
れ、その投錨効果で実施例１と同様にダイパッド２と封
止樹脂層との結合力が高まる。さらに、ヒートショック
試験などで熱的ストレスが加わった場合でも、ダイパッ
ド２に加わる反り応力が小径穴７を含む断面縮小部８に
移行してこの部分に集中するようになる。したがって、
この断面縮小部８から外れた位置にマウントされている
チップ素子１に作用する曲げ応力が大幅に緩和される。
これにより、チップ素子１のクラック発生，並びにダイ
パッド２と封止樹脂層との間の剥離の発生を回避できる
。なお、前記穴７の寸法，ピッチ間隔，穴の数などは、
ダイパッド２の厚さ寸法，樹脂パッケージ５のモールド
成形条件などを勘案して適正に決めるものとする。Embodiment 2: FIG. 2 shows an embodiment corresponding to claims 2 and 3 of the present invention. In this embodiment, die pad 2
On the surface of the die pad, small diameter holes 7 arranged in a row are dispersedly drilled in the area between the mounting part of the chip element 1 and the screw hole 2a drilled on the tip side of the die pad to locally reduce the cross section in this area. 8. This small diameter hole 7 is filled with the sealing resin injected into the mold during molding of the resin package, and its anchoring effect increases the bonding force between the die pad 2 and the sealing resin layer as in the first embodiment. Furthermore, even when thermal stress is applied in a heat shock test or the like, the warping stress applied to the die pad 2 is transferred to the reduced cross-section portion 8 including the small diameter hole 7 and concentrated there. therefore,
The bending stress acting on the chip element 1 mounted at a position away from the reduced cross-section portion 8 is significantly alleviated. Thereby, cracks in the chip element 1 and peeling between the die pad 2 and the sealing resin layer can be avoided. The dimensions, pitch interval, number of holes, etc. of the holes 7 are as follows:
It shall be determined appropriately by taking into consideration the thickness dimension of the die pad 2, the molding conditions of the resin package 5, etc.
【００１６】実施例３：図３は本発明の請求項２，４に
対応した実施例であり、ダイパッド２に対し、チップ素
子１のマウントとねじ止め用穴２ａとの間の領域でダイ
パッド２の表，裏両面に板面を横切るようなスリット状
の凹溝９を切削加工してこの部分に断面縮小部８を形成
したものである。なお、図示では前記スリット状凹溝９
がダイパッド２の表面側（チップ素子１をマウントした
面）に１条，裏面側には２条形成されている。このスリ
ット状凹溝９は、先記した実施例２の小径穴７と同様に
封止樹脂に対し投錨効果を発揮してダイパッド２と封止
樹脂層との間の剥離を防ぐとともに、ダイパッドの反り
に対しても凹溝９の部分に応力を集中させてチップ素子
１に加わる曲げ応力を緩和してクラックの発生を防止す
ることができる。Embodiment 3: FIG. 3 is an embodiment corresponding to claims 2 and 4 of the present invention. A slit-shaped concave groove 9 that crosses the plate surface is cut on both the front and back surfaces of the plate, and a reduced cross-section portion 8 is formed in this portion. In addition, in the illustration, the slit-shaped groove 9
One strip is formed on the front side of the die pad 2 (the surface on which the chip element 1 is mounted), and two strips are formed on the back side. This slit-shaped groove 9 exerts an anchoring effect on the sealing resin in the same manner as the small diameter hole 7 of the second embodiment described above, prevents separation between the die pad 2 and the sealing resin layer, and also prevents the die pad from peeling off. Even in the case of warping, stress can be concentrated on the groove 9 to alleviate the bending stress applied to the chip element 1, thereby preventing the occurrence of cracks.
【００１７】実施例４：図４は本発明の請求項２，５に
対応した実施例であり、断面縮小部８に対応してダイパ
ッド２には左右側面に断面Ｖ字形の切欠溝１０を切込み
形成したものであり、この切欠溝１０が実施例２，３に
おける小径穴７，スリット状凹溝９と同様な効果を奏す
る。なお、切欠溝１０の形状は図示例のＶ溝に限定され
るものではなく、円形，角形，楔形の溝などあってもよ
い。Embodiment 4: FIG. 4 is an embodiment corresponding to claims 2 and 5 of the present invention, in which notch grooves 10 having a V-shaped cross section are cut into the left and right sides of the die pad 2 corresponding to the reduced cross section portion 8. This notched groove 10 has the same effect as the small diameter hole 7 and the slit-shaped groove 9 in the second and third embodiments. Note that the shape of the notch groove 10 is not limited to the V-groove shown in the illustrated example, but may be a circular, square, or wedge-shaped groove.
【００１８】実施例５：図５は本発明の請求項６に対応
した実施例であり、台形樹脂パッケージ５の表面側には
、チップマウント部より先端側で層厚が縮小する段差部
５ａが形成してあり、このパッケージの段差部５ａに対
応してダイパッド２にはチップマウント部より先端側の
面域で板厚が薄くなる段差部２ｂが形成されている。
なお、この段差部２ｂの板厚ｄは、チップマウント部の
板厚をＤとしてＤ＞ｄ＞１／２・Ｄの範囲に選定されて
いる。Embodiment 5: FIG. 5 is an embodiment corresponding to claim 6 of the present invention, in which the surface side of the trapezoidal resin package 5 has a stepped portion 5a whose layer thickness decreases on the tip side from the chip mount portion. Corresponding to the stepped portion 5a of the package, the die pad 2 is formed with a stepped portion 2b which is thinner in a surface area closer to the tip than the chip mount portion. Note that the plate thickness d of the stepped portion 2b is selected in the range of D>d>1/2·D, where D is the plate thickness of the chip mount portion.
【００１９】かかる構成により、樹脂パッケージ５の段
差部５ａによる成形時の樹脂収縮が原因でダイパッド２
に作用する曲げ応力は、チップ素子１のマウント位置か
ら外れた段差部２ｂの境界部が切欠きとして働くので、
この部分に集中するようになる。したがって、ダイパッ
ド２にマウントされているチップ素子１に加わる曲げ応
力が緩和され、チップ素子のクラック発生を確実に防止
できる。With this configuration, the resin shrinkage during molding due to the stepped portion 5a of the resin package 5 causes the die pad 2 to
The bending stress acting on the chip element 1 is caused by the boundary of the stepped portion 2b that is away from the mounting position of the chip element 1 acting as a notch.
Start concentrating on this part. Therefore, the bending stress applied to the chip element 1 mounted on the die pad 2 is alleviated, and cracks in the chip element can be reliably prevented.
【００２０】[0020]
【発明の効果】本発明の樹脂封止形半導体装置は、以上
説明したように構成されているので、次記の効果を奏す
る。請求項１の構成においては、リードフレームのダイ
パッドに対し、チップ素子のマウント部を除く封止樹脂
との接触面域に多数の小径貫通穴を分散穿孔したので、
この貫通穴に充填した封止樹脂の投錨効果により、樹脂
パッケージの成形工程，あるいは製品のヒートショック
試験に伴う応力が原因でダイパッドに発生する反り，並
びに封止樹脂との間の剥離を良好に回避できる。したが
って、ダイパッドの曲げ応力に起因してチップ素子にク
ラックが発生する割合も少なくなるほか、前記投錨効果
によりダイパッドと封止樹脂層との間の結合力が向上し
て高い耐湿性が得られるなど、従来構造と比べて製品の
良品率を大幅に向上できる。The resin-sealed semiconductor device of the present invention is constructed as described above, and therefore provides the following effects. In the structure of claim 1, a large number of small-diameter through holes are dispersedly drilled in the die pad of the lead frame in the contact area with the sealing resin, excluding the mounting portion of the chip element.
The anchoring effect of the sealing resin filled in this through hole effectively prevents warping that occurs in the die pad due to stress associated with the molding process of the resin package or the heat shock test of the product, as well as peeling from the sealing resin. It can be avoided. Therefore, the rate at which cracks occur in chip elements due to the bending stress of the die pad is reduced, and the bonding force between the die pad and the sealing resin layer is improved due to the anchoring effect, resulting in high moisture resistance. , the rate of non-defective products can be significantly improved compared to the conventional structure.
【００２１】また、請求項２ないし５の構成においては
、ダイパッドに対し、チップ素子のマウント部とダイパ
ッドの先端部に穿孔したねじ止め用穴との間の領域に、
小径穴，スリット状凹溝，切欠溝などを加工して局部的
な断面縮小部を形成したので、この断面縮小部の穴，溝
に充填された封止樹脂の投錨効果で前記と同等な効果が
得られるほか、特にダイパッドに作用する曲げ応力がチ
ップ素子のマウント部から外れた位置の前記断面縮小部
に集中するようになるので、クラック発生の要因となる
チップ素子への曲げ応力をより効果的に緩和できる。[0021] Furthermore, in the structure of claims 2 to 5, the die pad is provided with a region between the mounting portion of the chip element and the screw hole drilled at the tip of the die pad.
Since a small diameter hole, slit-like groove, notch groove, etc. are formed to form a locally reduced section, the same effect as above can be achieved due to the anchoring effect of the sealing resin filled in the hole and groove of this reduced section. In addition, the bending stress that acts on the die pad in particular concentrates on the reduced cross-sectional area located away from the mounting section of the chip element, making it possible to more effectively reduce the bending stress on the chip element that causes cracks. can be alleviated.
【００２２】さらに、請求項６の構成においても、前記
と同様に封止樹脂層の硬化に伴う樹脂収縮，熱的ストレ
スに起因してダイパッド上にマウントされたチップ素子
に作用する曲げ応力を効果的に緩和してクラックの発生
を良好に防止できる。Furthermore, in the structure of claim 6, similarly to the above, bending stress acting on the chip element mounted on the die pad due to resin shrinkage and thermal stress as the sealing resin layer hardens is effectively reduced. It is possible to effectively prevent the occurrence of cracks.
【図１】本発明の実施例１の構成図であり、（ａ）は平
面図、（ｂ）は側面図FIG. 1 is a configuration diagram of Embodiment 1 of the present invention, in which (a) is a plan view and (b) is a side view.
【図２】本発明の実施例２の構成図であり、（ａ）は平
面図、（ｂ）は側面図FIG. 2 is a configuration diagram of Embodiment 2 of the present invention, (a) is a plan view, and (b) is a side view.
【図３】本発明の実施例３の構成図であり、（ａ）は平
面図、（ｂ）は側面図FIG. 3 is a configuration diagram of Embodiment 3 of the present invention, (a) is a plan view, and (b) is a side view.
【図４】本発明の実施例４の構成図であり、（ａ）は平
面図、（ｂ）は側面図FIG. 4 is a configuration diagram of a fourth embodiment of the present invention, in which (a) is a plan view and (b) is a side view.
【図５】本発明の実施例５の構成図であり、（ａ）は平
面図、（ｂ）は側面図FIG. 5 is a configuration diagram of Embodiment 5 of the present invention, in which (a) is a plan view and (b) is a side view.
【図６】従来における樹脂封止形半導体装置の構成図で
あり、（ａ）は平面図、（ｂ）は側断面図、（ｃ）は樹
脂パッケージが台形である構成の側断面図FIG. 6 is a configuration diagram of a conventional resin-sealed semiconductor device, in which (a) is a plan view, (b) is a side sectional view, and (c) is a side sectional view of a configuration in which the resin package is trapezoidal.
１ チップ素子 ２ ダイパッド ２ａ ねじ止め用穴 ２ｂ 段差部 ３ リード ５ 樹脂パッケージ ５ａ 段差部 ６ 貫通穴 ７ 小径穴 ８ 断面縮小部 ９ スリット状凹溝 １０ 切欠溝 1 Chip element 2 Die pad 2a Screw hole 2b Step part 3 Lead 5 Resin package 5a Step part 6 Through hole 7 Small diameter hole 8 Reduced section section 9 Slit-shaped groove 10 Notch groove
Claims (6)
のダイパッドにチップ素子をマウントし、さらにダイパ
ッド， チップ素子の周域を樹脂封止してなる樹脂封止
形半導体装置において、チップ素子のマウント部分を除
いてダイパッドの面上に多数の小径な貫通穴を分散穿孔
したことを特徴とする樹脂封止形半導体装置。[Claim 1] A resin-sealed semiconductor device in which a chip element is mounted on a die pad of a lead frame with leads drawn out on one end side, and the peripheral area of the die pad and the chip element is further sealed with resin, in which the chip element is mounted. 1. A resin-sealed semiconductor device characterized in that a large number of small-diameter through-holes are dispersedly drilled on the surface of a die pad except for a portion thereof.
のダイパッドにチップ素子をマウントし、さらにダイパ
ッド， チップ素子の周域を樹脂封止してなる樹脂封止
形半導体装置であり、リードと反対側のダイパッド先端
部にねじ止め用穴を有するものにおいて、ダイパッドの
チップ素子マウント部とねじ止め用穴との間の領域に、
局部的な断面縮小部を形成したことを特徴とする樹脂封
止形半導体装置。[Claim 2] A resin-sealed semiconductor device in which a chip element is mounted on a die pad of a lead frame with leads drawn out on one end side, and the surrounding areas of the die pad and chip element are sealed with resin, and the die pad and the chip element are sealed with resin. In the die pad having a screw hole at the tip of the side die pad, in the area between the chip element mount part of the die pad and the screw hole,
A resin-sealed semiconductor device characterized by forming a locally reduced section.
パッドの面上に断面縮小部に対応する小径穴を分散穿孔
したことを特徴とする樹脂封止形半導体装置。3. A resin-sealed semiconductor device according to claim 2, wherein small diameter holes corresponding to the reduced cross-section portions are dispersedly drilled on the surface of the die pad.
パッドの表， 裏両面に断面縮小部に対応するスリット
状の凹溝を切込み形成したことを特徴とする樹脂封止形
半導体装置。4. A resin-sealed semiconductor device according to claim 2, wherein slit-like grooves corresponding to the reduced cross-section portions are cut into both the front and back surfaces of the die pad.
パッドの左右側面に断面縮小部に対応する切欠溝を切込
み形成したことを特徴とする樹脂封止形半導体装置。5. A resin-sealed semiconductor device according to claim 2, wherein grooves corresponding to the reduced cross-section portions are cut into the left and right side surfaces of the die pad.
のダイパッドにチップ素子をマウントし、さらにダイパ
ッド， チップ素子の周域を樹脂封止してなる樹脂封止
形半導体装置であり、リードと反対側のダイパッド先端
部にねじ止め用穴を有し、かつ樹脂パッケージの先端側
域に封止樹脂の層厚が薄くなる段差部を形成したものに
おいて、前記樹脂パッケージの段差部に対応して、ダイ
パッドにチップマウントより先端側の面域で板厚が薄く
なる段差部を形成したことを特徴とする樹脂封止形半導
体装置。[Claim 6] A resin-sealed semiconductor device in which a chip element is mounted on a die pad of a lead frame with leads drawn out on one end side, and the peripheral area of the die pad and chip element is further sealed with resin, and the lead frame is opposite to the lead. A screw hole is provided at the tip of the side die pad, and a stepped portion in which the layer thickness of the sealing resin becomes thinner is formed in the tip side region of the resin package, corresponding to the stepped portion of the resin package, A resin-sealed semiconductor device characterized in that a die pad is formed with a stepped portion in which the plate thickness becomes thinner in a surface area on the tip side from a chip mount.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14903591A JPH04242966A (en) | 1990-08-09 | 1991-06-21 | Resin sealed semiconductor device |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21131090 | 1990-08-09 | ||
| JP2-211310 | 1990-08-09 | ||
| JP29312090 | 1990-10-30 | ||
| JP2-293120 | 1990-10-30 | ||
| JP14903591A JPH04242966A (en) | 1990-08-09 | 1991-06-21 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04242966A true JPH04242966A (en) | 1992-08-31 |
Family
ID=27319670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14903591A Pending JPH04242966A (en) | 1990-08-09 | 1991-06-21 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04242966A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6727575B2 (en) | 2001-04-12 | 2004-04-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2006005281A (en) * | 2004-06-21 | 2006-01-05 | Nippon Inter Electronics Corp | Lead frame, manufacturing method thereof, and resin-sealed semiconductor device |
| JP2007157801A (en) * | 2005-12-01 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor module and its manufacturing method |
| JP2010034348A (en) * | 2008-07-30 | 2010-02-12 | Sanyo Electric Co Ltd | Semiconductor device and semiconductor module |
| JP2011505689A (en) * | 2007-12-03 | 2011-02-24 | ソウル セミコンダクター カンパニー リミテッド | Slim LED package |
| CN103928422A (en) * | 2014-03-27 | 2014-07-16 | 张轩 | Lead frame suitable for high-temperature environment |
| JP2016207714A (en) * | 2015-04-16 | 2016-12-08 | ローム株式会社 | Semiconductor device |
-
1991
- 1991-06-21 JP JP14903591A patent/JPH04242966A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6727575B2 (en) | 2001-04-12 | 2004-04-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2006005281A (en) * | 2004-06-21 | 2006-01-05 | Nippon Inter Electronics Corp | Lead frame, manufacturing method thereof, and resin-sealed semiconductor device |
| JP4537774B2 (en) * | 2004-06-21 | 2010-09-08 | 日本インター株式会社 | Lead frame manufacturing method |
| JP2007157801A (en) * | 2005-12-01 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor module and its manufacturing method |
| JP2011505689A (en) * | 2007-12-03 | 2011-02-24 | ソウル セミコンダクター カンパニー リミテッド | Slim LED package |
| JP2010034348A (en) * | 2008-07-30 | 2010-02-12 | Sanyo Electric Co Ltd | Semiconductor device and semiconductor module |
| CN103928422A (en) * | 2014-03-27 | 2014-07-16 | 张轩 | Lead frame suitable for high-temperature environment |
| JP2016207714A (en) * | 2015-04-16 | 2016-12-08 | ローム株式会社 | Semiconductor device |
| US10497644B2 (en) | 2015-04-16 | 2019-12-03 | Rohm Co., Ltd. | Semiconductor device with first and second semiconductor chips connected to insulating element |
| US11177198B2 (en) | 2015-04-16 | 2021-11-16 | Rohm Co., Ltd. | Plurality of lead frames electrically connected to inductor chip |
| US11699641B2 (en) | 2015-04-16 | 2023-07-11 | Rohm Co., Ltd. | Semiconductor device |
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