JPH0594999A - Ldd type field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an implantation and trapping phenomenon from occurring so as to realize an LDD type transistor excellent in transfer characteristic by a method wherein a second gate electrode is provided to the side face of a first gate electrode covering the region lower than a source region and a drain region in impurity concentration. CONSTITUTION:A polysilicon layer composed of a gate insulating film 2 and a first conductive layer 3 is formed on a P-type silicon substrate 1 and then processed through an RIE method, and ann-region 5 is formed through an ion implantation method. Then, through a vacuum CVD method, a second conductive layer 6 of tungsten is formed on the first conductive layer 3. In succession, a source or a drain region 7 of high concentration is formed through an on implantation method, and the upper part of the n-region 5 of comparatively low concentration is covered wyith the second conductive layer 6. By this setup, as an n-region is lessened in resistance, an LDD type transistor of this design cart be kept high in transmission conductance and ion current and protected against the implantation and the trapping of hot ions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to an LDD (Lightly Doped Drai).
n) Concerning the structure.

[0002]

2. Description of the Related Art Ultra L typified by DRAM, SRAM, etc.
The capacity of SI has increased fourfold in three years, and such an improvement in the degree of integration within a limited chip area was brought about by the miniaturization of each element forming the integrated circuit. Is. However, with the progress of miniaturization, there have been problems such as a decrease in breakdown voltage due to an increase in electric field inside the transistor due to a reduction in transistor size, deterioration of element characteristics due to hot electrons, and a short channel effect. In particular, since a very high electric field is generated near the drain, a proposal and practical application of a transistor structure aiming at suppressing the electric field near the drain are being made.

The LDD structure transistor is a typical example thereof, and FIG. 3 shows a sectional view of the LDD type transistor. 1 is a P-type silicon substrate, 2 is a gate insulating film, 11
Is a gate electrode, 5 is a relatively low concentration n ⁻ region, 7 is a source or drain region, 8 is a protective insulating film, 9 is a contact portion, 10 is a metal wiring, and 12 is a sidewall.

In the process of forming the diffusion layer of the LDD type transistor, the gate electrode 11 is used as a mask to form the n ⁻ region 5 by ion implantation of low-concentration phosphorus, and then the gate electrode 11 is formed.
A side wall 12 is formed on the side surface of the substrate, and using this as a mask, high-concentration arsenic ion implantation is performed to form the source or drain region 7.

[0005]

Although the n ⁻ region 5 shown above functions as a resistance, it is necessary to increase its resistance value in order to obtain a higher breakdown voltage. However, conversely, when the transistor is on, this n ⁻ region 5 acts as a series resistance, which causes a decrease in on-current and a decrease in transfer conductance. Therefore, there is a limit to increase the resistance value, and the optimum value is selected. There is a need. However, as miniaturization of the transistor progresses, it is difficult to obtain a high breakdown voltage while maintaining the transfer characteristic only by optimizing the resistance of the n ⁻ region 5. Also, n
^- since that affects a relatively high electric field in the region 5, and hot electrons are generated, occur infusion trapping phenomenon to no side wall 3 below the gate electrode, hot electrons the n ^- turned into a region 5 depletion, the Since the resistance value is increased, there is a problem peculiar to the LDD structure in which the transfer characteristic is deteriorated.

An object of the present invention is to provide an LDD type transistor having good transfer characteristics by preventing the above injection trapping phenomenon.

[0007]

According to another aspect of the present invention, there is provided an LDD field effect transistor in which a region having an impurity concentration lower than that of a source region and a drain region is provided at a channel end near the source region and the drain region. In the field effect transistor having the provided LDD structure,
A second gate electrode is provided on at least a side surface of the first gate electrode so as to cover a region having an impurity concentration lower than that of the source region and the drain region.

According to a second aspect of the present invention, there is provided a method of manufacturing an LDD type field effect transistor according to the first aspect of the present invention.
A method for manufacturing a DD-type field effect transistor, comprising a step of forming a polysilicon film after forming a silicon oxide film on a semiconductor substrate, and a step of forming a first gate electrode made of polysilicon by a photoetching step. , Using the first gate electrode as a mask,
A step of forming a diffusion layer, a step of forming tungsten, tungsten silicide or polysilicon as a second gate electrode on at least a side surface of the first gate electrode by a low pressure CVD method, and using the first and second gate electrodes as a mask And a second diffusion layer having a higher impurity concentration than the first diffusion layer and serving as a source region and a drain region, is formed by an ion implantation method.

[0009]

In the LDD type transistor of the present invention,
Since the gate electrode is present above the n ⁻ region, the n ⁻
An electric field acts between the region and the gate electrode in the direction perpendicular to the substrate, the resistance of the n ⁻ region is reduced, and the injection trap of hot electrons is suppressed.

[0010]

The present invention will be described in detail below based on an example.

FIG. 1 shows a structural sectional view of an embodiment of the present invention described in claim 1, and FIG. 2 shows a manufacturing process drawing of an embodiment of the present invention described in claim 2. 1 is a P-type silicon substrate, 2 is a gate insulating film, 3 is a first gate electrode, 4 is a resist, 5
Is a relatively low resistance n ⁻ region, 6 is a second gate, 7 is a source or drain region, 8 is an interlayer insulating film, 9
Indicates a contact portion, and 10 indicates a metal wiring. A feature of the present invention is that, as shown in FIG. 1, the first gate electrode 3 and the second gate electrode 6 are formed on the n ⁻ region having a relatively low resistance.

Next, the manufacturing process of the present invention according to claim 2 will be described with reference to FIG.

First, a gate oxide film 2 is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method to a thickness of 80 to 120 Å,
A polysilicon film which is the first gate electrode 3 is deposited by 1000 to 3000 Å by using the low pressure CVD method, and phosphorus which is an N-type impurity is diffused into the polysilicon film at a high concentration by the conventional technique (FIG. 2A). ).

Next, the polysilicon film 3 is processed by the RIE method or the like by using the resist pattern 4 formed by the photolithography process as a mask, and then the polysilicon film 3 is used as a mask by which the silicon substrate 1 is doped with phosphorus which is an N-type impurity. Is added by an ion implantation method to form an n ⁻ region 5 (FIG. 2B). The concentration of phosphorus added at this time was 1.5 to 5 × 10 ¹⁷ cm ⁻³ .

Next, after removing the resist pattern 4,
Low pressure CVD using WF ₆ and SiH ₄ as source gas
A tungsten film as the second gate electrode 6 is formed by the method. In this case, tungsten is not deposited on the silicon oxide film which is the gate insulating film 2, and the polysilicon film 3
A tungsten layer 6 is selectively formed on the upper and side surfaces of the substrate (FIG. 2C). The deposition conditions by the low pressure CVD method are as follows: WF ₆ is 30 ccm, SiH ₄ is 18 sccm, the pressure is 0.1 Torr, the temperature is 280 ° C., and the deposited film thickness is about 600 to 1500Å. The selective growth of the tungsten film by the low pressure CVD method used here may be performed by a known method in the art. Moreover, polysilicon and tungsten silicide can be used as the material of the second gate electrode 6.

Next, when arsenic is implanted at a high concentration into the silicon substrate 1 by using the ion implantation method with the polysilicon as the first gate electrode 3 and the tungsten film as the second gate electrode 6 as a mask, a high concentration is obtained. A source or drain region 7 is formed. Through the above steps, a relatively low concentration n ⁻ region 5 connected to the high concentration drain region 7 is covered with the tungsten film which is the second conductive layer 6 (FIG. 2).
(D)).

Next, the deposition of the interlayer insulating film 8, the frontage of the contact 9 to the source or drain region 7 and the metal wiring 10.
Is performed by a conventional technique (FIG. 2 (e)).

Although the second gate electrode 6 is formed on the upper and side surfaces of the first gate electrode 3 in the above embodiment, it is sufficient that the second gate electrode 6 is present on the upper part of the n ⁻ region 5.
The second gate electrode 6 may be formed only on the side surface of the gate electrode 3.

[0019]

As described [Effect Invention above in detail, by using the present invention, during operation of the transistor, n ^- field acts in the vertical direction from a portion of the upper gate electrode region, n ^- regions of the resistor Therefore, high transmission tungsten and ion current can be secured, and since the upper part of the n ⁻ region is covered with the gate electrode, the injection and trapping phenomenon of hot electrons into the sidewall, which is a problem in the LDD structure, is suppressed. , High reliability can be obtained.

Further, in the present invention, when tungsten or tungsten silicide is used as the second gate electrode, its wiring resistance is much reduced as compared with the case where the gate electrode is formed of only polysilicon, and therefore the operating speed of the circuit. Is improved. Further, in the manufacturing method shown in the above embodiment, since the gate electrode has a two-layer structure, additional steps of deposition and processing are required, but all can be formed in a self-aligned manner by one lithography process. , It is possible to deal with it sufficiently by using the conventional process technology.

As described above, it is possible to relatively easily provide a high-performance and highly-reliable field-effect transistor which constitutes a main part of a semiconductor integrated circuit which is being miniaturized.

[Brief description of drawings]

FIG. 1 is a configuration cross-sectional view of an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of an example of the present invention.

FIG. 3 is a cross-sectional view of a conventional LDD type transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate insulating film 3 1st conductive layer 4 Resist pattern 5 n ^- region 6 2nd conductive layer 7 Source or drain region 8 Interlayer insulating film 9 Contact part 10 Metal wiring

Claims (2)

[Claims] 1. In a field effect transistor having an LDD structure in which a region having an impurity concentration lower than that of a source region and a drain region is provided at a channel end near the source region and the drain region, at least on a side surface of a first gate electrode. An LDD field effect transistor, wherein a second gate electrode is provided so as to cover a region having an impurity concentration lower than that of the source region and the drain region. 2. A step of forming a polysilicon film after forming a silicon oxide film on a semiconductor substrate, a step of forming a first gate electrode made of the polysilicon by a photoetching step, and a step of forming the first gate. Forming a first diffusion layer by an ion implantation method using the electrode as a mask; forming tungsten, tungsten silicide or polysilicon as a second gate electrode on at least a side surface of the first gate electrode by a low pressure CVD method; Forming a second diffusion layer to be a source region and a drain region, which has a higher impurity concentration than the first diffusion layer, by an ion implantation method using the first and second gate electrodes as a mask. L according to claim 1
Method for manufacturing DD type field effect transistor.