JPH0591418A - Phase compensating circuit - Google Patents

Abstract

PURPOSE:To control an output pulse signal in its optimum phase regardless of the variance of LSI production by controlling the input signal with the exter nal control voltage based on a reference signal. CONSTITUTION:The input timing pulse signal Pt supplied to an input terminal phi1 is turned into a shaped signal St by an LPF 1 and supplied to a comparator 2. The comparator 2 compares the signal St with the threshold voltage Vth supplied from a threshold voltage control circuit 5 and outputs an output pulse signal Po with which the range having the value larger than the voltage Vth is defined as the pulse width Tp. Then a phase comparator 3 checks the phase difference of the signal Po set to a reference pulse signal Pi. The output Px of the comparator 3 is converted into a voltage signal Vx by an LPF 4. Then the signal Vx is compared with the external control voltage Vc by the circuit 5. The circuit 5 controls the voltage Vth. Then the delay time of the signal Po is controlled with the control of the voltage Vth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase compensation circuit for controlling the phase of an output pulse signal, and more particularly to a phase of a timing pulse signal for driving a CCD solid-state image pickup device and a phase of a sampling pulse signal used for a correlated double sampling circuit. The present invention relates to a phase compensation circuit suitable for controlling the.

[0002]

2. Description of the Related Art Generally, an output signal S obtained at an output terminal of a CCD solid-state image pickup device 21 shown in FIG. 5 is a horizontal transfer pulse signal HD from a timing pulse generation circuit 22 and a charge reset pulse signal (hereinafter, simply charge The waveform is determined by RG (referred to as a reset signal). FIG. 6 shows a horizontal transfer pulse signal HD, a charge reset signal RG and a CCD.
The waveform of the output signal S from the solid-state image sensor 21 is shown.

The output signal S from the CCD solid-state image pickup device 21 is composed of two kinds of sampling pulse signals XShp and XShd from the timing pulse generation circuit 22.
The reset noise is removed by the correlated double sampling circuit 23 to which is supplied. The sampling pulse signals XShp and XShd need to have a constant phase relationship with the output signal S.

That is, one sampling pulse signal XS
hp is a portion FT of the feedthrough level of the output signal S
In addition, the other sampling pulse signal XShd must correspond to the signal level portion SL of the output signal S, respectively. Otherwise, the feedthrough level and the signal level of the output signal S cannot be properly sampled and held, the amplitude of the output signal S obtained at the output terminal is reduced, and the reset noise is removed by the correlated double sampling circuit 23. It becomes impossible to do it enough.

By the way, the waveform of the output signal from the CCD solid-state image pickup device 21, as shown in FIG. The waveform is delayed from the output timing of the signal RG. In the illustrated example, the rise of the reset level of the output signal S is delayed from the rise of the charge reset signal RG by a time t ₁ ,
An example in which the start time of the signal level of the output signal S is delayed by the time t ₂ from the fall of the horizontal transfer pulse signal HD is shown.

The delay times t ₁ and t ₂ vary due to variations in the source follower circuit in the CCD solid-state image pickup device 21. Therefore, the waveform of the output signal from the CCD solid-state image pickup device 21 is not constant due to the above variation, and the phase itself of the waveform varies. Therefore, the output signal S and the sampling pulse signals XShp and XSh
There is a risk that the phase relationship with d is deviated, and as a result, the amplitude of the output signal S is reduced, or the reset noise in the correlated double sampling circuit 23 cannot be sufficiently removed.

For example, if the rise of the sampling pulse signal XShp for sampling and holding the feedthrough level is applied to the signal level portion SL and the signal level is sampled and held due to the variation in the phase of the output signal S, sampling is performed. The held signal component is treated as a reset noise component, and the signal level of the output signal S is reduced accordingly.

Therefore, conventionally, for example, in order to set the sampling pulse signal XShp to the optimum phase, a phase compensating circuit constituted by a CMOS inverter array is incorporated in the timing pulse generating circuit 22, and the inverter array of this phase compensating circuit is incorporated. An example has been proposed in which phase compensation is performed by using group delay according to JP-A-1-181138.
No. 6).

[0009]

However, in this conventional phase compensating circuit, the wirings added to each inverter are made to have the same characteristics of the CMOSs forming the inverter rows and the same wiring length between the inverters. There is a process constraint that the capacity (which is one factor that determines the delay time) must be constant. That is, in this phase compensation circuit, manufacturing variations in CMOS and wiring formation are factors that reduce the accuracy of phase compensation.

Further, since the phase compensation is performed by the inverter array, when the optimum phase value is changed, it is necessary to correct the mask used for CMOS formation and a process period associated with the correction.

That is, the conventional phase control by the inverter train is determined by the program of the upper wiring portion (for example, selective contact between the first Al wiring layer and the second Al wiring layer). As described above, when the optimum phase value is changed, a process period of 2 to 3 weeks is required to correct / change the mask program of the wiring section, and the period (TAT) from order receipt to product delivery is very large. There was the inconvenience of becoming longer.

The present invention has been made in view of the above problems, and an object of the present invention is to form an L in CMOS formation or the like.
(EN) Provided is a phase compensation circuit that can control an output pulse signal to an optimum phase without being affected by variations in SI manufacturing, and that does not require a change in a mask program for a specification change of the optimum phase, a mask cost, and a process period. Especially.

[0013]

A phase compensation circuit of the present invention comprises a waveform shaping circuit 1 for blunting at least a rising portion of an input signal Pt waveform, a shaping signal St from the waveform shaping circuit 1 and a threshold voltage Vth. And a phase comparison for comparing the phase of the phase-compensated phase-shifted signal Po from the comparator 2 with the comparator 2 for phase-shifting the input signal Pt. Voltage control circuit 5 for controlling the level of the threshold voltage Vth by comparing the phase difference signal Px (Vx) from the phase comparator 3 with the control voltage Vc supplied from the outside. Is provided and configured.

The phase compensating circuit of the present invention further comprises a waveform shaping circuit 1 for blunting at least the rising portion of the input signal Pr waveform, and a shaping signal S from the waveform shaping circuit 1.
r is compared with the threshold voltage Vth to compare the input signal Pr
, A phase comparator 3 for comparing the phase of the phase-compensated phase-shifted signal Prr from the comparator 2 with the reference signal XShp subject to phase compensation, and the phase comparator 3 The phase difference signal Px (Vx) from the control signal Vc is compared with the control voltage Vc supplied from the outside to compare the threshold voltage Vt with the threshold voltage Vt.
The threshold voltage control circuit 5 for controlling the level of h and the phase shift signal Prr from the comparator 2 are supplied to one input terminal as a reset signal and the set signal Ps is supplied to the other input terminal. , And a flip-flop circuit FF that outputs a delay signal HD phase-compensated with respect to the reference signal XShp from the output terminal φout.

When the phase compensation circuit phase-compensates the sampling pulse signal XShp of the correlated double sampling circuit for the output signal S from the CCD solid-state image pickup device, the reference signal XShp is used as the sampling pulse of the correlated double sampling circuit. Signal and the delayed signal HD
Is a horizontal transfer pulse signal.

[0016]

According to the first configuration of the present invention described above, the input signal Pt is controlled by the external control voltage Vc based on the reference signal Pi, so that the phase of the reference signal Pi is compensated. The output signal Po can be easily obtained. In the case of this configuration, unlike the phase compensation by the inverter array, it is not affected by variations in the CMOS process and the like, and therefore the accuracy of the phase compensation is not reduced.

Further, when the specification is changed with respect to the optimum phase value, it is only necessary to change the control voltage Vc from the outside, and in the manufacturing process, as in the conventional case, the wiring program (between the wirings connecting the inverter rows is This eliminates the need to change the wiring pattern), and does not require a change in the mask program for changing the specification of the optimum phase, a mask cost, and a process period. Therefore, it is possible to efficiently reduce the period (TAT) from the order receipt to the product delivery.

Further, according to the second configuration of the present invention, the phase shift signal Prr from the comparator 2 is supplied to one input terminal as a reset signal and the set signal Ps is supplied to the other input terminal.
Is provided and a flip-flop circuit FF for outputting a phase-compensated delay signal HD to the reference signal Pi from the output terminal φout is provided, so that, for example, the reference signal XShp is a sampling pulse signal of the correlated double sampling circuit. The delay signal HD is used as a horizontal transfer pulse signal, and the present invention is applied to a sampling pulse signal X of a correlated double sampling circuit connected to a CCD solid-state image pickup device.
When Shp is applied to a phase compensation circuit for phase compensation, the sampling pulse signal XShp is applied to the horizontal transfer pulse signal H.
Phase compensation can be performed on D.

At this time, the sampling pulse signal XSh
When the specification is changed with respect to the optimum phase value of p, it is only necessary to change the external control voltage Vc, as in the first configuration of the present invention. This eliminates the need to change the wiring pattern for connecting the lines connecting the inverter rows, and does not require a mask program change for the optimum phase specification change, a mask cost, and a process period. Therefore, it is possible to efficiently reduce the period (TAT) from the order receipt to the product delivery.

[0020]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing the basic configuration of the phase compensation circuit according to the first embodiment.

This phase compensation circuit is turned on as shown in the figure.
A reference pulse signal P for phase compensation is applied to the force terminal φin.
i is supplied to the two input terminals of the reference pulse signal Pi.
Child φ ₁And φ₂Timing pulse signal Pt supplied to
And a phase shift process based on the control voltage Vc and output terminal
Obtain the phase-compensated output pulse signal Po from φout
Is configured.

That is, this phase compensation circuit has an input terminal φ ₁
Of the waveform of the input timing pulse signal Pt supplied to the input timing pulse signal Pt, the rising portion and the falling portion thereof are blunted and output as a shaping signal St. And a comparator 2 for comparing the shaping signal St from the LPF 1 with the threshold voltage Vth to perform a phase shift process on the input timing pulse signal Pt and outputting it as an output pulse signal Po, and a reference supplied to the input terminal φin. Pulse signal Pi
And the phase comparator 3 which compares the phase of the phase-compensated output pulse signal Po from the comparator 2 and outputs the phase difference signal Px.
And a low-pass filter (hereinafter simply referred to as LPF) 4 that converts the phase difference signal Px from the phase comparator 3 into a voltage.
And a threshold voltage control circuit 5 for controlling the level of the threshold voltage Vth by comparing the voltage signal Vx from the LPF 4 with a control voltage Vc supplied from the outside.

Next, the signal processing operation of this phase compensation circuit will be described with reference to FIG.

First, the input timing pulse signal Pt supplied to the input terminal φ ₁ is, as shown in FIG.
A shaped signal St having a substantially isosceles trapezoidal waveform whose rising and falling portions are blunted by PF1
And is supplied to the comparator 2 in the next stage.

In the comparator 2, the shaping signal St supplied to one input terminal is compared with the threshold voltage Vth from the threshold voltage control circuit 5 supplied to the other input terminal, A range having a value larger than the threshold voltage Vth outputs the output pulse signal Po having the pulse width Tp.

At this time, since the shaping signal St is shaped into a substantially isosceles trapezoidal waveform by the LPF ₁ , the delay time τ ₁ from the rise of the shaping signal St to the rise of the output pulse signal Po and the shaping signal The delay time τ ₂ from the falling edge to the falling edge of the output pulse signal is
When the threshold voltage Vth changes by the level of the threshold voltage Vth and the level of the threshold voltage Vth becomes 1/2 of the level of the shaping signal, the delay times τ ₁ and τ ₂ become the same (τ ₁
= Τ ₂ ). That is, from the comparator 2, the rise time is τ
_The output pulse signal Po delayed by _one (that is, phase-shifted) is output.

Next, the phase comparator 3 detects how much phase difference the output pulse signal Po subjected to the phase shift processing by the comparator 2 has with respect to the reference pulse signal Pi. The pulse signal Px from the phase comparator 3 indicates the phase difference between the output pulse signal Po and the reference pulse signal Pi, and this pulse signal Px is converted into the voltage signal Vx by the LPF 4 in the next stage.

Then, in the next threshold voltage control circuit 5, the voltage signal (indicating the phase difference) Vx from the LPF 4 is compared with the control voltage Vc from the outside, and the threshold voltage applied to the comparator 2 is compared. Control Vth. By controlling the threshold voltage Vth, the delay times τ ₁ and τ ₂ of the output pulse signal Po are changed to optimally compensate the phase of the reference pulse signal Pi.

According to the first embodiment, the input timing pulse signal Pt is controlled by the external control voltage Vc based on the reference pulse signal Pi, so that the phase of the reference pulse signal Pi is compensated. The output pulse signal Po can be easily obtained. In the case of this configuration, unlike the phase compensation by the inverter array, it is not affected by variations in the CMOS process and the like, and therefore the accuracy of the phase compensation is not reduced.

Further, when the specification is changed with respect to the optimum phase value, it is only necessary to change the control voltage Vc from the outside, and in the conventional manufacturing process, the wiring program (between the wirings connecting the inverter rows is changed). This eliminates the need to change the wiring pattern), and does not require a change in the mask program for changing the specification of the optimum phase, a mask cost, and a process period. Therefore, it is possible to efficiently reduce the period (TAT) from the order receipt to the product delivery.

Next, a second embodiment in which this phase compensating circuit is applied in the case of compensating the phase of the sampling pulse signal of the correlated double sampling circuit connected to the CCD solid-state image pickup device will be described with reference to FIGS. 3 and 4. explain. In the second embodiment, as the sampling pulse signal, for example, as shown in FIG. 4, of the output signals S from the CCD solid-state image sensor, the sampling pulse signal XShp for sampling and holding the feed-through section FT is applied. Indicates. Incidentally, in FIG. 3, the same symbols are given to those corresponding to those in FIG.

This phase compensation circuit, as shown in FIG.
Of the waveform of the reset signal Pr supplied to the input terminal φ ₁ , the rising and falling portions of the waveform are blunted and output as a shaping signal Sr (eg, a first-order lag low-pass filter or a Gaussian filter). )
1, the shaping signal Sr from the LPF 1 and the threshold voltage V
and a sampling pulse signal XShp that is supplied to the input terminal φin and a comparator 2 that performs a phase shift process on the reset signal Pr by comparing it with th and outputs it as a delayed reset signal Prr.
And a phase comparator 3 that outputs the phase difference signal Px by comparing the phases of the delayed reset signal Prr from the comparator 2 and an LPF that converts the phase difference signal Px from the phase comparator 3 into a voltage.
4 and the voltage signal Vx from the LPF 4 and the control voltage Vc supplied from the outside are compared, and the threshold voltage Vth
It has a threshold voltage control circuit 5 for controlling the level.

Furthermore, in the second embodiment, a 2-input 1-output flip-flop circuit FF composed of, for example, two NAND circuits N ₁ and N ₂ is connected to the subsequent stage of the comparator 2. This flip-flop circuit FF
The delayed reset signal Prr from the comparator 2 is supplied to one of the input terminals, and the set signal P is supplied to the other input terminal.
s is supplied. Then, the horizontal transfer pulse signal HD whose phase is compensated for the sampling pulse signal XShp is output from the output terminal φout.

Next, the signal processing operation of this phase compensation circuit will be described with reference to FIG.

First, as shown in FIG. 4, the reset signal Pr supplied to the input terminal φ ₁ has its pulse width T
r has a length corresponding to three pulse widths t of the master clock signal Mc having a frequency of 8f _SC , and its rest width T
A pulse signal in which n has a length corresponding to one pulse width t of the master clock signal Mc is used.

In the illustrated example, the output timing is such that the master clock signal Mc rises at the falling times t ₁ and t ₅ and falls at the rising times t ₄ and t ₈ 1.5 cycles after the falling of the master clock signal Mc. Have.

On the other hand, the set signal Ps has the same pulse width Ts and rest width Tm as the reset signal Pr, and the master clock signal Mc rather than the reset signal Pr.
A pulse signal having a phase advanced by 1 pulse width t is used.

The reset signal Pr supplied to the input terminal φ ₁ has its rising and falling portions blunted by the LPF ₁ in the next stage, and the shaping signal Sr having a substantially isosceles trapezoidal waveform. And is supplied to the comparator 2 in the next stage.

In the comparator 2, the shaping signal Sr supplied to one input terminal is compared with the threshold voltage Vth from the threshold voltage control circuit 5 supplied to the other input terminal, A range having a value larger than the threshold voltage Vth is set as the pulse width Trr and the delayed reset signal Prr delayed by the time τ ₁ is output. At this time, the fall of the delayed reset signal Prr is caused by the reset signal Pr.
It is delayed by time τ ₂ from the fall of.

Next, the delayed reset signal P from the comparator 2
The phase comparator 3 detects the phase difference of rr with respect to the sampling pulse signal XShp. The pulse signal Px from the phase comparator 3 indicates the phase difference between the delay reset signal Prr and the sampling pulse signal XShp, and the phase difference signal Px is converted into the voltage signal Vx by the LPF 4 in the next stage.

In the next threshold voltage control circuit 5, LPF4
A voltage signal Vx (indicating a phase difference) Vx is compared with a control voltage Vc from the outside to control the threshold voltage Vth applied to the comparator 2. By controlling the threshold voltage Vth, the delay times τ ₁ and τ _{2 of the} delay reset signal Prr are controlled.
Can be changed.

Then, the delayed reset signal Prr delayed by a predetermined time based on the threshold voltage Vth controlled by the external control voltage Vc is supplied to one input terminal of the flip-flop circuit FF in the subsequent stage. The set signal Ps is applied to the other input terminal of the flip-flop circuit FF.
Is supplied, the flip-flop circuit FF
A pulse signal HD which rises at the fall of the set signal Ps and falls at the next fall of the delayed reset signal Prr is output from the output terminal φout of the.

In the illustrated example, the set signal Ps rises at the rising times t ₂ and t ₆ , and the delayed reset signal P
The pulse signal HD falls at the falling edges (t ₂ + τ ₂ ) and (t ₆ + τ ₂ ) of rr. By using the pulse signal HD from this output terminal as the horizontal transfer pulse signal, the CCD solid-state image pickup device outputs the output signal S delayed by the time τ ₂ from the feedthrough portion FT.

This means that the sampling pulse signal XS
Since hp is phase-compensated with respect to the horizontal transfer pulse signal HD for a time τ ₂ , it is possible to surely avoid the inconvenience of sampling and holding the signal level portion SL of the output signal S by the sampling pulse signal XShp. In FIG. 4, RG represents a pulse signal for resetting electric charge.

According to the second embodiment, in the subsequent stage of the comparator 2, the delayed reset signal Prr from the comparator 2 is supplied to one input terminal and the set signal Ps is supplied to the other input terminal.
Is provided and a flip-flop circuit FF for outputting the phase-compensated horizontal transfer pulse signal HD to the sampling pulse signal XShp from the output terminal φout is provided. Therefore, the sampling pulse signal XShp is converted into the horizontal transfer pulse signal HD. On the other hand, the phase can be easily compensated.

At this time, the sampling pulse signal XSh
When the specification is changed with respect to the optimum phase value of p, it is only necessary to change the external control voltage Vc as in the first embodiment. This eliminates the need to change the wiring pattern for connecting the wirings), and does not require a change in the mask program for changing the specification of the optimum phase, a cost for masking, and a process period. Therefore, it is possible to efficiently reduce the period (TAT) from the order receipt to the product delivery.

[0047]

According to the phase compensation circuit of the present invention, C
The output pulse signal can be controlled to the optimum phase without being affected by variations in LSI manufacturing such as MOS formation, and the mask program can be changed to change the specification of the optimum phase.
No need for mask costs and process time,
It is possible to efficiently reduce the period (TAT) from receiving an order to delivering a product.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase compensation circuit according to a first embodiment.

FIG. 2 is a waveform diagram showing signal processing of the phase compensation circuit according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a phase compensation circuit according to a second embodiment.

FIG. 4 is a waveform diagram showing signal processing of the phase compensation circuit according to the second embodiment.

FIG. 5 is a block diagram showing a general configuration of a CCD solid-state imaging device.

FIG. 6 is a waveform diagram showing signal processing of the CCD solid-state imaging device.

[Explanation of symbols]

 1 LPF 2 comparator 3 phase comparator 4 LPF 5 threshold voltage control circuit FF flip-flop circuit

Claims (3)

[Claims] 1. A waveform shaping circuit for blunting at least a rising portion of an input signal waveform, and a comparator for comparing the shaped signal from the waveform shaping circuit with a threshold voltage to perform a phase shift process on the input signal. A phase comparator that compares the phase of the phase-compensated reference signal with the phase of the phase-compensated output signal from the comparator, and a phase difference signal from the phase comparator and a control voltage supplied from the outside. And a threshold voltage control circuit for controlling the level of the threshold voltage. 2. A waveform shaping circuit for blunting at least a rising portion of an input signal waveform, and a comparator for comparing the shaped signal from the waveform shaping circuit with a threshold voltage to perform a phase shift process on the input signal. A phase comparator that compares the phase of the phase-compensated reference signal with the phase of the phase-compensated output signal from the comparator, and a phase difference signal from the phase comparator and a control voltage supplied from the outside. And a threshold voltage control circuit for controlling the level of the threshold voltage, and an output signal from the comparator is supplied as a reset signal to one input terminal and a set signal is supplied to the other input terminal. And a flip-flop circuit that outputs a delayed signal whose phase is compensated for the reference signal from the output terminal. 3. The reference signal is a sampling pulse signal of a correlated double sampling circuit incorporated in a CCD solid-state image pickup device, and the delay signal is a horizontal transfer pulse signal of the CCD solid-state image pickup device. The phase compensation circuit according to claim 2.