JP2005236853A - Image scanner and image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct linearity deviation and density deviation in a CCD output stage by two or more channels of a 4-channel output CCD. <P>SOLUTION: Photoelectric conversion signals of two or more photoelectric conversion elements arranged in a strait line state, are respectively output as outputs OS1, OS2 by shift registers and output buffers for every odd-numbered elements and even-numbered elements of one side dividing the photoelectric conversion element arrangement in the center part, and respectively output as outputs OS3, OS4 by shift registers and output buffers for every odd-numbered elements and even-numbered elements of another side. The outputs are made by an output gate signal ϕ2B supplied to output gates of every shift registers, and the output OS can be changed by changing a falling slope of the signal. Therefore, the falling slope of the output gate signal ϕ2B created by a timing generating circuit 21, is changed by filter circuits 23, 25 of variable register types, and output OS are separately changed and output. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention provides an image reading apparatus that outputs an image signal photoelectrically converted by a linear image sensor such as a CCD for each of the left and right pixel arrays in the center of the pixel array of the linear image sensor, and multiplexes the output image signals. The present invention relates to an image processing apparatus such as a scanner apparatus having a reading apparatus, an electrophotographic copying machine, and a facsimile apparatus.

  A scanner device used in a digital copying machine or the like reads an image by photoelectrically converting an original image by a linear image sensor such as a CCD. CCDs are widely used because they are capable of high resolution and high-speed reading, but further speeding-up is required as digital copying machines become widespread. In order to cope with this increase in speed, a system has been developed that processes the CCD image charges in four channels for each even-numbered pixel and odd-numbered pixel on the left side of the center of the CCD pixel array and for each even-numbered pixel and odd-numbered pixel on the right side. .

FIG. 15 is a diagram showing the configuration of an image data processing system in a conventional 4-channel output CCD. In FIG. 15, 120 is a 4-channel output CCD system, 130 is a preprocessing system, and 140 is a scanner control system.
Although not shown, the 4-channel output CCD system 120 includes a CCD, a shift register, and an output buffer, each of which is composed of a plurality of light receiving elements (photodiodes) arranged in order. In the case of a 4-channel output CCD, there are four shift registers in order to divide the even and odd components into left and right at the center of the array of light receiving elements to obtain four outputs. Therefore, the first shift register sequentially transfers and outputs the signal from the leftmost light receiving element of the odd component, and the second shift register sequentially transfers and outputs the signal from the even light component of the leftmost light receiving element. The register sequentially transfers and outputs the signals from the light receiving element at the right end of the odd component, and the fourth shift register sequentially transfers and outputs the signals from the light receiving element at the right end of the even component.

  The analog signal output from the 4-channel output CCD system 120 is sampled and amplified for each pixel signal by the amplifiers 131 and 132 of the preprocessing system 130. The amplifiers 131 and 132 are amplifiers that can process two channels in parallel on a single chip. The amplifier 131 receives two left and right channels (output terminals 0S1, OS3) of the odd component of the pixel signal of the 4-channel output CCD system 120, and the amplifier 132 receives the even component of the pixel signal of the 4-channel output CCD system 120. Two left and right channels (output terminals OS2 and OS4) are input.

  In each of the amplifiers 131 and 132, the two-channel pixel signals from the left and right sides of the four-channel output CCD system 120 are processed in parallel (sampling and signal amplification), and then synthesized (multiplexed) into one channel. That is, the amplifier 131 synthesizes the left and right signals of the odd components into one channel, and the amplifier 132 synthesizes the left and right signals of the even components into one channel and outputs them from the amplifiers 131 and 132, respectively. Yes.

  The analog signals for each pixel amplified to an appropriate level in signal processing by these amplifiers 131 and 132 are AD converted by the AD converters 133 and 134 into digital signals. Since the resolution of the AD converters 133 and 134 used here is 8 bits (256 steps), the pixel data is 8 bits per pixel.

  It should be noted that control signals (sample hold pulse, composite signal, clamp signal) necessary for driving the registers, output buffers, and amplifiers 131 and 132 of the 4-channel output CCD system, and AD conversion processing in the AD converters 133 and 134 are used. The necessary AD conversion clock is supplied from the subsequent scanner control system 140.

  Although not shown in detail, the scanner control system 140 includes a bus width conversion circuit, a shading correction circuit, a bus selection circuit, a left / right correction circuit, a bit inversion circuit, and a raster conversion circuit. That is, the bus width conversion circuit divides the odd data and the even data into left data and right data. Therefore, for example, when the data rate of the image data is input from the preprocessing system 130 as 2 channels (odd channel and even channel) as 40 MHz per channel, the image data is output as 4 channels and 1 channel as the output after the bus width conversion processing. It is input to the next stage shading correction circuit in a state of being converted into 4 channels as 20 MHz.

  Shading correction is performed in the shading correction circuit. The image data subjected to the shading correction is input to the left / right correction circuit.

  Image information input to the 4-channel output CCD system as a light image signal is photoelectrically converted for each of a plurality of light receiving elements. At this time, each light receiving element receives a light image signal having the same density of the reflectance of the original, Even if the same level of charge signal is converted and output, the signal processing system is divided into four parts, and therefore, a circuit characteristic deviation, more specifically, a linearity deviation that occurs between signal transmission paths occurs. Distortion occurs between signals (image data). In order to correct this distortion, a left / right correction circuit is provided, and left / right correction is performed using a data conversion table using a memory.

  In addition to the linearity deviation, there are illuminance unevenness generated for each pixel of image data with respect to image density, sensitivity variation, and density gradient deviation (density deviation) due to dark current generated in the light receiving element and shift register. This density deviation can be corrected by the shading correction circuit, but it is difficult to correct in the intermediate gradation region. In the conventionally proposed solution, a gray scale chart is provided at the reading position in the main scanning or sub scanning direction. A method is used in which correction is performed by referring to a gamma correction table based on the read data of each step.

  The image data subjected to such correction is then bit-inverted by the bit inversion circuit, and the rasterizing circuit performs an alignment process of the image data arrangement order.

  Then, filtering processing, range correction, magnification conversion, gamma correction, gradation processing, and the like are performed by the next stage image processing system (not shown) (see Patent Document 1).

JP 2000-188686 A

  As described above, in the conventional 4-channel output CCD image data processing system, the left / right correction, which is the correction of the linearity deviation of the channel, is amplified by the amplifiers 131 and 132 and the AD converters 133 and 134 are amplified. This is performed on the image data after AD conversion. That is, the image data is input to the memory address, and the corrected image data is corrected in the left-right direction by outputting the data set in advance for each address of the memory instead of the data output of the memory. ing. Accordingly, image data processing is complicated, such as mounting a dedicated memory and a peripheral circuit for the processing. The correction of the density deviation is also performed on the image data after AD conversion, but the circuit configuration is inevitably complicated.

  Accordingly, the present invention has been made in view of such a situation, and an object of the present invention is to correct a linearity deviation due to a plurality of channels and output a density deviation in a 4-channel output CCD system at the time of output of a photoelectric conversion signal from the CCD. It is to correct.

According to the first aspect of the present invention, photoelectric conversion signals of a plurality of photoelectric conversion elements arranged in a straight line are output for each odd-numbered element and even-numbered element on one side obtained by dividing the photoelectric conversion element array at the center. In the image reading apparatus including the first output means and the second output means for outputting the odd-numbered elements and the even-numbered elements on the other side, the movement start time of the photoelectric conversion signal moving between the photoelectric conversion elements The image reading apparatus is characterized in that means for controlling is provided in both or either one of the first output means and the second output means.
According to a second aspect of the present invention, there is provided the image reading apparatus according to the first aspect, wherein the document having the standard density is read at different movement start times, and the read output values of the photoelectric conversion elements on the one side and the other side are acquired. An image reading apparatus comprising: means for setting a movement start time based on the acquired read output value.
According to a third aspect of the present invention, in the image reading apparatus according to the second aspect, the means for setting the movement start time based on the acquired read output value is the read output of the photoelectric conversion elements on the one side and the other side. An image reading apparatus is characterized in that a movement start time having a common value is set.
A fourth aspect of the present invention is an image processing apparatus comprising the image reading apparatus according to any one of the first to third aspects.

  According to the present invention, in a 4-channel output CCD system, it is possible to correct a linearity deviation due to a plurality of channels and to correct a density deviation at the time of output of a photoelectric conversion signal from the CCD. Therefore, it is not necessary to provide a correction circuit for linearity deviation or density deviation having a memory in the subsequent stage, and the circuit configuration of the image reading apparatus is simplified.

First, correction of linearity deviation in an image reading apparatus having a 4-channel output CCD system according to an embodiment of the present invention will be described.
FIG. 1 is a block diagram of a 4-channel output CCD apparatus in which the present invention is implemented. Although not shown, this 4-channel output CCD device photoelectrically converts reflected light from a document in a scanner unit such as a digital copying machine.
In FIG. 1, 5 is a plurality of photoelectric conversion elements (photodiodes) arranged in a straight line in order, and 1 is an analog that transfers and moves the signal output of the odd-numbered elements on the left side obtained by dividing the photoelectric conversion element 5 at the center. The shift register 2 is an analog shift register that transfers and moves the signal output of the even-numbered elements on the left side of the central part of the photoelectric conversion element 5, and 3 is the transfer-transfer of the signal output of the odd-numbered elements on the right side of the central part of the photoelectric conversion element 5 4 is an analog shift register for transferring and moving the signal output of even-numbered elements on the right side of the center of the photoelectric conversion element 5, 6 is an output gate terminal of the left shift registers 1 and 2, and 7 is a right shift register. 3 and 4 output gate terminals, 8 is an output buffer of the analog shift register 1, and 9 is an output buffer of the analog shift register 2. §, the output buffer of the analog shift register 3 10, 11 is an output buffer of the analog shift register 4. The output buffer 8 is an output terminal OS1 of the left odd component of the photoelectric conversion element 5, the output buffer 9 is an output terminal OS2 of the left even component of the photoelectric conversion element 5, and the output buffer 10 is an output terminal of the right odd component of the photoelectric conversion element 5. The OS3 and the output buffer 11 have an even-numbered right-side output terminal OS4 of the photoelectric conversion element 5. RS is a reset pulse input terminal and CP is an input terminal of a clamp pulse. These are formed on a single substrate as a CCD device.

  For driving the CCD, a signal is generated by a dedicated timing generation circuit to be described later, and the signal is supplied to the left and right output gate terminals 6 and 7 by two drivers. Then, a photoelectric output signal is taken out from the CCD by this timing signal.

FIG. 2 is a diagram showing the movement of the charge signal generated by the CCD. Referring to FIG. 2, the state of the shift will be described. The state of T11 is a state in which the movement of the charge signal is stable as a result of the previous movement (shift) operation, and the state of T12 is adjacent to the state of T11. This is a state where the movement of the charge signal to the register is started, and the state of T13 indicates a state where the movement is finished. This shift is performed sequentially by repeating high (H) and low (L) clocks φ1 and φ2 in the register of the analog shift register. Finally, the output gate signal φ2B is sent to the output gates 6 and 7. Is supplied, the charge signal is converted into an output signal (voltage) OS via the output buffer and output to the outside of the CCD.

FIG. 3 is a diagram illustrating the relationship between the output gate signal and the output signal.
In FIG. 3, when the output signal φ2B is supplied to the output gates 6 and 7, the charge signal of the shift register appears as a voltage signal from the output buffer by the fall of the signal φ2B. Here, the time from the timing of 10% until the output gate signal φ2B falls to the timing of 10% before the CCD output voltage signal OS is stabilized is referred to as an output delay time. When the output gate signal and the output voltage signal have an output delay time as described above, the voltage signal D is generally stabilized as shown in the relationship diagram between the output voltage signal and the output timing in FIG. The signal is sampled by the sampling signal SHD in the time zone (region) d1 and is output as a voltage signal (FIG. 4A). If the sampling signal SHD is advanced in order to perform high-speed reading, it cannot be output in the stable region d1 (FIG. 4B). This relationship will be further described with reference to FIG.

  FIG. 5 is a diagram illustrating the relationship between the output gate signal and the output timing of the output voltage signal. In FIG. 5, when the falling slope of the output gate signal φ2B is changed to a, b, c, the timing at which the charge starts to move changes. As a result, the voltage signal output from the output buffer changes like OSa, OSb, OSc. At this time, the output delay time is T21 for the output gate signal of slope a, T22 for the output gate signal of slope b, and T23 for the output gate signal of slope c. T21 <T22 <T23 depending on the characteristics of the output buffer. When the voltage signals OSa, OSb, OSc are sampled using the falling point of the predetermined sampling signal SHD as a sampling point, the voltage signal OSa can be output in a stable region, and the voltage signal OSb is slightly out of the stable region. In OSc, the signal is output at a point completely deviating from the stable region. That is, the voltage signal output due to this deviation decreases.

In this embodiment, the decrease in the output voltage signal due to the output delay time is used for correcting the linearity deviation.
FIG. 6 is an overall block diagram of a 4-channel output CCD system according to an embodiment of the present invention, in which 20 is the 4-channel output CCD device described in FIG. 1 and 21 is the 4-channel output CCD device 20. Timing generating circuit for generating the output gate signal φ2B, 22 and 23 are driver circuits for driving the output gate signal φ2B with an amplitude of 0 to 5V, and 24 and 25 are the falling slopes of the output gate signal φ2B. It is a filter circuit to control. Detailed circuits of the filter circuits 24 and 25 will be further described with reference to FIGS.

FIG. 7 is a configuration diagram of a filter circuit that controls the falling slope of the output gate signal, and FIG. 8 is a characteristic diagram of enhancement-type FETs and varicap diodes used in the filter circuit.
In FIG. 7, the filter circuit 24 is composed of an enhancement type FET 24a, the output of the driver 22 (output gate signal φ2B) is supplied to the source S, and the control signal analog-converted by the DA converter is applied to the gate G. The enhancement type FET 24a is used as a variable resistor by utilizing the characteristic that the drain current easily flows when the voltage between the gate G and the source S increases as shown in FIG.

  When the output of the DA converter 27 is set to 0V, the signal from the driver 22 is applied to the source S, so the voltage between the gate G and the source S becomes 0V or negative, and the FET 24a is turned off. Therefore, the combined resistance value of the FET 24a becomes the resistance value of the resistor R11 and constitutes a filter together with the capacitor C11. At this time, the time constant is maximized and the falling of the waveform becomes dull.

  Conversely, when the output voltage of the DA converter 27 is set to around 5V, the signal of the driver 22 is applied to the source S, so the voltage between the gate G and the source S is determined by the driver signal, and when the signal level is high, the FET 24a is turned on. When the resistance is large and the signal level is low, the voltage between the gate G and the source S increases and the on-resistance of the FET 24a decreases. When the on-resistance decreases, the combined resistance value of the on-resistance and resistors R11 and R12 decreases, and the combined resistance value and the capacitor C11 constitute a filter. At this time, the time constant is minimized, and the waveform falls sharply. The resistor R12 is attached for limiting the minimum resistance value, and the resistor R11> the resistor R12. Therefore, by changing the output of the DA converter 27, the time constant of the filter circuit can be made variable, so that the falling slope of the output gate signal φ2B can be controlled.

  As another method for controlling the falling slope of the output gate signal φ2B, an RC filter may be constituted by a general-purpose electronic volume and a capacitor, and the resistor is a fixed resistor, and a varicap (variable capacitor diode that can change the capacitance). ) To set the reverse voltage as a control signal, the capacitance changes (FIG. 8B), so that the time constant can be changed.

  The above description is about the filter circuit 24, but the same applies to the filter circuit 25.

  With the configuration of the above-described 4-channel output CCD system, the falling slope of the output gate signal φ2B can be controlled, so that the output voltages OSa, OSb, OSc of the 4-channel output CCD system can be controlled. That is, since the voltage can be controlled at the output stage from the 4-channel output CCD system, the linearity deviation generated between the signal transmission paths can be corrected in advance, that is, at the output stage of the CCD device. In this embodiment, the filter circuit is configured to control the outputs of both the left and right elements of the photoelectric conversion element 5. However, if one of the elements is used as a reference, only the other output is controlled. You may comprise as follows.

Further, in order to cope with color originals, the 4-channel output CCD device shown in FIG. 1 is configured as a 4-channel output CCD device having RGB filters, which are used to control the falling slope of the output gate signal φ2B. A filter circuit is attached. The output gate signal φ2B is generated as one signal by the timing generation circuit, and is supplied to the six filter circuits via the six driver circuits. Also in this case, the enhancement type FET 24a is used to control the falling slope.
FIG. 9 shows a color 4-channel output CCD device, and FIG. 10 shows a configuration diagram of a color 4-channel output CCD system. Three four-channel output CCD devices and four-channel output CCD systems are used for R, G, and B, respectively.

Next, correction of density deviation in the 4-channel output CCD system according to this embodiment will be described.
In the 4-channel output CCD system (FIG. 6), the control signals of the filter circuits 24 and 25 are temporarily set to a certain value, for example, a value that corrects the linearity deviation, and a gray chart having different multi-stage densities in the sub-scanning direction is read. To obtain the read output value.

FIG. 11 is a diagram illustrating a result of reading by the left and right photoelectric conversion elements, where the horizontal axis represents the amount of incident light to the 4-channel output CCD device, and the vertical axis represents the read output value. As shown in FIG. 11, even when the same original is read by the left and right photoelectric conversion elements, the read output values are different. Therefore, when the gray chart is read, the read output value of each stage of the gray chart, the reflectance calculated from the density of each stage of the gray chart, and the first stage of the gray chart are normalized by the output value 240 digit, and each reflectance is normalized. A density curve a connecting the read output values is obtained. Here, the straight line connecting the normalized reflectance of the first stage and the reflectance of 0% is defined as an ideal density line b, and the difference between the density line b and the density curve a at a certain halftone, for example, the reflectance of 50%, is defined as the straight line. Data is generated as the density difference c.
FIG. 12 is a diagram showing the density difference, where the horizontal axis represents the reflectance, the vertical axis represents the read output value, and the difference in the halftone between the density line b and the density curve a is the density difference c. This density difference is obtained in the left and right photoelectric conversion elements.

The operation for obtaining the density difference is performed by varying a plurality of the control signals, and is performed for the left and right photoelectric conversion elements.
FIG. 13 is a diagram showing the density difference obtained by changing the control signal, where the horizontal axis represents the reflectance and the vertical axis represents the read output value. When the control signal for the left photoelectric conversion element is changed as S1, S2, and S3, the read output values A1, A2, and A3 are obtained. The same operation is performed for the right photoelectric conversion element. Then, a relational expression is obtained from density difference data for each value of the control signal, and stored in a memory of a scanner unit (not shown).

Further, the maximum value (max value) and the minimum value (min value) of the density difference are obtained for each of the left and right photoelectric conversion elements, and are similarly stored in the memory. Then, the CPU calculates a common density difference region between the left and right photoelectric conversion elements from the max and min values of the left and right photoelectric conversion elements, and determines a value corresponding to the center value as a set value of the control signal.
FIG. 14 is a diagram illustrating a region of density difference common to the left and right photoelectric conversion elements, in which the horizontal axis represents the set value of the control signal and the vertical axis represents the density difference. In FIG. 14, the density difference areas Y1 to Y2 are common density difference areas, and the set value of the control signal is determined in this area (X1 to X2). Up to now, the setting value has been tentatively determined as the setting value for correcting the linearity deviation. However, by selecting the setting value closest to the setting value temporarily determined in the area, the linearity deviation is corrected and the density difference is corrected. It is possible to set a setting value for correcting.

  As described above, the image reading apparatus according to the present invention is useful as an image reading apparatus that simplifies the circuit configuration, and is suitable for use in a sheet through and flat bed scanner, a digital copying machine, a facsimile machine, and the like.

1 is a configuration diagram of a 4-channel output CCD device in which the present invention is implemented. FIG. It is a figure which shows the form of the movement of the electric charge signal produced | generated by CCD. It is a figure which shows the relationship between an output gate signal and an output signal. It is a figure which shows the relationship between an output voltage signal and output timing. It is a figure which shows the relationship between the output timing of an output gate signal and an output voltage signal. 1 is an overall block configuration diagram of a 4-channel output CCD system according to an embodiment of the present invention. FIG. It is a block diagram of the filter circuit which controls the falling inclination of an output gate signal. It is a characteristic view of the enhancement type FET and varicap diode used in the filter circuit. It is a figure which shows the 4-channel output CCD apparatus for colors. It is a figure which shows the block diagram of the 4-channel output CCD system for colors. It is a figure which shows the reading result by the left and right photoelectric conversion elements. It is a figure which shows the reading density difference by a photoelectric conversion element. It is a figure which shows the density | concentration difference acquired by changing a control signal. It is a figure which shows the area | region of the density | concentration difference common with a photoelectric conversion element on either side. It is a figure which shows the structure of the conventional 4-channel output CCD system.

Explanation of symbols

  1 .. Left odd component analog shift register 2.. Left even component analog shift register 3.. Right odd component analog shift register 4.. Right even component analog shift register 5. Left output gate terminal, 7. Right output gate terminal, 8. Left odd component output buffer, 9. Left even component output buffer, 10. Right odd component output buffer, 11. Right even component output buffer .

Claims (4)

First output means for outputting photoelectric conversion signals of a plurality of photoelectric conversion elements arranged in a straight line for each odd-numbered element and even-numbered element on one side obtained by dividing the photoelectric conversion element array at a central portion; In the image reading apparatus provided with the second output means for outputting every odd-numbered element and even-numbered element on the other side,
An image reading apparatus characterized in that means for controlling the movement start time of a photoelectric conversion signal moving between the photoelectric conversion elements is provided in both or either one of the first output means and the second output means. . The image reading apparatus according to claim 1.
Means for reading a document having a standard density at different movement start times and acquiring read output values of the photoelectric conversion elements on the one side and the other side;
Means for setting the movement start time based on the acquired read output value;
An image reading apparatus comprising: The image reading apparatus according to claim 2.
The means for setting the movement start time based on the acquired read output value sets the movement start time in which the read output values of the photoelectric conversion elements on the one side and the other side are common. apparatus. An image processing apparatus comprising the image reading apparatus according to claim 1.

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