JPH0590946A - Input level shift circuit - Google Patents

Abstract

PURPOSE:To reduce a current of a power supply by adopting the configuration such that other MOS transistor(TR) responds to OFF-ON in response to the ON-OFF operation of uni-lateral type MOS TR. CONSTITUTION:With a P-channel MOS TR 1 turned on, an N-channel MOS TR 5 is turned on in response to its source potential and then an N-channel MOS TR 4 is turned off. In this case, as the resistance of a resistor 3 is larger, the OFF operation of the N-channel MOS TR 4 is slower, the rise of the output is faster, and with the P-channel MOS TR 1 is turned off conversely, the N- channel MOS TR 4 is pulled up by the resistor 3 and turned on. In this case, as the resistance of the resistor 3 is larger, the ON operation of the N-channel MOS TR 4 is slow, but the fall of the output signal is not slow because if the resistor 12 exists. Thus, the resistor 3 is set larger to suppress power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSIC input circuit, and more particularly to an input circuit configuration having an input level shift function.

[0002]

2. Description of the Related Art Conventionally, in this type of input level shift circuit, as shown in FIG. 3, a P-type MOS transistor 1 and a resistor 2 are connected in series so as to be applied to the gate of a P-type MOS transistor 1, for example. A signal swinging from 0 to 5 (V) can be converted into a signal swinging from -10 to 5 (V) and taken out to the output terminal V0.

[0003]

In the conventional input level shift circuit described above, when a signal for turning on the P-type MOS transistor 1 is input, the P-type MOS is provided between the power supplies.
A current determined by the transistor 1 and the resistor 2 flows. If the resistance value at this time is too large, the speed at which the signal is transmitted to the next stage decreases, so it was necessary to select a small value.

Therefore, there is a drawback that the current consumption cannot be reduced.

[0005]

In the input level shift circuit of the present invention, a resistance and another conductivity type MOS transistor are arranged in series between one conductivity type MOS transistor for receiving an input signal and a power supply, and the one conductivity type MOS transistor is provided. ON of transistor
The other conductivity type MOS transistor is configured to respond to OFF-ON in response to the -OFF operation.

[0006]

According to the above structure, when one conductivity type MOS transistor is turned on, the other conductivity type MOS transistor is turned off, so that no current flows through the resistor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows an input level shift circuit according to an embodiment of the present invention. In the figure, 1 is a P-type MOS transistor, 12 and 3 are resistors, and 4 and 5 are N-type MOS transistors.
It is a transistor.

Next, the operation of the above input level shift circuit will be described. When the P-type MOS transistor 1 is turned on, the N-type MOS transistor 5 is turned on according to the source potential
Is turned on, and the N-type MOS transistor 4 is turned on.
FF. Here, the larger the resistance value of the resistor 3, the N-type MO
The OFF operation of the S-transistor 4 is fast, so that the output rises quickly. On the contrary, when the P-type MOS transistor 1 is turned off, the N-type MOS transistor 4 is pulled up by the resistor 3 and turned on. Here, the larger the resistance value of the resistor 3 is, the slower the ON operation of the N-type MOS transistor 4 is.

However, because of the resistor 12, the fall of the output signal does not slow down.

Therefore, the resistor 3 can have a large value, and the power consumption can be suppressed.

[0012]

Second Embodiment FIG. 2 shows an input level shift circuit according to the second embodiment of the present invention. In this embodiment, the first embodiment is 0
While this is a circuit that level-shifts a signal swinging to -5 (V) to -10 to 5 (V) to the negative potential side, this embodiment can level-shift to the positive potential side and consumes power. Has the advantage of being small. As for the structure, the conductivity type of the transistor is reversed and the power supply connection is reversed, so the description is omitted.

[0013]

As described above, the present invention responds to the ON-OFF timing of the one conductivity type MOS transistor which receives the input signal of the input level shift circuit, and the OFF-type.
By arranging the other conductivity type MOS transistors that are turned on in series, the power supply current can be made extremely small.

[Brief description of drawings]

FIG. 1 is an input level shift circuit diagram of a first embodiment of the present invention.

FIG. 2 is an input level shift circuit diagram of a second embodiment of the present invention.

FIG. 3 is a prior art input level shift circuit diagram.

[Explanation of symbols]

 1,9,10 P-type MOS transistor 3,7,8,12 Resistor 4,5,6 N-type MOS transistor

Claims (3)

[Claims] 1. A one conductivity type MOS for receiving an input signal between power supplies.
A transistor, a resistor and another conductivity type MOS transistor are arranged in series, and the drain electrode of the one conductivity type MOS transistor is used as an output terminal, and the other conductivity type MOS transistor is turned off in response to an ON-OFF operation of the one conductivity type MOS transistor. An input level shift circuit configured to respond to ON. 2. A P for receiving an input signal between the VDD and VSS power supplies.
-Type MOS transistor, resistor and N-type MOS transistor are connected in series so that the P-type MOS transistor is on the VDD power supply side, the drain electrode of the P-type MOS transistor is the output terminal, and the source of the P-type MOS transistor is The electrode is connected to the gate electrode of the MOS transistor via a second resistor, and the drain-source electrode of the second N-type MOS transistor is connected between the gate electrode of the N-type MOS transistor and the VSS power source. An input level shift circuit having a gate electrode connected to an output terminal. 3. A P-type MOS transistor, a resistor, and an N-type MOS transistor for receiving an input signal are connected in series between the VDD and VSS power supplies so that the N-type MOS transistor is on the VSS power supply side, and an N-type MOS transistor is connected. The drain electrode of the transistor is used as an output terminal, the source electrode of the N-type MOS transistor is connected to the gate electrode of the P-type MOS transistor through a second resistor, and the gate electrode of the P-type MOS transistor and the VDD electrode are connected to each other. An input level shift circuit in which a drain-source electrode of a second P-type MOS transistor is connected and a gate electrode thereof is connected to an output terminal.