JPH03191615A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH03191615A JPH03191615A JP1332096A JP33209689A JPH03191615A JP H03191615 A JPH03191615 A JP H03191615A JP 1332096 A JP1332096 A JP 1332096A JP 33209689 A JP33209689 A JP 33209689A JP H03191615 A JPH03191615 A JP H03191615A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- circuit
- electrode
- transistor
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 238000001514 detection method Methods 0.000 claims description 13
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路で実現される出力回路に関し、
特にレベル変換回路を含む出力回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output circuit realized by a semiconductor integrated circuit,
In particular, it relates to an output circuit including a level conversion circuit.
従来の出力回路について図面を参照して説明する。 A conventional output circuit will be explained with reference to the drawings.
第４図は従来の半導体集積回路で実現された出力回路の
一例を示す回路図である。FIG. 4 is a circuit diagram showing an example of an output circuit realized by a conventional semiconductor integrated circuit.
第４図に示すように従来の出力回路は入力端子１をＣＭ
ＯＳレベルＥＣＬレベル変換回路２の入力端３に接続し
、ＣＭＯＳレベルＥＣＬレベル変換回路２の出力端４を
ＮＰＮ型トランジスタ６のベース電極に接続し、ＮＰＮ
型トランジスタ６のコレクタ電極を正電源５に接続し、
ＮＰＮ型トランジスタ６のエミッタ電極を出力端子１０
と抵抗素子７ａの一端とに接続し、抵抗素子７ａの他端
を負電源９に接続して構成されていた。As shown in Figure 4, the conventional output circuit connects input terminal 1 to CM
The OS level is connected to the input terminal 3 of the ECL level conversion circuit 2, and the output terminal 4 of the CMOS level ECL level conversion circuit 2 is connected to the base electrode of the NPN type transistor 6.
Connect the collector electrode of the type transistor 6 to the positive power supply 5,
The emitter electrode of the NPN transistor 6 is connected to the output terminal 10.
and one end of the resistance element 7a, and the other end of the resistance element 7a was connected to the negative power supply 9.
第２図にＣＭＯＳレベルＥＣＬレベル変換回路２の一例
を示す、ＣＭＯＳレベルＥＣＬレベル変換回路２の動作
は、第２図が示すように正電源２５の電圧をＶＤＤ、負
電源３ｏの電圧を０、出力端子４のハイレベルとローレ
ベルの電位差をＶＳＢとすると、入力端子３の電圧が０
からＶＤＤに変化すると出力端４はＶＤＤから（ＶＤＤ
−ＶＳＢ）に変化し、入力端３の電圧がＶＤＤからＯに
変化すると出力端は（ＶＤＤ−ＶＳＢ）からＶＤＤに変
化するようになっている。An example of the CMOS level ECL level conversion circuit 2 is shown in FIG. 2.The operation of the CMOS level ECL level conversion circuit 2 is as shown in FIG. If the potential difference between the high level and low level of output terminal 4 is VSB, the voltage of input terminal 3 is 0.
When the voltage changes from VDD to VDD, the output terminal 4 changes from VDD to (VDD
-VSB), and when the voltage at the input terminal 3 changes from VDD to O, the output terminal changes from (VDD-VSB) to VDD.
上述の従来の出力回路は、出力端子１ｏの電位が立ち上
がる時は、ＮＰＮ型トランジスタ６のエミッタ電極から
出力端子１０に流れ込む電流によって負荷を駆動し、出
力端子１０の電位が立ち下がる時は、出力端子１０から
抵抗素子７ａに電流が流れることにより負荷に蓄積され
た電荷を放電するようになっていた。In the conventional output circuit described above, when the potential of the output terminal 1o rises, the load is driven by the current flowing from the emitter electrode of the NPN transistor 6 to the output terminal 10, and when the potential of the output terminal 10 falls, the output is A current flows from the terminal 10 to the resistive element 7a, thereby discharging the charge accumulated in the load.
上述した従来の出力回路は、高速動作をさせるために第
４図の中の抵抗素子７ａの抵抗値を小さくしなければな
らないので、定常電流が大きくなり消費電力が大きくな
るという欠点がある。The above-described conventional output circuit has the disadvantage that the resistance value of the resistor element 7a in FIG. 4 must be reduced in order to operate at high speed, resulting in an increase in steady current and an increase in power consumption.
本発明の出力回路は、入力信号用の入力端子を前記入力
信号が論理値で“Ｏｎから“１”に変化する時点から予
め設定した一定期間だけ“１″を出力してそれ以外は“
Ｏ”を出力する立ち上がり検出回路の入力端とレベル変
換回路の入力端とに接続し、前記レベル変換回路の逆相
出力端子をＮＰＮ型トランジスタのベース電極に接続し
、前記ＮＰＮ型トランジスタのコレクタ電極を正電源に
接続し、前記ＮＰＮ型トランジスタのエミッタ電極を出
力端子と抵抗素子の一方の端子とＮチャネル型ＭＯＳト
ランジスタのドレイン電極とに接続し、前記抵抗素子の
他方の端子と前記Ｎチャネル型ＭＯＳトランジスタのソ
ース電極とを負電源に接続し、前記立ち上がり検出回路
の出力端を前記Ｎチャネル型ＭＯＳトランジスタのゲー
ト電極に接続して成っている。The output circuit of the present invention has an input terminal for an input signal that outputs "1" for a predetermined period from the time when the input signal changes from "On" to "1" in logical value, and otherwise outputs "1".
The input terminal of a rise detection circuit that outputs "O" is connected to the input terminal of a level conversion circuit, the negative phase output terminal of the level conversion circuit is connected to the base electrode of an NPN type transistor, and the collector electrode of the NPN type transistor is connected to is connected to a positive power supply, the emitter electrode of the NPN type transistor is connected to an output terminal, one terminal of the resistor element, and the drain electrode of the N-channel type MOS transistor, and the other terminal of the resistor element is connected to the N-channel type MOS transistor. The source electrode of the MOS transistor is connected to a negative power supply, and the output end of the rise detection circuit is connected to the gate electrode of the N-channel type MOS transistor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の出力回路の一実施例を示す回路図、第
２図は第１図の中のＣＭＯＳレベルＥＣＬレベル変換回
路の一例を示す回路図、第３図は第１図の中の立ち上が
り検出回路の一例を示す回路図である。FIG. 1 is a circuit diagram showing an example of the output circuit of the present invention, FIG. 2 is a circuit diagram showing an example of the CMOS level ECL level conversion circuit in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the CMOS level ECL level conversion circuit in FIG. FIG. 2 is a circuit diagram showing an example of a rising edge detection circuit.
第１図において、本実施例の出力回路は、出力端子１を
立ち上がり検出回路１１の入力端１２とＣＭＯＳレベル
ＥＣＬレベル変換回路２の入力端３に接続し、ＣＭＯＳ
レベルＥＣＬレベル変換回路２の逆相出力端４をＮＰＮ
型トランジスタ６のベース電極に接続し、ＮＰＮ型トラ
ンジスタ６のコレクタ電極を正電源５に接続し、ＮＰＮ
型トランジスタ６のエミッタ電極を出力端子１０と抵抗
素子７の一方の端子とＮチャネル型ＭＯＳトランジスタ
８のドレイン電極に接続し、抵抗素子７の他方の端子と
Ｎチャネル型ＭｏＳトランジスタ８のソース電極を負電
源９に接続し、立ち上がり検出回路１１の出力端１３を
Ｎチャネル型ＭＯＳトランジスタ８のゲート電極に接続
して構成している。In FIG. 1, the output circuit of this embodiment connects the output terminal 1 to the input terminal 12 of the rise detection circuit 11 and the input terminal 3 of the CMOS level ECL level conversion circuit 2, and
The negative phase output terminal 4 of the level ECL level conversion circuit 2 is set to NPN.
The collector electrode of the NPN type transistor 6 is connected to the positive power supply 5, and the NPN type transistor 6 is connected to the base electrode of the NPN type transistor 6.
The emitter electrode of the type transistor 6 is connected to the output terminal 10, one terminal of the resistance element 7, and the drain electrode of the N-channel type MOS transistor 8, and the other terminal of the resistance element 7 and the source electrode of the N-channel type MoS transistor 8 are connected. It is connected to the negative power supply 9, and the output terminal 13 of the rise detection circuit 11 is connected to the gate electrode of the N-channel type MOS transistor 8.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
ここで、負電源９の電位を０、正電源５の電位をＶＤＤ
にし、ＮＰＮ型トランジスタ６のオン状態におけるエミ
ッタ電極とベース電極の電位差をＶＢＥとし、ＣＭＯＳ
レベルＥＣＬレベル変換回路２の出力端子１０のハイレ
ベルとローレベルとの電位差をＶＳＢとし、この時ＣＭ
ＯＳレベルＥＣＬレベル変換回路２は、ＣＭＯＳレベル
ＥＣＬレベル変換回路２の入力端３がＣＭＯＳレベルで
ＶＤＤから０に変化すると逆相出力端４を、（ＶＤＤ−
ＶＳＢ）からＶＤＤに変化させ、ＣＭＯＳレベルＥＣＬ
レベル変換回路２の入力端３がＣＭＯＳレベルでＯから
ＶＤＤに変化すると逆相出力端子４をＶＤＤから（ＶＤ
Ｄ−ＶＳＢ）に変化させるものとして本実施例の説明を
行う。Here, the potential of the negative power supply 9 is set to 0, and the potential of the positive power supply 5 is set to VDD.
and the potential difference between the emitter electrode and the base electrode in the on state of the NPN transistor 6 is VBE, and the CMOS
The potential difference between the high level and low level of the output terminal 10 of the level ECL level conversion circuit 2 is defined as VSB, and at this time CM
When the input terminal 3 of the CMOS level ECL level conversion circuit 2 changes from VDD to 0 at the CMOS level, the OS level ECL level conversion circuit 2 changes the negative phase output terminal 4 to (VDD-
VSB) to VDD, CMOS level ECL
When the input terminal 3 of the level conversion circuit 2 changes from O to VDD at the CMOS level, the reverse phase output terminal 4 changes from VDD to (VDD
The present embodiment will be explained as a change to D-VSB).
尚立ち上がり検出回路１１の回路の一例を第３図に示す
。An example of the rise detection circuit 11 is shown in FIG.
入力端−子１の電位がＯがらＶＤＤに変化すると、ＣＭ
ＯＳレベルＥＣＬレベル変換回路２の逆相出力端４の電
位はＶＤＤから（ＶＤＤ−ＶＳＢ）に変化し、立ち上が
り検出回路１１は予め設定した一定期間論理値で°“１
”を出力するため、その間Ｎチャネル型ＭＯＳトランジ
スタ８はオン状態となるので出力端子１０に付く負荷に
蓄積された電荷が抵抗素子７を通りＮチャネル型ＭＯＳ
トランジスタ８のソース電極がちドレイン電極を通って
負電源９に流れ込むことによって出力端子１０の電位を
（ＶＤＤ−ＶＳＢ−ＶＢＥ）に下げ、その後立ち上がり
検出回路１１は論理値で°０°゛を出力するためＮチャ
ネル型ＭＯＳトランジスタ８はオフ状態となり抵抗素子
７によって出力端子１０の電位は保たれる。一方、入力
端子１の電位がＶＤＤから０に変化すると、立ち上がり
検出回路１１は論理値で“０°”のままなのでＮチャネ
ル型ＭＯ９トランジスタ８はオフ状態となり、ＣＭＯＳ
レベルＥＣＬ変換回路２の逆相出力端４の電位は（ＶＤ
Ｄ−ＶＳＢ）からＶＤＤに変化し出力端子１０を（ＶＤ
Ｄ−ＶＢＥ）に立ち上げるが、この時はＮチャネル型Ｍ
ＯＳトランジスタ８はオフ状態のため、ＮＰＮ型トラン
ジスタ５のエミッタ電流は出力端子１０を通って負荷を
駆動し、また一部が抵抗素子７を通って負電源９に流れ
込む、そのため、入力端子１が論理値でＩＩ Ｏ１１か
ら“１”に変化する時のみＮチャネル型ＭＯＳトランジ
スタ８がオン状態となり出力端子１０の論理値で１”か
ら“０″への変化を速め、それ以外のときはＮチャネル
型ＭＯＳトランジスタ８がオフ状態のとなるため抵抗素
子７の抵抗値を大きくすることにより定常電流を小さく
することが出来るので、消費電力を少なくできる。When the potential of input terminal 1 changes from O to VDD, CM
The potential of the negative phase output terminal 4 of the OS level ECL level conversion circuit 2 changes from VDD to (VDD-VSB), and the rise detection circuit 11 maintains a logic value of ``1'' for a preset period of time.
”, the N-channel MOS transistor 8 is turned on during that time, and the charge accumulated in the load attached to the output terminal 10 passes through the resistor 7 and is transferred to the N-channel MOS transistor 8.
The potential of the output terminal 10 is lowered to (VDD-VSB-VBE) by flowing into the negative power supply 9 through the source electrode and drain electrode of the transistor 8, and then the rising detection circuit 11 outputs a logical value of 0°. Therefore, N-channel type MOS transistor 8 is turned off, and the potential of output terminal 10 is maintained by resistor element 7. On the other hand, when the potential of the input terminal 1 changes from VDD to 0, the rise detection circuit 11 remains at the logical value "0°", so the N-channel type MO9 transistor 8 turns off, and the CMOS
The potential of the negative phase output terminal 4 of the level ECL conversion circuit 2 is (VD
D-VSB) to VDD, output terminal 10 becomes (VD
D-VBE), but at this time the N-channel type M
Since the OS transistor 8 is in the off state, the emitter current of the NPN transistor 5 passes through the output terminal 10 to drive the load, and a part of it flows through the resistor element 7 to the negative power supply 9. Therefore, the input terminal 1 Only when the logic value changes from II O11 to "1", the N-channel MOS transistor 8 is turned on, and the logic value of the output terminal 10 accelerates the change from 1 to "0"; otherwise, the N-channel MOS transistor 8 turns on. Since the type MOS transistor 8 is in the off state, the steady current can be reduced by increasing the resistance value of the resistor element 7, so power consumption can be reduced.
以上説明したように本発明は、入力信号用の入力端子を
入力信号が論理値で“０パから“１°゛に変化する時か
ら予め設定した一定期間だけ“１°′を出力してそれ以
外は“０”を出力する立ち上がり検出回路の入力端とレ
ベル変換回路の入力端とに接続し、レベル変換回路の逆
相出力端をＮＰＮ型トランジスタのベース電極に接続し
、ＮＰＮ型トランジスタのコレクタ電極を正電源に接続
し、ＮＰＮ型トランジスタのエミッタ電極を出力端子と
抵抗素子の一方の端子とＮチャネル型ＭＯＳトランジス
タのドレイン電極とに接続し、抵抗素子の他方の端子と
Ｎチャネル型ＭＯＳトランジスタのソース電極とを負電
源に接続し、立ち上がり検出回路の出力端をＮチャネル
型ＭＯＳトランジスタのゲートを極に接続して構成する
ことによって、入力信号が論理値で“０゛から“１”に
変化する時のみＮチャネル型ＭＯＳトランジスタがオン
状態となり出力端子の論理値で°“１”から““０”へ
の変化を速め、それ以外のときはＮチャネル型ＭＯ５ト
ランジスタがオフ状態となるため抵抗素子の抵抗値を大
きくすることにより定常電流を小さくすることができる
ので、従来より消費電力を小さくすることができる効果
がある。As explained above, the present invention enables an input terminal for an input signal to output "1°" for a predetermined period of time from when the input signal changes from "0" to "1°" in logical value. Otherwise, connect the input terminal of the rise detection circuit which outputs "0" and the input terminal of the level conversion circuit, connect the negative phase output terminal of the level conversion circuit to the base electrode of the NPN type transistor, and connect the collector of the NPN type transistor. The electrode is connected to a positive power supply, the emitter electrode of the NPN transistor is connected to the output terminal, one terminal of the resistance element, and the drain electrode of the N-channel MOS transistor, and the emitter electrode of the NPN transistor is connected to the other terminal of the resistance element and the N-channel MOS transistor. By connecting the source electrode of the circuit to a negative power supply and connecting the output terminal of the rise detection circuit to the gate of an N-channel MOS transistor, the input signal changes from "0" to "1" in logical value. Only when the output terminal changes, the N-channel MOS transistor is turned on to speed up the change from "1" to "0" depending on the logic value of the output terminal, and at other times the N-channel MO5 transistor is turned off. By increasing the resistance value of the resistance element, the steady current can be reduced, which has the effect of reducing power consumption compared to the conventional method.
第１図は本発明の出力回路の一実施例を示す回路図、第
２図は第１図の中のＣＭＯＳレベルＥＣＬレベル変換回
路の一例を示す回路図、第３図は第１図の中の立ち上が
り検出回路の一例を示す回路図、第４図は従来の出力回
路の一例を示す回路図である。
１・・・入力端子、２・・・ＣＭＯＳレベルＥＣＬレベ
ル変換回路、３・・・入力端、４・・・逆送出力端、５
・・・正電源、６・・・ＮＰＮ型トランジスタ、７．７
ａ・・・抵抗素子、８・・・Ｎチャネル型ＭＯＳトラン
ジスタ、９・・・負電源、１０・・・出力端子、１１・
・・立ち上がり検出回路、１２・・・入力端、１３・・
・出力端、２１．２２．２３．２５．２７・・・抵抗素
子、２４・・・正電源、２６・・・ＮＰＮ型トランジス
タ、２８・・・ＮＰＮ型トランジスタ、２９・・・定電
流源、３０・・・負電源、３１・・・リファレンス電圧
入力端子、１１１・・・遅延回路、１１２・・・インバ
ータ回路、１１３・・・ＡＮＤ回路。FIG. 1 is a circuit diagram showing an example of the output circuit of the present invention, FIG. 2 is a circuit diagram showing an example of the CMOS level ECL level conversion circuit in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the CMOS level ECL level conversion circuit in FIG. FIG. 4 is a circuit diagram showing an example of a conventional output circuit. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... CMOS level ECL level conversion circuit, 3... Input terminal, 4... Reverse feed output terminal, 5
...Positive power supply, 6...NPN type transistor, 7.7
a... Resistance element, 8... N-channel type MOS transistor, 9... Negative power supply, 10... Output terminal, 11...
...Rise detection circuit, 12...Input terminal, 13...
・Output terminal, 21.22.23.25.27... Resistance element, 24... Positive power supply, 26... NPN type transistor, 28... NPN type transistor, 29... Constant current source, 30... Negative power supply, 31... Reference voltage input terminal, 111... Delay circuit, 112... Inverter circuit, 113... AND circuit.
Claims (1)
から“１”に変化する時点から予め設定した一定期間だ
け“１”を出力してそれ以外は“０”を出力する立ち上
がり検出回路の入力端とレベル変換回路の入力端とに接
続し、前記レベル変換回路の逆相出力端子をＮＰＮ型ト
ランジスタのベース電極に接続し、前記ＮＰＮ型トラン
ジスタのコレクタ電極を正電源に接続し、前記ＮＰＮ型
トランジスタのエミッタ電極を出力端子と抵抗素子の一
方の端子とＮチャネル型ＭＯＳトランジスタのドレイン
電極とに接続し、前記抵抗素子の他方の端子と前記Ｎチ
ャネル型ＭＯＳトランジスタのソース電極とを負電源に
接続し、前記立ち上がり検出回路の出力端を前記Ｎチャ
ネル型ＭＯＳトランジスタのゲート電極に接続して成る
ことを特徴とする出力回路。The input terminal for the input signal is connected to the logic value “0” of the input signal.
Connected to the input end of the rise detection circuit and the input end of the level conversion circuit, which outputs "1" for a predetermined period from the time when the signal changes from "1" to "1", and outputs "0" otherwise. The negative phase output terminal of the level conversion circuit is connected to the base electrode of the NPN transistor, the collector electrode of the NPN transistor is connected to a positive power supply, and the emitter electrode of the NPN transistor is connected to the output terminal and one terminal of the resistance element. and the drain electrode of the N-channel MOS transistor, the other terminal of the resistance element and the source electrode of the N-channel MOS transistor are connected to a negative power supply, and the output end of the rise detection circuit is connected to the N-channel MOS transistor. An output circuit characterized in that it is connected to a gate electrode of a type MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332096A JPH03191615A (en) | 1989-12-20 | 1989-12-20 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332096A JPH03191615A (en) | 1989-12-20 | 1989-12-20 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03191615A true JPH03191615A (en) | 1991-08-21 |
Family
ID=18251101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1332096A Pending JPH03191615A (en) | 1989-12-20 | 1989-12-20 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03191615A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6998733B2 (en) | 2002-05-07 | 2006-02-14 | Renesas Technology Corp. | Pulse current generation circuit |
| JP2007081608A (en) * | 2005-09-13 | 2007-03-29 | Nec Electronics Corp | Output buffer circuit |
-
1989
- 1989-12-20 JP JP1332096A patent/JPH03191615A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6998733B2 (en) | 2002-05-07 | 2006-02-14 | Renesas Technology Corp. | Pulse current generation circuit |
| JP2007081608A (en) * | 2005-09-13 | 2007-03-29 | Nec Electronics Corp | Output buffer circuit |
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