JPH05120887A - Differential amplifying circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption per chip in a semiconductor integrated circuit by automatically stopping the current flowing to a differential amplifying circuit in the case of excess of the output level of this differential amplifying circuit over a prescribed level. CONSTITUTION:When a reset signal 105 is inputted from the external and is applied to one terminals of NOR circuits 13 and 14, control signals 107 and 106 are outputted as control signals in the low level and the high level respectively correspondingly to the output levels of circuits 13 and 14. Then, transfer gates 10 and 11 are turned off, and transfer gates 9 and 12 are turned on. Simultaneously, the signal 107 in the low level is inputted to gates of PMOS transistors TRS 1 and 2, and TRs 1 and 2 are turned off. The signal 106 in the high level is inputted to the gate of an NMOS TR 7 forming a current source to turn on the TR 7, and a current starts to flow to the TR 7. Thus, the amplifying function is stopped if the output level exceeds a prescribed value in the normal operation state of the differential amplifying circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional differential amplifier circuit composed of CMOS transistors, as shown in FIG.
It is composed of PMOS transistors 26 and 27 and NMOS transistors 28, 29 and 30. In FIG. 4, PMOS transistors 26 and 2
7 acts as a resistance element, and NMOS transistor 28
And 29 contribute as a pair transistor having the same characteristics to the amplifying action on the data inputs 115 and 116, and the NMOS transistor 30 acts as a current source via a bias voltage 119 externally supplied to the gate. It is working.

Corresponding to the voltage changes of the data input signals 115 and 116, the channel resistances of the NMOS transistors 26 and 27 inputting these data input signals to their gates are changed, and the voltage amplification by the PMOS transistors 28 and 29 is performed. By action, the voltage difference between the data inputs 115 and 116 is amplified and the data output signal 11
It is output as 7 and 116.

In this conventional differential amplifier circuit, regardless of the output levels of the data output signals 117 and 118 output from the differential amplifier circuit, a bias voltage 119 input from the outside is used as a current source. Functioning N
Current always flows through the MOS transistor 30.

[0005]

In the conventional differential amplifier circuit described above, as shown in FIG. 4, the bias voltage 119 supplied from the outside is supplied to the NMOS transistor 30 functioning as a current source. A current always flows through the differential amplifier circuit, and when the differential amplifier circuit is used inside a semiconductor integrated circuit, the power consumption per chip increases.

[0006]

A differential amplifier circuit of the present invention is a differential amplifier circuit formed in a semiconductor integrated circuit, wherein a differential amplifier circuit amplifies and outputs a voltage difference between two predetermined data input signals. The output level of the data output signal of the amplifying section and the differential amplifying section is inputted, and it operates so as to control the current flowing through the differential amplifying section via a control signal generated by a predetermined logical processing operation. And a control circuit.

The control signal output from the control circuit is also used as a timing signal for transmitting the current stop time of the differential amplifier to an external circuit included in the semiconductor integrated circuit. You can also

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The present embodiment is an example of a case where it is used in a memory output section of a semiconductor integrated circuit, and as shown in FIG. 1, PMOS transistors 1 to 4, NMOS transistors 5 to 7, transfer gates 9 to 12, NOR circuits 13, 14 and 22, and inverters 15-21
And a control circuit including.

In FIG. 1, the voltage difference between the data input signals 101 and 102 sent from a memory cell (not shown) included in the semiconductor integrated circuit is caused by the gates of the PMOS transistors 5 and 6 forming a differential amplifier pair, respectively. To be amplified and output as data output signals 103 and 104. The data output signals 103 and 104 are input to the NOR circuits 14 and 13 via the transfer gates 12 and 9 included in the control circuit 8, respectively, but the output levels of the data output signals 103 and 104 are When the threshold voltage of the PMOS transistor forming either of the NOR circuits 14 and 13 is exceeded, the control signal 107 of "H" level output from the inverter 21 and the "L" level output from the NOR circuit 22 are output. The control signal 106 of
It is input to the transfer gates 9, 10, 11 and 12, whereby the transfer gates 10 and 11 are turned on and the transfer gates 9 and 12 are turned off.

In this state, at the same time, the "H" level control signal 107 is applied to the PMOS transistors 1 and 2.
Are input to the gate of the NMOS transistor 7 and the PMOS transistors 1 and 2 are turned on, and the “L” level control signal 106 is also input to the gate of the NMOS transistor 7 forming the current source. , NMO
The S transistor 7 is also turned off, and the current flowing through the differential amplifier circuit via the NMOS transistor 7 is cut off. Therefore, the function as the differential amplifier circuit is stopped, and the potential levels of the output terminals of the data output signals 103 and 104 are maintained at the level of the supplied power supply voltage.

Next, when the reset signal 105 is input from the outside and is input to the other input terminals of the NOR circuits 13 and 14, corresponding to the output levels of these NOR circuits,
Control signals 107 and 106 are output as "L" level and "H" level control signals, respectively. As a result, the transfer gates 10 and 11 are turned off, and the transfer gates 9 and 12 are turned on. At the same time, the "L" level control signal 107 changes the PMO
The PMOS transistors 1 and 2 are input to the gates of the S transistors 1 and 2 and turned off, and the "H" level control signal 106 is input to the gate of the NMOS transistor 7 forming a current source.
When the NMOS transistor 7 is turned on, the NMOS
Current starts to flow in the transistor 7. Therefore, it returns to the operation state as the differential amplifier circuit, the voltage difference between the data input signals 101 and 102 is amplified, and the data output signals 103 and 104 are normally output.

That is, when the level of the data output signal amplified and output exceeds a predetermined level in the normal operation state of the differential amplifier circuit, the amplifying function of the differential amplifier circuit is controlled by the control circuit 8. Is stopped and the amplification function is restored by inputting a reset signal to the control circuit 8. Therefore, no current flows in the differential amplifier circuit except in a state where the differential amplifier circuit normally operates.

2A, 2B, 2C and 2D are timing charts of the operation signals in the above-mentioned embodiment, and the data input signal 101, respectively.
/ 102, data output signals 103/104, reset signal 105 and control signal 106.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the present embodiment. The operational amplifier circuit 23 and the control circuit 24 are provided corresponding to the external circuit 25.
And is configured. The operational amplifier circuit 23 and the control circuit 24 correspond to the above-described differential amplifier circuit and the control circuit 8, and in the present embodiment, the data input signal 108.
In response to the inputs 109 and 109, the signal 110 output from the operational amplifier circuit 23 is input to the control circuit 24, and the control signals 112 and 113 output from the control circuit 24 corresponding to the input of the signal 110 are calculated. The current fed back to the amplifier circuit 23 and flowing through the operational amplifier circuit 23 is controlled. That is, when the level of the signal 110 from the operational amplifier circuit 23 exceeds a predetermined level, the current of the operational amplifier circuit is stopped,
In the external circuit 25, the time point at which the current is stopped in the operational amplifier circuit 23 can be easily determined based on the output timing of the control signals 112 and 113. That is, in this embodiment, the control circuit 24 uses the external circuit 2
It also serves as a timing generator for 5.

[0016]

As described above, according to the present invention, when the output level of the differential amplifier circuit exceeds a predetermined level, the current flowing through the differential amplifier circuit is automatically stopped, so that the semiconductor There is an effect that the current consumption per chip in the integrated circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing operation signals in the one embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1-4, 26, 27 PMOS transistor 5-7, 28-30 NMOS transistor 8, 24 Control circuit 9-12 Transfer gate 13, 14, 22 NOR circuit 15-21 Inverter 23 Operational amplifier circuit 25 External circuit

Claims (2)

[Claims] 1. In a differential amplifier circuit formed in a semiconductor integrated circuit, a differential amplifier section that amplifies and outputs a voltage difference between two predetermined data input signals, and a data output signal of the differential amplifier section. A control circuit that operates to control the current flowing through the differential amplification section via a control signal generated by a predetermined logical processing operation. Amplifier circuit. 2. A control signal output from the control circuit is supplied to an external circuit included in the semiconductor integrated circuit,
The differential amplifier circuit according to claim 1, wherein the differential amplifier circuit is also used as a timing signal for transmitting a time point when the current of the differential amplifier section is stopped.