JPH0590441A - Leadless chip carrier - Google Patents

Leadless chip carrier

Info

Publication number
JPH0590441A
JPH0590441A JP27705891A JP27705891A JPH0590441A JP H0590441 A JPH0590441 A JP H0590441A JP 27705891 A JP27705891 A JP 27705891A JP 27705891 A JP27705891 A JP 27705891A JP H0590441 A JPH0590441 A JP H0590441A
Authority
JP
Japan
Prior art keywords
chip carrier
leadless chip
cleaning
insulating substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27705891A
Other languages
Japanese (ja)
Inventor
Yoshitaka Ono
嘉隆 小野
Teruo Hayashi
照雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP27705891A priority Critical patent/JPH0590441A/en
Publication of JPH0590441A publication Critical patent/JPH0590441A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/26Cleaning or polishing of the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Abstract

PURPOSE:To obtain a leadless chip carrier which achieves an improved washing even when it is mounted to a mother board. CONSTITUTION:In a lead chip carrier with a conductor circuit 11 and a recessed part 16 for mounting electronic parts which are formed at a surface side of an insulation substrate 1, a pad 12 for mounting on a mother board 2 which is formed at the rear-surface side, and a through-hole 13 which electrically connects the conductor circuit 11 and the pad 12 for mounting, a rear-surface side of the insulation substrate 1 is provided with a recessed part 17 for washing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,洗浄性に優れたリード
レスチップキャリアに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless chip carrier having excellent cleanability.

【0002】[0002]

【従来技術】従来,リードレスチップキャリアとして
は,例えば図9,10に示すものがある。上記リードレ
スチップキャリア10は,図9に示すごとく,絶縁基板
1と,該絶縁基板1の表面側に形成された導体回路11
と,絶縁基板1の裏面側に設けられマザーボード2に実
装するための実装用パッド12と,該実装用パッド12
と上記導体回路11とを電気的に接続するスルーホール
13とを有すると共に,上記表面側には電子部品搭載用
凹部16を設けている。
2. Description of the Related Art Conventionally, leadless chip carriers include those shown in FIGS. As shown in FIG. 9, the leadless chip carrier 10 includes an insulating substrate 1 and a conductor circuit 11 formed on the front surface side of the insulating substrate 1.
A mounting pad 12 provided on the back side of the insulating substrate 1 for mounting on the mother board 2, and the mounting pad 12
And a through hole 13 for electrically connecting the conductor circuit 11 and the conductor circuit 11, and a recess 16 for mounting an electronic component is provided on the front surface side.

【0003】上記絶縁基板1は,これをマザーボード2
に実装した場合,実装用パッド12においてマザーボー
ド2上のパッド21と半田3により固定されている。そ
して,絶縁基板1の裏面側とマザーボード2との間に
は,空間115と隙間105がある。空間115は絶縁
基板1の裏面119と,マザーボード2の表面29と,
そのパッド21,実装用パッド12,半田3とに囲まれ
た内部にある。その厚さは,50〜100μmである。
一方,隙間105は,適宜の間隔で設けられ,半田3に
より接続された実装用ハッド12,半田3及びパッド2
1と,絶縁基板1と,マザーボード2との間にできる。
その厚さは,空間115と同じである。また,その長さ
は1000〜2000μmである。
The insulating substrate 1 has a mother board 2
When mounted on the mounting pad 12, the mounting pad 12 is fixed to the pad 21 on the mother board 2 by the solder 3. A space 115 and a gap 105 are provided between the back surface of the insulating substrate 1 and the mother board 2. The space 115 includes a back surface 119 of the insulating substrate 1, a front surface 29 of the mother board 2,
It is inside the pad 21, the mounting pad 12, and the solder 3. Its thickness is 50-100 μm.
On the other hand, the gaps 105 are provided at appropriate intervals, and the mounting hud 12, the solder 3 and the pad 2 are connected by the solder 3.
1 and the insulating substrate 1 and the mother board 2.
Its thickness is the same as the space 115. The length is 1000 to 2000 μm.

【0004】次に,リードレスチップキャリア10とマ
ザーボード2の実装法について述べる。まず,リードレ
スチップキャリア10の実装用パッド12とスルーホー
ル13と,マザーボード2上のパッド21との間には,
半田付けを助長するフラックスが塗られる。そして,I
Rリフロー等により,上記の実装用パッド12,スルー
ホール13,及びマザーボード上のパッド21を半田付
けにより実装する。その後,半田から残ったフラックス
は,一種の腐蝕剤なので,実装後洗浄除去される。そし
て,その時の洗浄水は,リードレスチップキャリア10
の外部から,パッド間に形成された上記隙間105の部
分を通過させ,リードレスチップキャリア10の裏面1
19とマザーボード2の表面29との間の上記空間11
5の間に送入させる。そして,上記フラックスを洗浄す
る。
Next, a method of mounting the leadless chip carrier 10 and the mother board 2 will be described. First, between the mounting pad 12 and the through hole 13 of the leadless chip carrier 10 and the pad 21 on the motherboard 2,
Flux is applied to facilitate soldering. And I
The mounting pad 12, the through hole 13, and the pad 21 on the motherboard are mounted by soldering by R reflow or the like. After that, the flux remaining from the solder is a kind of corrosive agent, and is therefore removed by cleaning after mounting. Then, the cleaning water at that time is the leadless chip carrier 10
Of the leadless chip carrier 10 from the outside of the leadless chip carrier 10 through the gap 105 formed between the pads.
The space 11 between the surface 19 of the motherboard 19 and the surface 29 of the motherboard 2
Send in between 5. Then, the above flux is washed.

【0005】[0005]

【解決しようとする課題】しかしながら,上記空間11
5の厚さは,上記のごとく,僅か50〜100μmの厚
さしかなく,実装後の洗浄で洗浄液がその空間115内
に充分に入り込めない,或いは入り込みにくい。たと
え,洗浄水が入ったとしても,上記空間115の厚みが
小さいために,層流として流れるだけで,残ったフラッ
クスを除去することが困難である。本発明は,かかる従
来の問題点に鑑み,リードレスチップキャリアとマザー
ボードとの間の洗浄性に優れた,リードレスチップキャ
リアを提供しようとするものである。
[Problems to be Solved] However, the space 11
As described above, the thickness of No. 5 is only 50 to 100 μm, and the cleaning liquid cannot sufficiently or hardly enter the space 115 in the cleaning after mounting. Even if the cleaning water enters, it is difficult to remove the remaining flux only by flowing as a laminar flow because the space 115 has a small thickness. In view of the above conventional problems, the present invention aims to provide a leadless chip carrier having excellent cleaning properties between the leadless chip carrier and the mother board.

【0006】[0006]

【課題の解決手段】本発明は,絶縁基板と,該絶縁基板
の表面側に形成した導体回路と,絶縁基板の裏面側に設
けられマザーボードに実装するための実装用パッドと,
該実装用パッドと上記導体回路とを電気的に接続するス
ルーホールとを有すると共に,上記表面側には電子部品
搭載用凹部を設けてなるリードレスチップキャリアにお
いて,上記絶縁基板には,裏面側に洗浄用凹部を設けて
なることを特徴とするリードレスチップキャリアにあ
る。
According to the present invention, an insulating substrate, a conductor circuit formed on the front surface side of the insulating substrate, a mounting pad provided on the rear surface side of the insulating substrate for mounting on a mother board,
A leadless chip carrier having a through hole for electrically connecting the mounting pad and the conductor circuit, and a recess for mounting an electronic component on the front surface side, wherein the insulating substrate has a back surface side. The leadless chip carrier is characterized in that a cleaning recess is provided in the.

【0007】本発明において,洗浄用凹部は,前記のご
とく,絶縁基板の裏面側に設けられている。また,該洗
浄用凹部は,例えば100〜300μmの厚さに形成す
る。そのため,リードレスチップキャリアとマザーボー
ドとの間の空間の厚さは150〜400μmと広くな
る。上記100μm未満では充分な洗浄が期待できな
い。一方,300μmを越えると電子部品搭載用凹部底
面の板厚が薄くなり,電子部品を充分に保持できなくな
るという問題がある。また,絶縁基板は,上記洗浄用凹
部から外部へ連通する排水溝を有していることが好まし
い。例えば,上記排水溝は,絶縁基板の四隅に設ける
(図6参照)。これにより,洗浄水は,リードレスチッ
プキャリアとマザーボードと実装用パッド等との間の隙
間をスムーズに通過して,上記空間内に入ることがで
き,従来よりも多量の洗浄水が洗浄用凹部に流れ込む。
そして,十分な洗浄を行い,該排水溝より排水となって
流出する。
In the present invention, the cleaning recess is provided on the back surface side of the insulating substrate as described above. The cleaning recess is formed to have a thickness of 100 to 300 μm, for example. Therefore, the thickness of the space between the leadless chip carrier and the mother board is as wide as 150 to 400 μm. If it is less than 100 μm, sufficient cleaning cannot be expected. On the other hand, if the thickness exceeds 300 μm, there is a problem that the thickness of the bottom surface of the recess for mounting an electronic component becomes thin and the electronic component cannot be sufficiently held. Further, it is preferable that the insulating substrate has a drain groove communicating from the cleaning recess to the outside. For example, the drainage grooves are provided at the four corners of the insulating substrate (see FIG. 6). As a result, the cleaning water can smoothly pass through the gap between the leadless chip carrier, the motherboard, and the mounting pad, etc., and enter the space, and a larger amount of cleaning water than before can be obtained. Flow into.
Then, it is thoroughly washed and becomes drainage from the drainage groove and flows out.

【0008】[0008]

【作用及び効果】本発明のリードレスチップキャリアに
おいては,絶縁基板の裏面側に洗浄用凹部を設けること
により,リードレスチップキャリアとマザーボードの空
間の厚さが150〜400μmと,従来の50〜100
μmに比べてかなり広がる。そのため,リードレスチッ
プキャリアの洗浄時に,この空間に入った洗浄水は乱流
を形成する。それ故,十分な洗浄効果が得られる。上記
のごとく,本発明によれば,リードレスチップキャリア
とマザーボードとの間の洗浄性に優れたリードレスチッ
プキャリアを提供することができる。
In the leadless chip carrier of the present invention, the space between the leadless chip carrier and the mother board has a thickness of 150 to 400 .mu.m, which is 50 to 400 .mu.m. 100
It is much wider than μm. Therefore, when cleaning the leadless chip carrier, the cleaning water entering this space forms a turbulent flow. Therefore, a sufficient cleaning effect can be obtained. As described above, according to the present invention, it is possible to provide a leadless chip carrier having excellent cleanability between the leadless chip carrier and the mother board.

【0009】[0009]

【実施例】実施例1 本発明の実施例にかかるリードレスチップキャリアにつ
き,図1ないし図5を用いて説明する。本例のリードレ
スチップキャリア10は,図1に示すごとく,絶縁基板
1,導体回路11,実装用パッド12,そしてスルーホ
ール13を有すると共に,上記絶縁基板1の表面側には
電子部品搭載用凹部16,そして裏面側には洗浄用凹部
17を設けている。上記絶縁基板1は,長さ1000〜
2000μmの実装用パッド12において,半田3によ
りマザーボード2のパッド21に装着されている。
Embodiment 1 A leadless chip carrier according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the leadless chip carrier 10 of this example has an insulating substrate 1, a conductor circuit 11, a mounting pad 12, and a through hole 13, and on the surface side of the insulating substrate 1 for mounting electronic components. A recess 16 and a cleaning recess 17 are provided on the back surface side. The insulating substrate 1 has a length of 1000 to
The 2000 μm mounting pad 12 is mounted on the pad 21 of the mother board 2 by the solder 3.

【0010】また,リードレスチップキャリア10とマ
ザーボード2の空間は,図1〜図3に示すごとく,実装
用パッド12と半田3とマザーボードのパッド21の厚
さにより形成される空間115(従来と同様)と,絶縁
基板の裏面側に形成された洗浄用凹部17の厚さにより
形成される空間116よりなる。そして,空間115
(厚み50〜100μm)と空間116(100〜30
0μm)を合わせた洗浄空間117の厚さは150〜4
00μmになる。その他は,前記従来例と同様である。
As shown in FIGS. 1 to 3, the space between the leadless chip carrier 10 and the mother board 2 is formed by the thickness of the mounting pad 12, the solder 3 and the mother board pad 21 (compared with the conventional case). The same) and a space 116 formed by the thickness of the cleaning recess 17 formed on the back surface side of the insulating substrate. And the space 115
(Thickness 50 to 100 μm) and space 116 (100 to 30
The thickness of the cleaning space 117, which is 0 μm), is 150 to 4
It becomes 00 μm. Others are the same as in the conventional example.

【0011】次に,上記リードレスチップキャリア10
の製造法につき,図4及び図5を用いて説明する。ま
ず,図4(a)に示すごとく,表面に銅箔層110,1
20を有する絶縁基板1を準備する。次に,図4(b)
に示すごとくスルーホール130を穿設し,図4(c)
に示すごとく電子部品搭載用凹部16をザグリ加工によ
り設ける。更に図4(d)に示すごとく,上記電子部品
搭載用凹部16の反対側に洗浄用凹部17をザグリ加工
により設ける。
Next, the leadless chip carrier 10 described above.
The manufacturing method will be described with reference to FIGS. 4 and 5. First, as shown in FIG. 4A, the copper foil layers 110, 1 are formed on the surface.
An insulating substrate 1 having 20 is prepared. Next, FIG. 4 (b)
A through hole 130 is formed as shown in FIG.
As shown in, the electronic component mounting recess 16 is provided by counterboring. Further, as shown in FIG. 4D, a cleaning recess 17 is provided on the opposite side of the electronic component mounting recess 16 by counterboring.

【0012】その後,図5(a)に示すごとく,上記絶
縁基板1の全表面に金属メッキ180を施し,次いで図
5(b)に示すごとく,エッチング処理により導体回路
11及び実装用パッド12を形成する。更に,図5
(c)に示すごとく,スルーホール13をその中心部に
おいて切断し,半円状のスルーホールとする。また,こ
れにより切断端面15が成形される。このようにして得
られたリードレスチップキャリア10は,実装用パッド
12,弧状のスルーホール13において,前記のごとく
マザーボードのパッド21に対して半田接合される。
Thereafter, as shown in FIG. 5 (a), metal plating 180 is applied to the entire surface of the insulating substrate 1, and then, as shown in FIG. 5 (b), the conductor circuit 11 and the mounting pads 12 are removed by etching. Form. Furthermore, FIG.
As shown in (c), the through hole 13 is cut at its central portion to form a semicircular through hole. Moreover, the cut end surface 15 is formed by this. The leadless chip carrier 10 thus obtained is soldered to the pad 21 of the mother board as described above at the mounting pad 12 and the arc-shaped through hole 13.

【0013】このようにして,上記図1に示したリード
レスチップキャリアが得られる。尚,図2は,リードレ
スチップキャリアを裏面側からみた平面図である。ま
た,図3は,半田付けしたリードレスチップキャリア1
0を,図2のA−A線に沿って垂直に切断し,裏面側か
らみた斜視図である。図2及び図3は,洗浄水Wが,矢
印で示すごとく,パッド間に形成された隙間105を通
過し,内部の洗浄空間117に入り込み,乱流を形成し
ながら洗浄する様子を示している。十分な洗浄後,他の
隙間105より排出される。
In this way, the leadless chip carrier shown in FIG. 1 is obtained. Note that FIG. 2 is a plan view of the leadless chip carrier as seen from the back surface side. 3 shows the solderless leadless chip carrier 1
FIG. 3 is a perspective view in which 0 is cut vertically along the line AA in FIG. 2 and viewed from the back surface side. 2 and 3 show a state in which the cleaning water W passes through the gap 105 formed between the pads as shown by the arrow, enters the cleaning space 117 inside, and cleans while forming a turbulent flow. .. After sufficient cleaning, it is discharged from another gap 105.

【0014】上記より知られるごとく,本例のリードレ
スチップキャリア10においては,マザーボード2との
間に,従来の隙間115に加えて洗浄用凹部17の隙間
116を加えた洗浄空間117を形成している。そのた
め,上記洗浄空間117に入った洗浄水Wは,乱流を形
成してその内部を良く洗浄する。また,その後は,この
乱流状態の洗浄水Wが,実装パッド12とマザーボード
2との間の隙間105を通って勢い良く排出される。そ
のため,リードレスチップキャリア10とマザーボード
2との間のフラックス等は,充分に洗浄除去される。
As is known from the above, in the leadless chip carrier 10 of this embodiment, a cleaning space 117 is formed between the mother board 2 and the conventional clearance 115, in addition to the clearance 116 of the cleaning recess 17. ing. Therefore, the cleaning water W that has entered the cleaning space 117 forms a turbulent flow and cleans the inside thereof well. After that, the turbulent cleaning water W is vigorously discharged through the gap 105 between the mounting pad 12 and the motherboard 2. Therefore, the flux and the like between the leadless chip carrier 10 and the mother board 2 are sufficiently washed and removed.

【0015】実施例2 次に,実施例2について,図6及び図7を用いて,説明
する。本例は,実施例1の絶縁基板1に,洗浄用凹部1
7から外部へ連通する排水溝19を,その四隅に設けた
ものである。排水溝19は,洗浄用凹部17と同じ深さ
である。その他は,実施例1と同様である。洗浄時に
は,上記排水溝19により多量の洗浄水が洗浄空間11
7に流れ込むことができる。また,洗浄空間117で
は,実施例1と同様の十分な洗浄効果が得られる。ま
た,排水溝19は,前記図4に示したごとく,ザグリ加
工により図4(d)の洗浄用凹部を形成するのと同時
に,四隅に形成する。その他は,実施例1の絶縁基板の
製造法と同様である。
Second Embodiment Next, a second embodiment will be described with reference to FIGS. 6 and 7. In this example, the insulating substrate 1 of Example 1 is provided with a cleaning recess 1
Drainage grooves 19 communicating with the outside from 7 are provided at the four corners. The drain groove 19 has the same depth as the cleaning recess 17. Others are the same as in the first embodiment. At the time of cleaning, a large amount of cleaning water is supplied to the cleaning space 11 by the drain groove 19.
Can flow into 7. Further, in the cleaning space 117, a sufficient cleaning effect similar to that of the first embodiment can be obtained. Further, as shown in FIG. 4, the drainage grooves 19 are formed at the four corners at the same time when the cleaning recess shown in FIG. 4D is formed by counterboring. Others are the same as the method of manufacturing the insulating substrate of the first embodiment.

【0016】実施例3 次に,実施例3について,図8を用いて説明する。本例
は,洗浄用凹部17を形成するために予め貫通穴を設け
ておいた絶縁基板と,他の基板とを接合して,リードレ
スチップキャリアを製造する方法を示している。即ち,
まず図8(a)に示すごとく,片面に銅箔層105を有
する第1基板100と,片面に銅箔層165を有する第
2基板160と,プリプレグ102を準備する。上記第
2基板160とプリプレグ102は,洗浄用凹部17を
設けるための貫通穴166,1020を有する。次に,
第1基板100と第2基板160とは,図8(b)に示
すごとく,銅箔層の形成されていない面同志をプリプレ
グ102を挟んで,熱圧着により接着する。これによ
り,洗浄用凹部17が形成される。次に,図8(c)に
示すごとく,スルーホール130を穿設する。そして,
図8(d)に示すごとく,表面側に電子部品搭載用凹部
16を設ける。その後は,実施例1と同様に,図5に示
すごとく絶縁基板全体にメッキを行い,スルーホール1
3をその中心部で切断し,半円状のスルーホールとす
る。本例によれば,図8(a)に示すごとく,予め洗浄
用凹部を形成するための貫通穴166を設けてあるの
で,実施例1のごとくザグリ加工により洗浄用凹部17
を形成する必要がない。また,本例によれば,実施例1
と同様の効果を得ることができる。
Third Embodiment Next, a third embodiment will be described with reference to FIG. This example shows a method of manufacturing a leadless chip carrier by joining an insulating substrate, which has been previously provided with through holes for forming the cleaning recess 17, with another substrate. That is,
First, as shown in FIG. 8A, a first substrate 100 having a copper foil layer 105 on one surface, a second substrate 160 having a copper foil layer 165 on one surface, and a prepreg 102 are prepared. The second substrate 160 and the prepreg 102 have through holes 166 and 1020 for providing the cleaning recess 17. next,
As shown in FIG. 8B, the first substrate 100 and the second substrate 160 are bonded to each other by thermocompression bonding with the prepreg 102 sandwiching the surfaces having no copper foil layer. As a result, the cleaning recess 17 is formed. Next, as shown in FIG. 8C, a through hole 130 is formed. And
As shown in FIG. 8D, an electronic component mounting recess 16 is provided on the front surface side. After that, as in the first embodiment, the entire insulating substrate is plated as shown in FIG.
3 is cut at its central portion to form a semicircular through hole. According to the present example, as shown in FIG. 8A, since the through hole 166 for forming the cleaning recess is provided in advance, the cleaning recess 17 is formed by counterboring as in the first embodiment.
Need not be formed. According to this example, the first embodiment
The same effect as can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1における,マザーボードに実装された
リードレスチップキャリアの断面図。
FIG. 1 is a sectional view of a leadless chip carrier mounted on a mother board according to a first embodiment.

【図2】実施例1における,リードレスチップキャリア
の裏面図。
FIG. 2 is a back view of the leadless chip carrier according to the first embodiment.

【図3】図2のA−A線で切断した,半田付けされたリ
ードレスチップキャリアの裏面斜視図。
FIG. 3 is a rear perspective view of the soldered leadless chip carrier taken along the line AA in FIG.

【図4】実施例1における,リードレスチップキャリア
の製造工程の説明図。
FIG. 4 is an explanatory diagram of a manufacturing process of the leadless chip carrier according to the first embodiment.

【図5】図4に続く,工程説明図。FIG. 5 is an explanatory view of the process following FIG.

【図6】実施例2における,リードレスチップキャリア
の裏面図。
FIG. 6 is a rear view of the leadless chip carrier according to the second embodiment.

【図7】図6のB−B線で切断した,半田付けされたリ
ードレスチップキャリアの裏面斜視図。
FIG. 7 is a rear perspective view of the soldered leadless chip carrier taken along the line BB in FIG.

【図8】実施例3における,リードレスチップキャリア
の製造工程の説明図。
FIG. 8 is an explanatory diagram of a manufacturing process of a leadless chip carrier according to a third embodiment.

【図9】従来例における,マザーボードに実装されたリ
ードレスチップキャリアの断面図。
FIG. 9 is a cross-sectional view of a leadless chip carrier mounted on a motherboard in a conventional example.

【図10】従来例における,リードレスチップキャリア
の裏面図。
FIG. 10 is a rear view of the leadless chip carrier in the conventional example.

【符号の説明】[Explanation of symbols]

1...絶縁基板, 2...マザーボード, 3...半田, 10...リードレスチップキャリア, 11...導体回路, 12...実装用パッド, 13...スルーホール, 16...電子部品搭載用凹部, 17...洗浄用凹部, 19...排水溝, 21...マザーボード上のパッド, 1. . . Insulating substrate, 2. . . Motherboard, 3. . . Solder, 10. . . Leadless chip carrier, 11. . . Conductor circuit, 12. . . Mounting pad, 13. . . Through hole, 16. . . Recess for mounting electronic components, 17. . . Cleaning recess, 19. . . Drainage, 21. . . Pads on the motherboard,

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板と,該絶縁基板の表面側に形成
した導体回路と,絶縁基板の裏面側に設けられマザーボ
ードに実装するための実装用パッドと,該実装用パッド
と上記導体回路とを電気的に接続するスルーホールとを
有すると共に,上記表面側には電子部品搭載用凹部を設
けてなるリードレスチップキャリアにおいて, 上記絶縁基板には,裏面側に洗浄用凹部を設けてなるこ
とを特徴とするリードレスチップキャリア。
1. An insulating substrate, a conductor circuit formed on a front surface side of the insulating substrate, a mounting pad provided on a rear surface side of the insulating substrate for mounting on a mother board, the mounting pad and the conductor circuit. In a leadless chip carrier having a through hole for electrically connecting with each other and having a recess for mounting an electronic component on the front surface side, wherein the insulating substrate has a recess for cleaning on the back surface side. Leadless chip carrier characterized by.
【請求項2】 請求項1において,絶縁基板は,上記洗
浄用凹部から外部へ連通する排水溝を有していることを
特徴とするリードレスチップキャリア。
2. The leadless chip carrier according to claim 1, wherein the insulating substrate has a drain groove communicating from the cleaning recess to the outside.
JP27705891A 1991-09-26 1991-09-26 Leadless chip carrier Pending JPH0590441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27705891A JPH0590441A (en) 1991-09-26 1991-09-26 Leadless chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27705891A JPH0590441A (en) 1991-09-26 1991-09-26 Leadless chip carrier

Publications (1)

Publication Number Publication Date
JPH0590441A true JPH0590441A (en) 1993-04-09

Family

ID=17578202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27705891A Pending JPH0590441A (en) 1991-09-26 1991-09-26 Leadless chip carrier

Country Status (1)

Country Link
JP (1) JPH0590441A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129770A (en) * 1995-10-31 1997-05-16 Nec Corp Integrated circuit device
WO2002089257A2 (en) * 2001-04-25 2002-11-07 Siemens Production And Logistics Systems Ag Connection housing for an electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129770A (en) * 1995-10-31 1997-05-16 Nec Corp Integrated circuit device
WO2002089257A2 (en) * 2001-04-25 2002-11-07 Siemens Production And Logistics Systems Ag Connection housing for an electronic component
WO2002089257A3 (en) * 2001-04-25 2003-01-03 Siemens Production & Logistics Connection housing for an electronic component

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