JPH0444293A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH0444293A JPH0444293A JP2149417A JP14941790A JPH0444293A JP H0444293 A JPH0444293 A JP H0444293A JP 2149417 A JP2149417 A JP 2149417A JP 14941790 A JP14941790 A JP 14941790A JP H0444293 A JPH0444293 A JP H0444293A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- printed wiring
- wiring board
- land
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000005476 soldering Methods 0.000 claims abstract description 11
- 239000011888 foil Substances 0.000 claims abstract description 8
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 238000007747 plating Methods 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子部品を高密度に実装できるプリント配線
基板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed wiring board on which electronic components can be mounted with high density.
従来の技術
近年、プリント配線基板は、電子機器の小型化をめざし
た、より高密度な実装を可能にするものとして大変重要
である。BACKGROUND OF THE INVENTION In recent years, printed wiring boards have become very important as they enable higher-density packaging in order to miniaturize electronic devices.
以下、図面を参照しながら従来のプリント配線基板につ
いて説明する。Hereinafter, a conventional printed wiring board will be described with reference to the drawings.
第4図は従来のプリント配線基板にチップ部品を高密度
実装したときの状態を示す平面図であり、図において1
はプリント配線基板2の上面に設けられたチップ部品3
をはんだ付けするためのランド部、4はチップ部品3の
両端に設けられた電極部でランド部1にはんだ5によっ
てはんた付けされている。6はプリント配線基板2の他
の面または内層に設けられている導体部(図示せず)と
電気的に導通させるためのスルーホール部である。Figure 4 is a plan view showing the state when chip components are mounted at high density on a conventional printed wiring board.
is a chip component 3 provided on the top surface of a printed wiring board 2
Land portions 4 for soldering are electrode portions provided at both ends of the chip component 3, and are soldered to the land portions 1 with solder 5. Reference numeral 6 denotes a through-hole portion for electrically connecting with a conductor portion (not shown) provided on the other surface or inner layer of the printed wiring board 2.
以上のように構成されたプリント配線基板2においては
、スルーホール部6はランド部1に接続してその一端に
設けられており、したがってプリント配線基板2の上面
において電子部品を搭載する面積以外にスルーホール部
6を設けるための面積を必要とする。In the printed wiring board 2 configured as described above, the through hole portion 6 is connected to the land portion 1 and provided at one end thereof, and therefore, the area on the upper surface of the printed wiring board 2 is occupied by an area other than the area on which electronic components are mounted. An area for providing the through hole portion 6 is required.
発明が解決しようとする課題
しかしながら上g己のような構成では、チンプ部品3等
を高密度に実装する場合、プリント配線基板2に設けら
れているスルーホール部6の占める面積がチップ部品3
等の実装面積を減少させる原因となっている。一方ラン
ド部1の内部にスルーホール部6を形成して実装密度を
上げようとした場合、リフローはんだ付は工法において
はんた5が溶融するとき、スルーホール部6の内部に流
れこみ、チップ部品3等を接続するためのはんた5の量
が不均一になり、はんだ付けの品質が十分得られなくな
ってしまうという課題がある。Problems to be Solved by the Invention However, in the above configuration, when chip components 3 and the like are mounted at high density, the area occupied by the through-hole portion 6 provided in the printed wiring board 2 is larger than the area occupied by the chip components 3.
This causes a reduction in the mounting area. On the other hand, when attempting to increase the packaging density by forming through-hole portions 6 inside the land portions 1, when the solder 5 melts in the reflow soldering method, it flows into the through-hole portions 6 and chips There is a problem in that the amount of solder 5 used to connect components 3 and the like becomes non-uniform, resulting in insufficient soldering quality.
本発明は上記課題を解決するものであり、表面実装部品
等を高密度に実装できるプリント配線基板を提供するこ
とを目的とするものである。The present invention is intended to solve the above-mentioned problems, and an object of the present invention is to provide a printed wiring board on which surface-mounted components and the like can be mounted with high density.
課題を解決するための手段
本発明は上記目的を達成するためにプリント配線基板の
画面または内層の導体部分に導通ずるスルーホール部が
表面実装部品の電極部をはんだ付けするためのランド部
内に設けられ、かつスルーホール部の開口端を導体材料
で被覆した構成を備えたものである。Means for Solving the Problems In order to achieve the above object, the present invention provides a through-hole section that conducts to the screen or the conductor section of the inner layer of the printed wiring board in the land section for soldering the electrode section of the surface mount component. The opening end of the through-hole portion is coated with a conductive material.
作用
本発明は上記した構成によって、プリント配線基板のス
ルーホール部と表面実装部品をはんた付けするためのラ
ンド部とを同−面積内に配置することが可能となり、プ
リント配線基板の面積を有効に活用でき、したがってよ
り一層の高密度実装を実現できる。Effect of the Invention With the above-described configuration, the present invention makes it possible to arrange the through-hole portion of the printed wiring board and the land portion for soldering surface-mounted components within the same area, thereby reducing the area of the printed wiring board. It can be used effectively, and therefore even higher density packaging can be achieved.
実施例
以下、本発明の一実施例について第1図〜第3図とさも
に第4図と同一部分については同一番号を付して詳しい
説明を省略し、相違する点について説明する。Embodiment Hereinafter, regarding an embodiment of the present invention, parts that are the same as those in FIGS. 1 to 3 and 4 will be given the same reference numerals, detailed explanations will be omitted, and differences will be explained.
第1図および第2図は本発明の一実施例の構成を示すも
のであり、スルーホール部7はランド部1の内部に設ζ
すられており、そのスルーホール7はその開口端8を銅
箔等よりなる導体箔9によって被覆されている。またス
ルーホール7の内部は導電性ペーストまたは金属線材ま
たは銅メツキ材等からなる導電材10によって充填され
ている。1 and 2 show the configuration of an embodiment of the present invention, in which the through hole portion 7 is provided inside the land portion 1.
The opening end 8 of the through hole 7 is covered with a conductive foil 9 made of copper foil or the like. Further, the inside of the through hole 7 is filled with a conductive material 10 made of a conductive paste, a metal wire, a copper plating material, or the like.
つぎに上記の構成においてその動作を説明する。Next, the operation of the above configuration will be explained.
上記実施例において、スルーホール部7はチップ部品等
の表面実装部品3の電極部4をはんた付けするためラン
ド部1の同一面内に設けられており、さらにそのスルー
ホール部7の開口端8は導体箔9で被覆され、ランド部
1の面とともに均一な面となっている。したかって第2
図から明らかなように従来例に見られたランド部1に接
続するスルーホール部6を形成する必要がなく、より一
層の高密度実装が可能となり、またスルーホール部7の
開口端8は導体箔9および導電材10によって封しられ
ているためはんだ5が流れ込みはんだ付は品質を悪くす
ることもない。In the above embodiment, the through-hole portion 7 is provided on the same surface of the land portion 1 in order to solder the electrode portion 4 of the surface-mounted component 3 such as a chip component, and the opening of the through-hole portion 7 is The end 8 is covered with a conductive foil 9 and forms a uniform surface along with the surface of the land portion 1. The second thing I want to do is
As is clear from the figure, there is no need to form a through-hole section 6 connected to the land section 1 as seen in the conventional example, and even higher density mounting is possible. Since it is sealed by the foil 9 and the conductive material 10, the solder 5 will not flow in and the soldering quality will not deteriorate.
つぎに、本実施例の製造方法を第3図ial〜げ)を用
いて説明する。Next, the manufacturing method of this example will be explained using FIGS.
第3図ta+に示すような両面に銅箔11ををするガラ
スエポキ/樹脂等よりなるプリント配線基板2にドリル
等によってスルーホール部7を穿孔しく第3図1b))
、そのスルーホール部7の内面と銅箔11の表面に導通
部12(主に銅)がめっきによって設けられる(第3図
(C))。つぎにスルーホール部7の内部に導電性ペー
ストまたは金属線材または銅メツキ材等を充填すること
によって導電材10を形成する(第3図(d))。さら
に、これら銅箔11の表面およびスルーホール部7の開
口端8を閉塞した導電材10の表面をめっきによってめ
っき層13を形成した後(第3図(el)、不要部分を
エツチングして配線パターンを形成する(第3図(f)
)。As shown in Fig. 3 ta+, a through-hole portion 7 is drilled in a printed wiring board 2 made of glass epoxy/resin etc. with copper foil 11 on both sides using a drill etc. Fig. 3 1b))
A conductive portion 12 (mainly copper) is provided on the inner surface of the through-hole portion 7 and the surface of the copper foil 11 by plating (FIG. 3(C)). Next, a conductive material 10 is formed by filling the inside of the through hole portion 7 with a conductive paste, metal wire, copper plating material, etc. (FIG. 3(d)). Furthermore, after forming a plating layer 13 by plating the surface of these copper foils 11 and the surface of the conductive material 10 that closed the open end 8 of the through-hole portion 7 (FIG. 3(el)), unnecessary portions are etched and wiring is formed. Forming a pattern (Fig. 3 (f)
).
このように上記実施例によれば、スルーホール部7を表
面実装部品をはんだ付けするランド部1内に形成するこ
とにより表面実装部品3を搭載する面積を増加すること
ができ、より高密度な実装が可能となる。As described above, according to the above embodiment, by forming the through hole portion 7 in the land portion 1 to which the surface mount component is soldered, the area for mounting the surface mount component 3 can be increased, and a higher density can be achieved. Implementation becomes possible.
なお、本実施例においてめっき層13を形成する方法と
して、銅をめっきする以外に銅箔をプレスして積層する
ことも可能である。In addition, as a method for forming the plating layer 13 in this embodiment, it is also possible to press and laminate copper foils in addition to plating copper.
発明の効果
以上のように本発明によれば、プリント配線基板の両面
または内層の導体部分に導通ずるスルーホール部が表面
実装部品の電極部をはんだ付けするためのランド部内に
設けられ、かつスルーホ−ル部の開口端を導体箔で被覆
しているためにスルーホール部をランド部以外に設ける
必要かなく、プリント配線基板の面積を有効に活用する
ことができ、したがって表面実装部品を高密度に実装す
ることが可能になるという効果が得られる。Effects of the Invention As described above, according to the present invention, a through-hole portion that is electrically connected to both surfaces of a printed wiring board or a conductor portion of an inner layer is provided in a land portion for soldering an electrode portion of a surface mount component. - Since the open end of the round part is covered with conductive foil, there is no need to provide a through hole part other than the land part, and the area of the printed wiring board can be used effectively, so surface mount components can be mounted at high density. This has the effect that it can be implemented in
第1図は本発明の〜実施例のプリント配線基板の構成を
示す要部断面図、第2図は同プリント配線基板に表面実
装部品を搭載した状態を示す部分平面図、第3図(al
〜(f+は同プリント配線基板の製造方法を示す工程図
、第4図は従来のプリント配線基板に部品を搭載した状
態を示す部分平面図である。
1・・・・・・ランド部、2・・・・・・プリント配線
基板、3・・・・・・チップ部品(表面実装部品)、4
・・・・・・電極部、7・・・・・・スルーホール部、
8・・・・・・開口端、9・・・・・導体箔。
代理人の氏名 弁理士 粟野重孝 はか12第 3 図
14FA
1−−−うンy(で
斗−實睡帥
7−− スノL−71、−1し告P
ε−−−開口tgFIG. 1 is a sectional view of a main part showing the configuration of a printed wiring board according to an embodiment of the present invention, FIG. 2 is a partial plan view showing a state in which surface-mounted components are mounted on the same printed wiring board, and FIG.
~(f+ is a process diagram showing the manufacturing method of the same printed wiring board, and FIG. 4 is a partial plan view showing a state in which components are mounted on a conventional printed wiring board. 1...Land part, 2 ...Printed wiring board, 3...Chip parts (surface mount parts), 4
... Electrode part, 7... Through hole part,
8... Open end, 9... Conductor foil. Name of agent Patent attorney Shigetaka Awano Haka 12 No. 3 Figure 14 FA 1 --- Uny (Deto-Jisuishu 7-- Suno L-71, -1 Shisho P ε --- Opening tg
Claims (1)
て、その両面または内層の導体部分に導通するスルーホ
ール部が表面実装部品の電極部をはんだ付けするための
ランド部内に設けられ、かつ前記スルーホール部の開口
端を導体箔で被覆したプリント配線基板。A printed wiring board having a double-sided or multilayer structure, wherein a through-hole portion that conducts to a conductor portion on both surfaces or an inner layer is provided in a land portion for soldering an electrode portion of a surface mount component, and the through-hole portion is provided in a land portion for soldering an electrode portion of a surface mount component. A printed wiring board whose open end is covered with conductive foil.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2149417A JP2926902B2 (en) | 1990-06-07 | 1990-06-07 | Printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2149417A JP2926902B2 (en) | 1990-06-07 | 1990-06-07 | Printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0444293A true JPH0444293A (en) | 1992-02-14 |
JP2926902B2 JP2926902B2 (en) | 1999-07-28 |
Family
ID=15474662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2149417A Expired - Lifetime JP2926902B2 (en) | 1990-06-07 | 1990-06-07 | Printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2926902B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04188689A (en) * | 1990-11-19 | 1992-07-07 | Toshiba Corp | Printed wiring board |
JPH0621632A (en) * | 1992-07-03 | 1994-01-28 | Nec Corp | Multilayer printed wiring board |
JPH08213759A (en) * | 1992-07-31 | 1996-08-20 | Toppan Printing Co Ltd | Multilayer printed circuit board |
JPH09331145A (en) * | 1996-06-11 | 1997-12-22 | Nec Corp | Pad structure on wiring board |
WO2005086548A1 (en) * | 2004-03-04 | 2005-09-15 | Sankyo Kasei Co., Ltd. | Three-dimensional circuit board |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01100996A (en) * | 1987-10-14 | 1989-04-19 | Canon Inc | Multilayer printed wiring board |
-
1990
- 1990-06-07 JP JP2149417A patent/JP2926902B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01100996A (en) * | 1987-10-14 | 1989-04-19 | Canon Inc | Multilayer printed wiring board |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04188689A (en) * | 1990-11-19 | 1992-07-07 | Toshiba Corp | Printed wiring board |
JPH0621632A (en) * | 1992-07-03 | 1994-01-28 | Nec Corp | Multilayer printed wiring board |
JPH08213759A (en) * | 1992-07-31 | 1996-08-20 | Toppan Printing Co Ltd | Multilayer printed circuit board |
JPH09331145A (en) * | 1996-06-11 | 1997-12-22 | Nec Corp | Pad structure on wiring board |
WO2005086548A1 (en) * | 2004-03-04 | 2005-09-15 | Sankyo Kasei Co., Ltd. | Three-dimensional circuit board |
US8528202B2 (en) | 2004-03-04 | 2013-09-10 | Sankyo Kasei Co., Ltd. | Method for manufacturing a three dimensional circuit board |
Also Published As
Publication number | Publication date |
---|---|
JP2926902B2 (en) | 1999-07-28 |
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