JPH0590329A - Semiconductor optical element - Google Patents
Semiconductor optical elementInfo
- Publication number
- JPH0590329A JPH0590329A JP24816091A JP24816091A JPH0590329A JP H0590329 A JPH0590329 A JP H0590329A JP 24816091 A JP24816091 A JP 24816091A JP 24816091 A JP24816091 A JP 24816091A JP H0590329 A JPH0590329 A JP H0590329A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor optical
- ausn
- semiconductor
- optical element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Led Devices (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、サブマウントのＡｕＳ
ｎもしくはＰｂＳｎのバンプ上に半導体光素子をフリッ
プチップ実装する半導体光素子に関し、位置精度が向上
し、セルフアラインによる結合損失が少なくなることが
可能な半導体光素子に関するものである。The present invention relates to a submount AuS.
The present invention relates to a semiconductor optical device in which a semiconductor optical device is flip-chip mounted on a bump of n or PbSn, and to a semiconductor optical device capable of improving position accuracy and reducing coupling loss due to self-alignment.
【０００２】[0002]
【従来の技術】本発明光素子の実装方法において、フリ
ップチップ実装が実現されている。フリップチップ実装
は、Ａｕワイヤで配線をしないために配線距離を短くで
き且つセルフアライン実装が可能である。2. Description of the Related Art In the method of mounting an optical element according to the present invention, flip chip mounting is realized. In the flip-chip mounting, the wiring distance can be shortened and self-aligned mounting is possible because wiring is not performed with Au wires.
【０００３】近年の半導体光素子の需要増と低コスト化
のためには、半導体光素子自体の低コスト化とともに、
組立工程における低コスト化も必要になってくる。その
ためには、セルフアライン実装が可能なフリップチップ
実装が重要である。フリップチップ実装は、Ａｕワイヤ
ボンディングをすることなく実装でき、しかもセルフア
ラインによって自動的に実装位置が決まる。In order to increase the demand and cost of semiconductor optical devices in recent years, the cost of the semiconductor optical device itself has been reduced and
It is also necessary to reduce the cost in the assembly process. For that purpose, flip-chip mounting that enables self-aligned mounting is important. Flip chip mounting can be performed without Au wire bonding, and the mounting position is automatically determined by self-alignment.
【０００４】しかし、マウント上のＡｕＳｎやＰｂＳｎ
等のバンプ量や形状などによって位置精度が異なってく
る。光ファイバ結合をセルフアラインで行う場合、位置
精度が悪くなると結合損失が大きくなる。従って、結合
損失を最小限に抑えるためには、セルフアラインの位置
精度を高めていくことが重要である。However, AuSn or PbSn on the mount
The positional accuracy varies depending on the bump amount, shape, etc. When the optical fiber coupling is performed by self-alignment, the coupling loss increases when the positional accuracy deteriorates. Therefore, in order to minimize the coupling loss, it is important to improve the position accuracy of self-alignment.
【０００５】図５は、フリップチップ実装した第１の従
来例の構造の断面概略図である。第１の従来例として、
レンズ付きメサ型面発光ダイオードを示す。発光ダイオ
ード５は、通常のフォトリソグラフィ技術を用い、電流
狭搾メサ部６を作成した。図には示していないが、絶縁
膜として窒化シリコンを用い、Ｔｉ／Ｐｔ及びＡｕＧｅ
でオーミック電極をつけ、更にｐ型電極用Ａｕバンプ３
及びｎ型電極用Ａｕバンプ４を電解メッキ法により作成
した。発光ダイオード５の発光部分は、ウェットエッチ
ング法により凸状のレンズ部７を作成し、発光効率を高
めた。実装するサブマウント基板１には、アルミナを用
い、Ａｕパッドを配線した。Ａｕパッド上にＡｕＳｎバ
ンプ２を作成し、その後発光ダイオード５を乗せ温度を
あげ融着した。FIG. 5 is a schematic sectional view of the structure of the first conventional example mounted by flip chip. As a first conventional example,
1 shows a mesa type surface emitting diode with a lens. For the light emitting diode 5, the current squeezing mesa portion 6 was created by using a normal photolithography technique. Although not shown in the figure, silicon nitride is used as the insulating film, and Ti / Pt and AuGe are used.
Ohmic electrode is attached with and Au bump 3 for p-type electrode
And Au bumps 4 for n-type electrodes were formed by electrolytic plating. In the light emitting portion of the light emitting diode 5, a convex lens portion 7 was formed by a wet etching method to improve the light emitting efficiency. Alumina was used for the submount substrate 1 to be mounted, and Au pads were wired. The AuSn bump 2 was formed on the Au pad, and then the light emitting diode 5 was placed on the Au pad to raise the temperature and fuse them.
【０００６】図６は、フリップチップ実装した第２の従
来例の構造の断面概略図である。第２の従来例として、
レンズ付き裏面入射型ｐｉｎフォトダイオードを示す。
ｐｉｎフォトダイオード８は、通常のフォトリソグラフ
ィ技術を用い、Ｚｎ拡散によりｐ+ 拡散領域９を作成
し、ｐｎ接合を作成した。図には示していないが、絶縁
膜且つパッシベーション膜として窒化シリコンを用い、
ＡｕＺｎ及びＡｕＧｅでオーミック電極をつけ更にｐ型
電極用Ａｕバンプ３及びｎ型電極用Ａｕバンプ４を電解
メッキ法により作成した。ｐｉｎフォトダイオード８の
光入射部分には、ウェットエッチング法により凸状のレ
ンズ部７を作成し、量子効率を高めた。実装するサブマ
ウント基板１には、アルミナを用い、Ａｕパッドを配線
した。Ａｕパッド上にＡｕＳｎバンプ２を作成し、その
後ｐｉｎフォトダイオード８を乗せ温度をあげ融着し
た。FIG. 6 is a schematic sectional view of the structure of the second conventional example which is flip-chip mounted. As a second conventional example,
A back-illuminated pin photodiode with a lens is shown.
For the pin photodiode 8, a normal photolithography technique was used to form ap + diffusion region 9 by Zn diffusion to form a pn junction. Although not shown in the figure, silicon nitride is used as an insulating film and a passivation film,
An ohmic electrode was attached using AuZn and AuGe, and Au bumps 3 for p-type electrodes and Au bumps 4 for n-type electrodes were formed by electrolytic plating. A convex lens portion 7 was formed on the light incident portion of the pin photodiode 8 by a wet etching method to improve quantum efficiency. Alumina was used for the submount substrate 1 to be mounted, and Au pads were wired. The AuSn bump 2 was formed on the Au pad, and then the pin photodiode 8 was placed on the Au pad to raise the temperature and fuse them.
【０００７】尚、実装の方法を図７に簡単に示す。The mounting method is briefly shown in FIG.
【０００８】工程１（ＡｕＳｎバンプ固定） サブマウント基板１上に配線したＡｕパッド１０上に、
ＡｕＳｎバンプ２を乗せる。Step 1 (Fixing AuSn bump) On the Au pad 10 wired on the submount substrate 1,
Place the AuSn bump 2.
【０００９】工程２（リフロー） Ａｕパッド１０上に仮固定したＡｕＳｎバンプ２を、温
度を上げて溶かし（３００℃程度）、リフローニングす
る。Step 2 (Reflow) The AuSn bump 2 temporarily fixed on the Au pad 10 is melted by raising the temperature (about 300 ° C.) and reflowed.
【００１０】工程３（半導体光素子実装） リフローニングしたＡｕＳｎバンプ２上に半導体光素子
１１（発光ダイオード，面発光レーザ，ｐｉｎフォトダ
イオード及びアバランシェフォトダイオード等を含む半
導体光素子及び半導体光素子を含む光集積素子）を乗せ
温度を上げ融着する。Step 3 (semiconductor optical device mounting) A semiconductor optical device 11 (including a semiconductor optical device including a light emitting diode, a surface emitting laser, a pin photodiode, an avalanche photodiode, and the like) is provided on the reflowed AuSn bump 2. An optical integrated device) is placed and the temperature is raised to fuse.
【００１１】[0011]
【発明が解決しようとする課題】図８の（ａ）及び
（ｂ）に、第１及び第２の従来例として発光ダイオード
及びｐｉｎフォトダイオードの位置ズレの個数を示し
た。位置確認は、サブマウントに予め目印としてつけた
確認位置と半導体光素子のズレ具合を位置ズレ量とした
（２００個〜２５０個程度）。第１の従来例及び第２の
従来例とも位置ズレ量は、±１０μｍ以上あり、精密な
位置精度がでていない。この原因は、ＡｕＳｎの量及び
リフローした時の形状などが大きく影響していると考え
られる。量や形状を精密に制御することも重要である
が、逆に精度を許容する範囲つまりトレランスを大きく
することも必要である。FIGS. 8A and 8B show the number of positional deviations of the light emitting diode and the pin photodiode as the first and second conventional examples. In the position confirmation, the amount of positional deviation is the degree of deviation between the confirmation position and the semiconductor optical element, which are previously marked on the submount as a mark (about 200 to 250 pieces). The positional deviation amount is ± 10 μm or more in both the first conventional example and the second conventional example, and precise positional accuracy cannot be obtained. It is considered that the cause of this is that the amount of AuSn and the shape after reflow have a great influence. Although it is important to precisely control the quantity and shape, it is also necessary to increase the range in which accuracy is allowed, that is, the tolerance.
【００１２】こうした問題は、セルフアラインによる光
ファイバーとの結合において結合損失が大きくなるばか
りでなくセルフアラインによる結合ができなくなり、コ
ストが高くなる。[0012] These problems not only increase coupling loss in coupling with an optical fiber by self-alignment but also prevent coupling by self-alignment, resulting in high cost.
【００１３】本発明の目的は、上記の課題を克服し、フ
リップチップ実装する半導体光素子に関し、位置精度が
向上し、セルフアラインによる結合損失が少なくなるこ
とが可能な半導体光素子を提供することにある。An object of the present invention is to overcome the above problems and to provide a semiconductor optical device for flip-chip mounting, in which the positional accuracy is improved and the coupling loss due to self-alignment can be reduced. It is in.
【００１４】[0014]
【課題を解決するための手段】本発明は、サブマウント
のＡｕＳｎもしくはＰｂＳｎのバンプ上にフリップチッ
プ実装された半導体光素子であって、素子のバンプ電極
が凹状になっていることを特徴とする。SUMMARY OF THE INVENTION The present invention is a semiconductor optical device flip-chip mounted on AuSn or PbSn bumps of a submount, wherein the bump electrodes of the device are concave. ..
【００１５】半導体光素子は、半導体発光素子、半導体
受光素子、これら素子のアレイ，マトリックス素子、ま
たは光電気集積素子例えばＰＩＮ−ＦＥＴ，ＬＤ−ＦＥ
Ｔ等である。The semiconductor optical device is a semiconductor light emitting device, a semiconductor light receiving device, an array of these devices, a matrix device, or an optoelectronic integrated device such as a PIN-FET or LD-FE.
T etc.
【００１６】[0016]
【作用】本発明は、上述の手段をとることにより、従来
技術の問題点を解決した。The present invention has solved the problems of the prior art by taking the above-mentioned means.
【００１７】これは、サブマウントのＡｕＳｎもしくは
ＰｂＳｎのバンプ上に半導体素子をフリップチップ実装
する半導体光素子において、素子のバンプ電極を凹状に
することにより、融着する接触面積を大きくとることに
よって位置精度が向上し、光ファイバーとのセルフアラ
イン結合を可能にし、結合損失を少なくすることが可能
となる。This is because, in a semiconductor optical device in which a semiconductor device is flip-chip mounted on a bump of AuSn or PbSn of a submount, the bump electrode of the device is formed into a concave shape so as to increase the contact area for fusion. The accuracy is improved, the self-alignment coupling with the optical fiber is enabled, and the coupling loss can be reduced.
【００１８】[0018]
【実施例】本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described.
【００１９】図１は、本発明による第１の実施例の半導
体発光素子をフリップチップ実装した断面概略図であ
る。第１の実施例として、レンズ付きメサ型面発光ダイ
オードを示す。発光ダイオード５は、通常のフォトリソ
グラフィ技術を用い、電流狭搾メサ部６を作成した。図
には示していないが、絶縁膜として窒化シリコンを用
い、Ｔｉ／Ｐｔ及びＡｕＧｅでオーミックを電極をつけ
更にｐ型電極用Ａｕバンプ３及びｎ型電極用Ａｕバンプ
４を電解メッキ法により作成した。ｐ型電極用Ａｕバン
プ３及びｎ型電極用Ａｕバンプ４は、フォトリソグラフ
ィ技術により一部だけをエッチングするようにパターニ
ングし、なだらかな凹状にエッチング加工する（静止エ
ッチングでは、急峻な段差はできない）。発光ダイオー
ド５の発光部分は、ウェットエッチング法により凸状の
レンズ部７を作成し、発光効率を高めた。実装するサブ
マウント基板１には、アルミナを用い、Ａｕパッドを配
線した。Ａｕパッド上にＡｕＳｎバンプ２を作成し、そ
の後発光ダイオード５を乗せ温度を上げ融着した。サブ
マウント１は、熱伝導率の高い窒化アルミ等も利用され
る。FIG. 1 is a schematic sectional view of a semiconductor light emitting device according to the first embodiment of the present invention, which is flip-chip mounted. As a first embodiment, a mesa type surface emitting diode with a lens will be shown. For the light emitting diode 5, the current squeezing mesa portion 6 was created by using a normal photolithography technique. Although not shown in the figure, silicon nitride was used as an insulating film, an ohmic electrode was attached using Ti / Pt and AuGe, and Au bumps 3 for p-type electrodes and Au bumps 4 for n-type electrodes were formed by electrolytic plating. . The Au bumps 3 for p-type electrodes and the Au bumps 4 for n-type electrodes are patterned by photolithography so that only a part of them is etched, and etched into a gentle concave shape (a steep step cannot be formed by static etching). . In the light emitting portion of the light emitting diode 5, a convex lens portion 7 was formed by a wet etching method to improve the light emitting efficiency. Alumina was used for the submount substrate 1 to be mounted, and Au pads were wired. The AuSn bump 2 was formed on the Au pad, and then the light emitting diode 5 was placed on the Au pad to raise the temperature and fuse them. The submount 1 is also made of aluminum nitride or the like having high thermal conductivity.
【００２０】図２は、本発明による第２の実施例の半導
体受光素子をフリップチップ実装した断面概略図であ
る。第２の本実施例として、レンズ付き裏面入射型ｐｉ
ｎフォトダイオードを示す。ｐｉｎフォトダイオード８
は、通常のフォトリソグラフィ技術を用い、Ｚｎ拡散に
よりｐ+ 拡散領域９を作成し、ｐｎ接合を作成した。図
には示していないが、絶縁膜且つパッシベーション膜と
して窒化シリコンを用い、ＡｕＡｎ及びＡｕＧｅでオー
ミック電極をつけ更にｐ型電極用Ａｕバンプ３及びｎ型
電極用Ａｕバンプ４を電解メッキ法により作成した。ｐ
型電極用Ａｕバンプ３及びｎ型電極用Ａｕバンプ４は、
第１の実施例と同様に作成した。ｐｉｎフォトダイオー
ド８の光入射部分には、ウェットエッチング法により凸
状のレンズ部７を作成し、量子効率を高めた。実装する
サブマウント基坂１には、アルミナを用い、Ａｕパッド
を配線した。Ａｕパッド上にＡｕＳｎバンプ２を作成
し、その後ｐｉｎフォトダイオード８を乗せ温度を上げ
融着した。FIG. 2 is a schematic sectional view of a semiconductor light receiving element of the second embodiment according to the present invention, which is flip-chip mounted. As a second embodiment, a back-illuminated pi with lens is used.
n photodiode is shown. pin photodiode 8
Was formed into a p + diffusion region 9 by Zn diffusion using a normal photolithography technique to form a pn junction. Although not shown in the figure, silicon nitride was used as an insulating film and a passivation film, ohmic electrodes were attached with AuAn and AuGe, and Au bumps 3 for p-type electrodes and Au bumps 4 for n-type electrodes were formed by electrolytic plating. .. p
The type electrode Au bump 3 and the n-type electrode Au bump 4 are
It was created in the same manner as in the first embodiment. A convex lens portion 7 was formed on the light incident portion of the pin photodiode 8 by a wet etching method to improve quantum efficiency. Alumina was used for the submount Kisaka 1 to be mounted, and Au pads were wired. The AuSn bump 2 was formed on the Au pad, and then the pin photodiode 8 was placed on the Au pad to raise the temperature and fuse them.
【００２１】尚、実装の方法を図３に簡単に示す。The mounting method is briefly shown in FIG.
【００２２】工程１（ＡｕＳｎバンプ固定） サブマウント基坂１上に配線したＡｕパッド１０上に、
ＡｕＳｎバンプ２を乗せる。Step 1 (fixing AuSn bump) On the Au pad 10 wired on the submount Kisaka 1
Place the AuSn bump 2.
【００２３】工程２（リフロー） Ａｕパッド１０上に仮固定したＡｕＳｎバンプ２を、温
度を上げて溶かし（３００℃程度）、リフローニングす
る。Step 2 (Reflow) The AuSn bump 2 temporarily fixed on the Au pad 10 is melted by raising the temperature (about 300 ° C.) and reflowed.
【００２４】工程３（半導体光素子実装） リフローニングしたＡｕＳｎバンプ２上に半導体光素子
１１（発光ダイオード，面発光レーザ，ｐｉｎフォトダ
イオード及びアバランシェフォトダイオード等を含む半
導体光素子及び半導体光素子を含む光集積素子）を乗せ
温度を上げ融着する。Step 3 (Semiconductor Optical Device Mounting) The semiconductor optical device 11 (including a semiconductor optical device including a light emitting diode, a surface emitting laser, a pin photodiode, an avalanche photodiode, etc.) is provided on the reflowed AuSn bump 2. An optical integrated device) is placed and the temperature is raised to fuse.
【００２５】この様にｐ型及びｎ型電極用Ａｕバンプを
凹状に加工することで、融着の接触面積を大きく取るこ
とができ、位置精度を高くすることができ光ファイバー
結合をセルフアラインですることが可能となる。By processing the Au bumps for the p-type and n-type electrodes in a concave shape in this manner, a large contact area for fusion can be secured, the positional accuracy can be increased, and the optical fiber coupling can be self-aligned. It becomes possible.
【００２６】得られた発光ダイオード及びｐｉｎフォト
ダイオードの位置精度を表す位置ズレに対する個数を図
４に示す。位置ズレは、前記従来例における位置ズレ測
定と同じ手法である。位置ズレは従来例に対して半分程
度に収まり、位置精度が飛躍的に向上していることがわ
かる。これは、凹状のＡｕバンプを有する半導体光素子
において、サブマウント基坂に融着する接触面積を大き
くすることによって、接触強度を高めセルフアライン効
果を高めたことによるものである。FIG. 4 shows the number of obtained light emitting diodes and pin photodiodes with respect to the positional deviation, which represents the positional accuracy. The positional deviation is the same method as the positional deviation measurement in the conventional example. It can be seen that the positional deviation is reduced to about half that of the conventional example, and the positional accuracy is dramatically improved. This is because, in the semiconductor optical device having the concave Au bumps, the contact area fused to the submount substrate is increased to increase the contact strength and enhance the self-alignment effect.
【００２７】[0027]
【発明の効果】本発明による半導体光素子は、得られる
半導体光素子において、サブマウント基坂にフリップチ
ップ実装した場合位置精度が向上することが可能となっ
た。According to the semiconductor optical device of the present invention, it is possible to improve the positional accuracy of the obtained semiconductor optical device when it is flip-chip mounted on the submount substrate.
【図１】本発明による第１の実施例の発光ダイオードを
実装したときの断面概略図である。FIG. 1 is a schematic cross-sectional view of a mounted light emitting diode according to a first embodiment of the present invention.
【図２】本発明による第２の実施例のｐｉｎフォトダイ
オードを実装したときの断面概略図である。FIG. 2 is a schematic sectional view when a pin photodiode of a second embodiment according to the present invention is mounted.
【図３】半導体光素子の実装方法の工程概略図である。FIG. 3 is a schematic process diagram of a method for mounting a semiconductor optical device.
【図４】発光ダイオード及びｐｉｎフォトダイオードの
位置ズレ量に対する個数を示した図である。FIG. 4 is a diagram showing the number of light emitting diodes and pin photodiodes with respect to the positional deviation amount.
【図５】第１の従来例の発光ダイオードを実装したとき
の断面概略図である。FIG. 5 is a schematic cross-sectional view when a light emitting diode of a first conventional example is mounted.
【図６】第２の従来例のｐｉｎフォトダイオードを実装
したときの断面概略図である。FIG. 6 is a schematic sectional view when a pin photodiode of a second conventional example is mounted.
【図７】半導体光素子の実装方法の工程概略図である。FIG. 7 is a process schematic diagram of a method for mounting a semiconductor optical device.
【図８】発光ダイオード及びｐｉｎフォトダイオードの
位置ズレ量に対する個数を示した図である。FIG. 8 is a diagram showing the number of light emitting diodes and pin photodiodes with respect to the positional deviation amount.
１ サブマウント基坂 ２ ＡｕＳｎバンプ ３ ｐ型電極用Ａｕバンプ ４ ｎ型電極用Ａｕバンプ ５ 発光ダイオード ６ 電流狭搾メサ部 ７ レンズ部 ８ ｐｉｎフォトダイオード ９ ｐ+ 拡散領域 １０ Ａｕパッド １１ 半導体光素子 １２ Ａｕバンプ1 Submount Kisaka 2 AuSn Bump 3 Au Bump for p-type Electrode 4 Au Bump for n-type Electrode 5 Light Emitting Diode 6 Current Squeezing Mesa Part 7 Lens Part 8 Pin Photodiode 9 p + Diffusion Area 10 Au Pad 11 Semiconductor Photonic Device 12 Au bump
Claims (2)
のバンプ上にフリップチップ実装された半導体光素子で
あって、素子のバンプ電極が凹状になっていることを特
徴とする半導体光素子。1. Submount AuSn or PbSn
The semiconductor optical device flip-chip mounted on the bump of, wherein the bump electrode of the device is concave.
は半導体受光素子、または半導体集積素子であることを
特徴とする請求項１記載の半導体光素子。2. The semiconductor optical device according to claim 1, wherein the semiconductor device is a semiconductor light emitting device, a semiconductor light receiving device, or a semiconductor integrated device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24816091A JPH0590329A (en) | 1991-09-27 | 1991-09-27 | Semiconductor optical element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24816091A JPH0590329A (en) | 1991-09-27 | 1991-09-27 | Semiconductor optical element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590329A true JPH0590329A (en) | 1993-04-09 |
Family
ID=17174117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24816091A Pending JPH0590329A (en) | 1991-09-27 | 1991-09-27 | Semiconductor optical element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590329A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996003776A1 (en) * | 1994-07-21 | 1996-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| US6136626A (en) * | 1994-06-09 | 2000-10-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| JP2002043623A (en) * | 2000-07-27 | 2002-02-08 | Nichia Chem Ind Ltd | Optical semiconductor element and its manufacturing method |
| US7456438B2 (en) | 2005-10-17 | 2008-11-25 | Samsung Electro-Mechanics Co., Ltd. | Nitride-based semiconductor light emitting diode |
| JP2011034989A (en) * | 2009-07-29 | 2011-02-17 | Showa Denko Kk | Semiconductor light-emitting element and method for manufacturing the same, lamp, electronic apparatus, and mechanical apparatus |
| US8643046B2 (en) | 2009-05-14 | 2014-02-04 | Toyoda Gosei Co., Ltd. | Semiconductor light-emitting element, method for producing the same, lamp, lighting device, electronic equipment, mechanical device and electrode |
| KR20160053138A (en) * | 2014-10-31 | 2016-05-13 | 서울바이오시스 주식회사 | High efficiency light emitti ng device |
| JP2019004064A (en) * | 2017-06-16 | 2019-01-10 | ウシオオプトセミコンダクター株式会社 | Multi-beam semiconductor laser element and multi-beam semiconductor laser device |
| KR20190088562A (en) * | 2016-12-06 | 2019-07-26 | 엘지이노텍 주식회사 | Light emitting element |
| CN113161455A (en) * | 2021-01-26 | 2021-07-23 | 江西乾照光电有限公司 | MiniLED chip and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55140280A (en) * | 1979-04-20 | 1980-11-01 | Hitachi Ltd | Light emitting diode |
| JPS62279645A (en) * | 1986-05-28 | 1987-12-04 | Hitachi Ltd | Method for solder connection |
-
1991
- 1991-09-27 JP JP24816091A patent/JPH0590329A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55140280A (en) * | 1979-04-20 | 1980-11-01 | Hitachi Ltd | Light emitting diode |
| JPS62279645A (en) * | 1986-05-28 | 1987-12-04 | Hitachi Ltd | Method for solder connection |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6136626A (en) * | 1994-06-09 | 2000-10-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| EP1473781A2 (en) * | 1994-07-21 | 2004-11-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| US5895225A (en) * | 1994-07-21 | 1999-04-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| US6133058A (en) * | 1994-07-21 | 2000-10-17 | Matsushita Electric Industrial Co., Ltd. | Fabrication of semiconductor light-emitting device |
| US5751013A (en) * | 1994-07-21 | 1998-05-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| WO1996003776A1 (en) * | 1994-07-21 | 1996-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| EP1473781A3 (en) * | 1994-07-21 | 2007-02-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor light-emitting device and production method thereof |
| JP2002043623A (en) * | 2000-07-27 | 2002-02-08 | Nichia Chem Ind Ltd | Optical semiconductor element and its manufacturing method |
| US7456438B2 (en) | 2005-10-17 | 2008-11-25 | Samsung Electro-Mechanics Co., Ltd. | Nitride-based semiconductor light emitting diode |
| US8643046B2 (en) | 2009-05-14 | 2014-02-04 | Toyoda Gosei Co., Ltd. | Semiconductor light-emitting element, method for producing the same, lamp, lighting device, electronic equipment, mechanical device and electrode |
| JP2011034989A (en) * | 2009-07-29 | 2011-02-17 | Showa Denko Kk | Semiconductor light-emitting element and method for manufacturing the same, lamp, electronic apparatus, and mechanical apparatus |
| KR20160053138A (en) * | 2014-10-31 | 2016-05-13 | 서울바이오시스 주식회사 | High efficiency light emitti ng device |
| KR20190088562A (en) * | 2016-12-06 | 2019-07-26 | 엘지이노텍 주식회사 | Light emitting element |
| JP2019004064A (en) * | 2017-06-16 | 2019-01-10 | ウシオオプトセミコンダクター株式会社 | Multi-beam semiconductor laser element and multi-beam semiconductor laser device |
| CN113161455A (en) * | 2021-01-26 | 2021-07-23 | 江西乾照光电有限公司 | MiniLED chip and manufacturing method thereof |
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