JP2011034989A - Semiconductor light-emitting element and method for manufacturing the same, lamp, electronic apparatus, and mechanical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element including an electrode capable of preventing a component of a metal reflecting layer from being diffused, and to provide a method for manufacturing the semiconductor light-emitting element, a lamp, an electronic apparatus, and a mechanical apparatus. <P>SOLUTION: The semiconductor light-emitting element 1 is provided with: a substrate 101; a laminated semiconductor layer 20 wherein an n-type semiconductor layer 104, a light-emitting layer 105 and a p-type semiconductor layer 106 are laminated on the substrate 101 in the order; one electrode 111 bonded to the p-type semiconductor layer 106; and the other electrode 108 bonded to the n-type semiconductor layer 104. In the semiconductor light-emitting element 1, one or both of the electrode 111 or the other electrode 108 have a structure wherein a first diffusion preventing layer 51, the metal reflection layer 52, and a second diffusion preventing layer 53 are laminated in the order, and the first diffusion preventing layer 51 comprises an oxide containing any metal among In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn, and Ni. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device, a method for manufacturing the same, a lamp, an electronic device, and a mechanical device, and more particularly, a semiconductor light emitting device including an electrode that prevents diffusion of a material of a metal reflective layer, a method for manufacturing the same, a lamp, The present invention relates to electronic equipment and mechanical devices.

  In recent years, GaN-based compound semiconductors have attracted attention as semiconductor materials for short wavelength light emitting devices. In general, GaN-based compound semiconductors are formed on a substrate such as a sapphire single crystal, various oxides, and a group III-V compound such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It is formed using thin film forming means.

A GaN-based compound semiconductor light emitting device generally includes an n-type GaN-based compound semiconductor (hereinafter referred to as an n-type semiconductor layer), an active layer (hereinafter referred to as a light-emitting layer), and a p-type GaN-based compound semiconductor layer (hereinafter referred to as a p-type semiconductor layer). And a p-type electrode on the p-type semiconductor layer, and an n-type electrode on the n-type semiconductor layer.
In such a GaN-based compound semiconductor light emitting device, the light emitting device is mounted on the wiring substrate with the substrate facing up and the electrode facing down, so that the light emitted from the light emitting layer is extracted to the outside through the substrate. There is a flip chip type semiconductor light emitting device.

  In the flip-chip type semiconductor light emitting device, an electrode having a reflective layer such as Ag or Al is formed in order to reflect light by the electrode. However, Ag is a metal that is easily oxidized, and in order to easily cause migration in a high temperature range of 300 ° C. or higher, a technology that surrounds Ag with a metal that does not react with Ag (Patent Document 1) and white that has high reflectivity. A technique using a metal or an alloy thereof as a reflective layer (Patent Document 2) is disclosed.

  However, even if the Ag is surrounded by a metal that does not react with Ag, if the contact surface between the Ag electrode and the GaN compound semiconductor is large, Ag migration to the GaN compound semiconductor occurs, resulting in a decrease in reflectance. The problem is that the luminous efficiency decreases due to the light emission and the VF increases due to poor contact, the Pt group is also difficult to migrate, but the reflectivity is low compared to Ag in the first place, and migration cannot be prevented at temperatures close to 400 ° C. there were.

JP 2006-245232 A JP 2006-183400 A

  The present invention has been made in view of the above circumstances, and has a positive and negative electrode portion (n-type electrode and / or p-type electrode) and a semiconductor laminated semiconductor layer (an n-type semiconductor layer and / or a p-type semiconductor layer in contact with the electrode). ) And effectively preventing migration of Ag (silver) to a compound semiconductor even under severe conditions, thereby providing a highly reliable, high-quality semiconductor light-emitting device, a manufacturing method thereof, a lamp, An object is to provide an electronic device and a mechanical device.

In order to achieve the above object, the present invention employs the following configuration. That is,
(1) a substrate, a stacked semiconductor layer in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are stacked in this order on the substrate; one electrode bonded to the p-type semiconductor layer; A semiconductor light emitting device comprising: the other electrode bonded to the n-type semiconductor layer, wherein one or both of the one electrode and the other electrode are the first diffusion preventing layer and the metal reflection layer. And the first diffusion prevention layer is formed of In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn. A semiconductor light-emitting device comprising an oxide containing any one of Ni and Ni.

(2) The semiconductor light-emitting element according to (1), wherein the first diffusion prevention layer is any one of ITO, IZO, AZO, or GZO.
(3) The semiconductor light-emitting element according to (1) or (2), wherein the first diffusion preventing layer has a maximum thickness of 1 nm to 500 nm.
(4) Any one of (1) to (3), wherein an inclined surface is formed on the outer edge of the first diffusion preventing layer so that the film thickness gradually decreases toward the outer peripheral side. The semiconductor light emitting device according to item.

(5) The semiconductor light-emitting element according to any one of (1) to (4), wherein the metal reflective layer is made of Ag, Rh, or an alloy containing any of the metals.
(6) The semiconductor light emitting element according to any one of (1) to (5), wherein the metal reflective layer is an APC alloy or an ANC alloy.
(7) The semiconductor light-emitting element according to any one of (1) to (6), wherein the metal reflective layer has a maximum thickness of 20 to 3000 nm.

(8) In any one of (1) to (7), an inclined surface is formed on the outer edge portion of the metal reflective layer so that the film thickness gradually decreases toward the outer peripheral side. Semiconductor light emitting device.
(9) The second diffusion preventing layer is made of any one of Ti, Ni, Ta, Cr, and Nb, a nitride of the metal, or an alloy containing any of the metals (1) The semiconductor light emitting element of any one of-(8).
(10) Any one of (1) to (9), wherein an inclined surface is formed on the outer edge of the second diffusion prevention layer so that the film thickness gradually decreases toward the outer peripheral side. The semiconductor light emitting device according to item.

(11) The semiconductor light emitting element according to any one of (1) to (10), wherein the stacked semiconductor layer is mainly composed of a gallium nitride based semiconductor.
(12) A lamp comprising the semiconductor light emitting element according to any one of (1) to (11) and a mounting substrate, wherein the mounting substrate has one wiring portion and one wiring on one surface. The semiconductor light emitting device is disposed such that a substrate of the semiconductor light emitting device is opposite to the mounting substrate, and the semiconductor light emitting device One of the electrodes is connected to the one wiring portion, and the other electrode of the semiconductor light emitting element is connected to the other wiring portion.

(13) The method for manufacturing a semiconductor light emitting element according to any one of (1) to (11), wherein one or both of one electrode or the other electrode of the semiconductor light emitting element is formed. The step of forming a first diffusion barrier layer on one or both of the p-type semiconductor layer and the n-type semiconductor layer, heat-treating the first diffusion barrier layer, And a step of laminating a metal reflection layer and a second diffusion prevention layer in this order on one diffusion prevention layer.
(14) A lamp comprising the semiconductor light-emitting device according to any one of (1) to (11).
(15) An electronic device in which the lamp according to (12) or (14) is incorporated.
(16) A mechanical device in which the electronic device according to (15) is incorporated.

  According to said structure, favorable ohmic of a positive / negative electrode part (n-type electrode and / or p-type electrode) and a semiconductor laminated semiconductor layer (n-type semiconductor layer and / or p-type semiconductor layer which touches the said electrode) By providing contact and effectively preventing migration of Ag (silver) to compound semiconductors even under harsh conditions, we provide high-reliability, high-quality semiconductor light-emitting elements, manufacturing methods, lamps, electronic equipment, and mechanical devices can do.

  The semiconductor light-emitting device of the present invention has a structure in which one or both of one electrode and the other electrode is formed by laminating a first diffusion prevention layer, a metal reflection layer, and a second diffusion prevention layer in this order. And the first diffusion prevention layer is composed of an oxide containing any one of In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn, and Ni. The diffusion preventive layer and the second diffusion preventive layer prevent the constituent material of the metal reflective layer from diffusing and prevent the reflectance of the metal reflective layer from decreasing. In particular, even when heat is applied to the electrode during flip chip bonding, it is possible to prevent a reduction in the reflectance of the metal reflective layer without diffusing the constituent material of the metal reflective layer. In addition, the transmittance of the first diffusion prevention layer can be increased to improve the light emission efficiency of the semiconductor light emitting device. Furthermore, the first diffusion prevention layer can be in ohmic contact with the p-type semiconductor layer to increase the conductivity between the p-type electrode and the p-type semiconductor layer, thereby improving the light emission efficiency of the semiconductor light emitting device.

  The semiconductor light emitting device of the present invention has a configuration in which the first diffusion prevention layer is any one of ITO, IZO, AZO, or GZO, so that diffusion of the constituent material of the metal reflection layer is prevented, and the reflectance of the metal reflection layer is reduced. Reduction can be prevented. In addition, the transmittance of the first diffusion prevention layer can be increased to improve the light emission efficiency of the semiconductor light emitting device. Furthermore, the first diffusion prevention layer can be in ohmic contact with the p-type semiconductor layer to increase the conductivity between the p-type electrode and the p-type semiconductor layer, thereby improving the light emission efficiency of the semiconductor light emitting device.

  In the semiconductor light emitting device of the present invention, the metal reflective layer is made of Ag, Rh, or an alloy containing any of the above metals. Therefore, it is possible to increase the reflectance of the metal reflective layer and improve the light emission efficiency of the semiconductor light emitting device. it can.

  The semiconductor light emitting device of the present invention has a configuration in which the inclined surface is formed on the metal reflective layer so that the film thickness gradually decreases toward the outer periphery. Therefore, the second diffusion prevention is performed so as to cover the outer edge of the metal reflective layer. A layer can be formed, and the metal diffusion layer can be covered with a high shielding property by the second diffusion preventing layer, and the metal constituting the metal reflection layer can be prevented from diffusing to the bonding layer side.

  In the semiconductor light emitting device of the present invention, since the second diffusion preventing layer is composed of a metal of any one of Ti, Ni, Ta, Cr, and Nb, a nitride of the metal, or an alloy containing any of the metals, It is possible to prevent the metal constituting the reflective layer from diffusing into the bonding layer.

  The lamp of the present invention is a lamp comprising the semiconductor light-emitting element described above and a mounting substrate, and the mounting substrate is disposed on one surface so as to be separated from one wiring portion and the one wiring portion. The semiconductor light emitting element is disposed such that the substrate is opposite to the mounting substrate, the one electrode is connected to the one wiring portion, Since the other electrode is connected to the other wiring part, the lamp having the semiconductor light emitting device that prevents the diffusion of the constituent material of the metal reflecting layer and prevents the reflectance of the metal reflecting layer from being reduced; can do.

  The method for manufacturing a semiconductor light-emitting device according to the present invention is the method for manufacturing a semiconductor light-emitting device described above, wherein the step of forming one or both of one electrode or the other electrode of the semiconductor light-emitting device is provided. , A step of forming a first diffusion barrier layer on one or both of the p-type semiconductor layer and the n-type semiconductor layer, a step of heat-treating the first diffusion barrier layer, and the first diffusion And a step of laminating the metal reflection layer and the second diffusion prevention layer in this order on the prevention layer. Therefore, the first diffusion prevention layer is crystallized in the heat treatment step to form a constituent material of the metal reflection layer. After improving the anti-diffusion property, transparency and conductivity of the metal, the metal reflective layer can be laminated. Thereby, in order to improve the reflectance of the metal reflection layer, the constituent material of the metal reflection layer can be prevented from diffusing to the p semiconductor layer side even if the metal reflection layer is subsequently heat-treated. In addition, even when heat is applied to the electrode in the lamp manufacturing process, the constituent material of the metal reflective layer can be prevented from diffusing to the p semiconductor layer side. Furthermore, by forming a second diffusion preventing layer on the metal reflective layer, it is possible to prevent the constituent material of the metal reflective layer from diffusing to the bonding layer side when heat is applied to the electrodes in the lamp manufacturing process. it can.

It is a cross-sectional schematic diagram which shows an example of the semiconductor light-emitting device of this invention. FIG. 2 is a schematic plan view of the semiconductor light emitting element shown in FIG. 1. It is a cross-sectional schematic diagram in the B-B 'line of FIG. It is a cross-sectional schematic diagram which shows an example of the laminated semiconductor layer of the semiconductor light-emitting device of this invention. It is an expanded sectional view which shows an example of the p-type electrode of the semiconductor light-emitting device of this invention. It is an example of process sectional drawing of the p-type electrode of the semiconductor light-emitting device of this invention. It is an example of process sectional drawing of the p-type electrode of the semiconductor light-emitting device of this invention. It is an example of process sectional drawing of the p-type electrode of the semiconductor light-emitting device of this invention. It is a cross-sectional schematic diagram which shows an example of the lamp | ramp of this invention.

Hereinafter, modes for carrying out the present invention will be described.
(First embodiment)
1-5 is a figure which shows an example of the semiconductor light-emitting device which is embodiment of this invention. In the drawings to be referred to in the following description, the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationships of actual semiconductor light emitting elements and the like.
FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor light-emitting device according to an embodiment of the present invention, FIG. 2 is a schematic plan view of the semiconductor light-emitting device shown in FIG. 1, and FIG. It is a cross-sectional schematic diagram in a line. 1 is a schematic cross-sectional view taken along line AA ′ of FIG. 4 is a schematic cross-sectional view showing an example of a laminated semiconductor layer constituting the semiconductor light-emitting device shown in FIG. 1, and FIG. 5 is an enlarged cross-sectional view of the p-type electrode of the semiconductor light-emitting device shown in FIG.

(Semiconductor light emitting device)
As shown in FIGS. 1 and 3, in the semiconductor light emitting device 1 according to the embodiment of the present invention, a buffer layer 102, a base layer 103, and a laminated semiconductor layer 20 are sequentially laminated on one surface 101 c of a substrate 101. Configured. The stacked semiconductor layer 20 is configured by stacking an n-type semiconductor layer 104, a light emitting layer 105, and a p-type semiconductor layer 106 in this order from the substrate 101 side.

As shown in FIG. 1, the laminated semiconductor layer 20 has one side surface cut out in a rectangular shape in cross section to form a notch portion 16, and the remaining portion without being cut out serves as a notch remaining portion 17.
In the notch 16, an n-type electrode 108 is formed on one surface 104 c of the n-type semiconductor layer 104. The insulating protective film 10 is formed so as to cover the side surface of the n-type electrode 108, the exposed surface of the one surface 104 c of the n-type semiconductor layer 104, and the side surface of the laminated semiconductor layer 20. Note that the upper surface of the n-type electrode 108 is exposed.

In the notch remaining portion 17, a first diffusion prevention layer 51, a metal reflection layer 52, a second diffusion prevention layer 53, and a surface of the p-type semiconductor layer 106 opposite to the substrate 101 (hereinafter referred to as an upper surface) 106 c, The bonding layer 55 and the insulating protective film 10 are laminated in this order, and a recess 111c is provided so as to remove a part of the insulating protective film 10 and a part of the bonding layer 55, thereby forming a p-type electrode 111. Has been.
The p-type electrode 111 has an inclined shape (hereinafter referred to as a taper shape).
Further, the light emission direction of the semiconductor light emitting element 1 is indicated by an arrow f.

As shown in FIG. 2, the semiconductor light emitting device 1 according to the embodiment of the present invention has a rectangular shape in plan view, and a cutout portion 16 that is cut out in a semicircular semirectangular shape in plan view is provided on one side. The portion left without being cut out is referred to as a notch remaining portion 17.
The notch 16 is provided with an n-type electrode 108 having a circular shape in plan view. The insulating protective film 10 is formed so as to cover the exposed surface of the notch 16. The upper surface of the n-type electrode 108 is exposed, but the side surface of the n-type electrode 108 is covered with the insulating protective film 10.
The notch remaining part 17 is covered with the insulating protective film 10. A concave portion 111 c having a circular shape in plan view is provided in the region of the insulating protective film 10, and the bonding layer 55 is exposed from the concave portion 111 c to constitute the p-type electrode 111.
Hereinafter, each member will be described.

<Board>
The substrate 101 is not particularly limited as long as the substrate 101 is transparent and a group III nitride semiconductor crystal is epitaxially grown on the surface, and various substrates can be selected and used. For example, sapphire, zinc oxide, magnesium oxide, zirconium oxide, magnesium aluminum oxide, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, A substrate made of tungsten, molybdenum, or the like can be used.
Among the above substrates, a sapphire substrate having a c-plane as a main surface is particularly preferable, and the buffer layer 102 may be formed on the c-plane of sapphire.

When the buffer layer 102 is formed by a sputtering method, the buffer layer 102 can be formed without using ammonia, and chemical modification is caused by contact with ammonia at a high temperature among the above substrates. An oxide substrate, a metal substrate, or the like that is known can be used.
In addition, since the temperature of the substrate 101 can be kept low, even when the substrate 101 made of a material that decomposes at a high temperature is used, each layer is formed on the substrate without damaging the substrate 101. Is possible.

<Laminated semiconductor layer>
The laminated semiconductor layer 20 is a layer made of, for example, a group III nitride semiconductor. As shown in FIGS. 1 and 3, the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 are formed on the substrate 101. These layers are laminated in this order. The laminated semiconductor layer 20 may further include a base layer 103 and a buffer layer 102 (however, FIGS. 1 and 3 are illustrated separately).
As shown in FIG. 4, each of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 can be composed of a plurality of semiconductor layers.
Note that the stacked semiconductor layer 20 can be formed with a good crystallinity when formed by the MOCVD method, but by optimizing the conditions also by the sputtering method, a semiconductor layer having a crystallinity superior to that of the MOCVD method can be formed. . Hereinafter, description will be made sequentially.

<Buffer layer>
Buffer layer 102 is preferably made of polycrystalline _{Al x Ga 1-x N (} 0 ≦ x ≦ 1) , and more preferably those of the single crystal _{Al x Ga 1-x N (} 0 ≦ x ≦ 1) .
As described above, the buffer layer 102 can be, for example, made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm. When the thickness of the buffer layer 102 is less than 0.01 μm, the buffer layer 102 may not sufficiently obtain an effect of relaxing the difference in lattice constant between the substrate 101 and the base layer 103. On the other hand, when the thickness of the buffer layer 102 exceeds 0.5 μm, although the function as the buffer layer 102 is not changed, the film forming process time of the buffer layer 102 becomes long and the productivity is lowered.
The buffer layer 102 has a function of relaxing the difference in lattice constant between the substrate 101 and the base layer 103 and facilitating the formation of a C-axis oriented single crystal layer on the (0001) C plane of the substrate 101. Therefore, when the single crystal base layer 103 is stacked over the buffer layer 102, the base layer 103 with higher crystallinity can be stacked. In the present invention, it is preferable to perform the buffer layer forming step, but it may not be performed.

The buffer layer 102 may have a hexagonal crystal structure made of a group III nitride semiconductor. Further, the group III nitride semiconductor crystals forming the buffer layer 102 may have a single crystal structure, and those having a single crystal structure are preferably used. By controlling the growth conditions, the group III nitride semiconductor crystal grows not only in the upward direction but also in the in-plane direction to form a single crystal structure. Therefore, by controlling the film formation conditions of the buffer layer 102, the buffer layer 102 made of a crystal of a group III nitride semiconductor having a single crystal structure can be obtained. When the buffer layer 102 having such a single crystal structure is formed on the substrate 101, the buffer function of the buffer layer 102 works effectively, so that the group III nitride semiconductor formed thereon has a good orientation. It becomes a crystal film having the property and crystallinity.
Further, the group III nitride semiconductor crystal forming the buffer layer 102 can be formed into a columnar crystal (polycrystal) having a texture based on hexagonal columns by controlling the film forming conditions. In addition, the columnar crystal consisting of the texture here is a crystal that is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape. Say.

<Underlayer>
_{Examples of the} base layer 103 include Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1), and Al _x Ga _1-x N (0 ≦ x <1) is preferable because the base layer 103 with good crystallinity can be formed.
The film thickness of the underlayer 103 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is increased.
In order to improve the crystallinity of the base layer 103, the base layer 103 is preferably not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added.

<N-type semiconductor layer>
As shown in FIG. 4, it is preferable that the n-type semiconductor layer 104 is generally composed of an n-contact layer 104a and an n-cladding layer 104b. The n contact layer 104a can also serve as the n clad layer 104b. In addition, the above-described base layer may be included in the n-type semiconductor layer 104.
The n contact layer 104a is a layer for providing an n-type electrode. The n contact layer 104a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). .
The n contact layer 104a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm. ^If it contains in the density | concentration of ³ , it is preferable at the point of the maintenance of favorable ohmic contact with an n-type electrode. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.
The thickness of the n contact layer 104a is preferably 0.5 to 5 μm, and more preferably set to a range of 1 to 3 μm. When the film thickness of the n-contact layer 104a is in the above range, the semiconductor crystallinity is maintained well.

An n-clad layer 104b is preferably provided between the n-contact layer 104a and the light-emitting layer 105. The n-clad layer 104b is a layer that injects carriers into the light emitting layer 105 and confines carriers. The n-clad layer 104b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. Needless to say, when the n-cladding layer 104b is formed of GaInN, it is desirable to make it larger than the band gap of GaInN of the light emitting layer 105.
The film thickness of the n-clad layer 104b is not particularly limited, but is preferably 0.005 to 0.5 μm, and more preferably 0.005 to 0.1 μm. The n-type doping concentration of the n-clad layer 104b is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.

When the n-cladding layer 104b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 100 mm or less, It may include a structure in which an n-side second layer made of a group III nitride semiconductor having a composition different from that of the n-side first layer and having a thickness of 100 mm or less is stacked.
The n-clad layer 104b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. Preferably, either the n-side first layer or the n-side second layer is in contact with the active layer (light-emitting layer 105).

<Light emitting layer>
As the light emitting layer 105 stacked on the n-type semiconductor layer 104, there is a light emitting layer 105 having a single quantum well structure or a multiple quantum well structure.
As the well layer 105b having a quantum well structure as shown in FIG. 4, a group III nitride semiconductor layer made of Ga _1-y In _y N (0 <y <0.4) is usually used. The film thickness of the well layer 105b can be set to a film thickness that provides a quantum effect, for example, 1 to 10 nm, and preferably 2 to 6 nm, from the viewpoint of light emission output.
In the case of the light emitting layer 105 having a multiple quantum well structure, the Ga _1-y In _y N is used as the well layer 105b, and Al _z Ga _1-z N (0 ≦ z <0) having a larger band gap energy than the well layer 105b. .3) is defined as a barrier layer 105a. The well layer 105b and the barrier layer 105a may or may not be doped with impurities by design.

<P-type semiconductor layer>
As shown in FIG. 4, the p-type semiconductor layer 106 is generally composed of a p-clad layer 106a and a p-contact layer 106b. The p contact layer 106b can also serve as the p clad layer 106a.
The p-cladding layer 106a is a layer for confining carriers in the light emitting layer 105 and injecting carriers. The p-cladding layer 106a is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 105 and can confine carriers in the light-emitting layer 105, but is preferably Al _x Ga _1-x N. (0 <x ≦ 0.4).
When the p-clad layer 106a is made of such AlGaN, it is preferable in terms of confining carriers in the light-emitting layer. The thickness of the p-clad layer 106a is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm.
The p-type doping concentration of the p-clad layer 106a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
The p-clad layer 106a may have a superlattice structure in which a plurality of layers are stacked.

  When the p-cladding layer 106a is a layer including a superlattice structure, a detailed illustration is omitted, but a p-side first layer made of a group III nitride semiconductor having a thickness of 100 mm or less, It may include a structure in which a p-side second layer made of a group III nitride semiconductor having a composition different from that of the p-side first layer and having a thickness of 100 mm or less is stacked. Further, it may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.

The p contact layer 106b is a layer for providing a positive electrode. The p contact layer 106b is preferably Al _x Ga _1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the p ohmic electrode.
When a p-type impurity (dopant) is contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact can be obtained. It is preferable in terms of maintenance, prevention of crack generation, and good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.
The thickness of the p contact layer 106b is not particularly limited, but is preferably 0.01 to 0.5 μm, and more preferably 0.05 to 0.2 μm. When the film thickness of the p-contact layer 106b is within this range, it is preferable in terms of light emission output.

<P-type electrode>
FIG. 5 is an enlarged cross-sectional view showing an example of the p-type electrode 111 of the semiconductor light emitting device 1 according to the embodiment of the present invention shown in FIG.
As shown in FIG. 5, the p-type electrode 111 includes a first diffusion prevention layer 51, a metal reflection layer 52, a second diffusion prevention layer 53, a bonding layer 55, and an insulating protective film 10. It is roughly structured.

<First diffusion preventing layer>
As shown in FIG. 5, the first diffusion prevention layer 51 is formed on the upper surface 106 c of the p-type semiconductor layer 106. Further, an inclined surface 51e is formed on the outer edge 51f so that the film thickness gradually decreases toward the outer periphery 50g.

  The first diffusion prevention layer 51 is preferably made of an oxide containing any one of In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn, and Ni. Indium oxide, zinc Oxides or titanium oxides are particularly preferred. Since these materials are excellent in transparency (translucency) and conductivity, the transparency and conductivity of the first diffusion prevention layer 51 are increased, and the light emission efficiency of the semiconductor light emitting device is improved.

The conductive indium oxide may have any composition as long as it is a transparent conductive material containing an indium element in the oxide. For example, ITO (Indium Tin Oxide (In ₂ O ₃ —SnO ₂ )) ), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (gallium indium oxide (In ₂ O ₃ —Ga ₂ O ₃ )). Also. Examples of the conductive titanium oxide include niobium-doped titanium oxide. Still other transparent conductive materials include AZO (aluminum zinc oxide (ZnO—Al ₂ O ₃ )), GZO (gallium zinc oxide (ZnO—Ga ₂ O ₃ )), fluorine-doped tin oxide, niobium-doped titanium oxide, and the like. Can be used. In particular, the first diffusion prevention layer 51 is preferably any one of ITO, IZO, AZO, or GZO.

The first diffusion preventing layer 51 may be in an amorphous state, but it is preferable to use a crystallized film. By using the crystallized film, the transparency and conductivity of the first diffusion preventing layer 51 can be further increased, and the light emission efficiency of the semiconductor light emitting element can be further improved. As a crystallized film of ITO or IZO, for example, a film containing In ₂ O ₃ crystal having a hexagonal crystal structure or a bixbite structure can be given.
Note that the crystallized film may be formed by heat-treating the first diffusion prevention layer 51 formed in an amorphous state. Usually, the first diffusion prevention layer 51 immediately after film formation is in an amorphous state, but if it is thermally annealed under predetermined conditions, it can be changed to a crystallized film.

The maximum thickness of the first diffusion preventing layer 51 is preferably 1 nm to 500 nm, more preferably 2 nm to 100 nm, and further preferably 3 nm to 20 nm. By setting the maximum thickness of the first diffusion preventing layer 51 to 1 nm to 500 nm, diffusion can be prevented to a bonding layer of a metal material such as Ag constituting the metal reflection layer 52 described later.
Further, the first diffusion preventing layer 51 can be formed using conventional means well known in this technical field.

<Metal reflective layer>
As shown in FIG. 5, the metal reflection layer 52 is formed so as to completely cover the first diffusion prevention layer 51. In addition, an inclined surface 52e is formed on the outer edge 52f so that the film thickness gradually decreases toward the outer periphery 50g.

  The metal reflective layer 52 is preferably made of Ag or Rh or an alloy containing any of the above metals. Since an alloy containing either Ag or Rh or the above metal is a highly reflective metal, light from the light emitting layer 105 can be effectively reflected. Moreover, it is general as a material for electrodes, and is excellent in terms of easy availability and easy handling.

  The metal reflection layer 52 is preferably a known APC alloy or ANC alloy. An APC alloy or an ANC alloy is an alloy containing Ag, has a high light reflectivity, and is excellent in terms of easy availability and handling.

  The maximum thickness of the metal reflective layer 52 is desirably 20 to 3000 nm, more desirably 50 to 2000 nm, and most desirably 100 to 1500 nm. If the metal reflection layer 52 is too thin, a sufficient reflection effect cannot be obtained. On the other hand, if it is too thick, there is no particular advantage, and only a long process time and material waste are caused.

  The metal reflection layer 52 is preferably formed in close contact with the first diffusion preventing layer 51. As a result, the metal reflection layer 52 can be firmly bonded to the first diffusion prevention layer 51, and the bonding strength between the metal reflection layer 52 and the first diffusion prevention layer 51 can be increased, and the p-type electrode 111. It is possible to increase the bonding strength. Moreover, the light from the light emitting layer 105 can be reflected efficiently.

<Second diffusion prevention layer>
As shown in FIG. 5, a second diffusion prevention layer 53 is formed so as to completely cover the metal reflection layer 52. Further, an inclined surface 53e is formed on the outer edge 53f so that the film thickness gradually decreases toward the outer periphery 53g.

  The second diffusion preventing layer 53 is preferably made of any one of Ti, Ni, Ta, Cr, and Nb, a nitride of the metal, or an alloy containing any of the metals. By using these materials as the second diffusion preventing layer 53, it is possible to prevent the metal material such as Ag constituting the metal reflection layer 52 from diffusing to the bonding layer 55 side.

The maximum thickness of the second diffusion preventing layer 53 is preferably in the range of 50 nm or more, more preferably in the range of 100 nm or more, and further preferably in the range of 200 nm or more.
By setting the maximum thickness of the second diffusion preventing layer 53 in the range of 50 nm or more, diffusion can be prevented to a bonding layer of a metal material such as Ag constituting the metal reflection layer 52. The maximum thickness of the second diffusion preventing layer 53 is preferably thinner than 5000 nm from the viewpoint of material cost.

<Bonding layer>
As shown in FIG. 5, the bonding layer 55 is formed so as to completely cover the second diffusion preventing layer 53. Furthermore, an inclined surface 55e is formed on the outer edge portion 55f so that the film thickness gradually decreases toward the outer peripheral 55g side. The bonding layer 55 may be formed so as to completely cover the second diffusion prevention layer 53 through a layer made of an arbitrary material.

The bonding layer 55 is preferably made of a metal of Au or Al or an alloy containing any of the metals, and more preferably made of Au.
Since Au and Al have high adhesion to bumps (solder balls, bonding balls), when bonded to the mounting substrate via the bumps, the mounting substrate and the bonding layer 55 are firmly bonded to each other. The light emitting element 1 is not easily peeled off from the mounting substrate.

The maximum thickness of the bonding layer 55 is preferably 50 nm to 2000 nm, more preferably 100 nm to 1500 nm, and still more preferably 200 nm to 1000 nm.
If the maximum thickness of the bonding layer 55 is less than 50 nm, the adhesion with the bonding ball is deteriorated. Further, even if the maximum thickness of the bonding layer 55 is greater than 2000 nm, there is no particular advantage, and this only increases the cost.

<Insulating protective film>
The insulating protective film is not always necessary, but is preferably used from the viewpoint of reliability.
As shown in FIG. 5, the insulating protective film 10 is formed so as to cover the bonding layer 55. The insulating protective film 10 may be formed so as to cover the bonding layer 55 through a layer made of an arbitrary material. Furthermore, an inclined surface 10e may be formed on the outer edge portion 10f of the insulating protective film 10 such that the film thickness gradually decreases toward the outer periphery 10g.
Further, as shown in FIG. 1, the insulating protective film 10 includes an upper surface 106c of the p-type semiconductor layer 106, an exposed side surface of the laminated semiconductor 20, an exposed surface 104c of the n-type semiconductor layer 104, a side surface of the n-type electrode 108, and the like. It is formed to cover completely.

The insulating protective film 10 may be an insulating protective film, and examples thereof include a film made of silicon oxide such as SiO ₂ .
The maximum thickness of the insulating protective film 10 is preferably 50 nm to 1000 nm, more preferably 100 nm to 500 nm, and still more preferably 150 nm to 450 nm.

<Recess>
As shown in FIGS. 1 and 5, a concave portion 111c having a rectangular shape in cross section and a circular shape in plan view is formed so as to penetrate the insulating protective film 10 and partially expose the bonding layer 55, and an inner bottom surface 111d. Is exposed.

  The diameter of the inner bottom surface 111d of the recess 111c is preferably 60 to 100 μm. As a result, the area of the inner bottom surface 111d of the recess 111c can be made slightly larger than the diameter of the bumps used in manufacturing the lamp, and the mounting operation can be facilitated. When the diameter of the inner bottom surface 111d is larger than 100 μm, the mounting operation becomes easier, but the area for forming the insulating protective film is reduced, and the effect of the insulating protective film may be impaired, and reliability as a semiconductor light emitting device Decreases. Conversely, if the diameter of the inner bottom surface 111d is smaller than 60 μm, the mounting operation becomes difficult and the production yield of the product is lowered.

  Note that the position of the recess 111 c of the p-type electrode 111 is not limited to the position shown in FIG. 1 and may be formed anywhere as long as it is the upper surface 106 c of the p-type semiconductor layer 106. For example, it may be formed at a position farthest from the n-type electrode 108 or may be formed at the center of the semiconductor light emitting element 1.

<N-type electrode>
As shown in FIGS. 1 to 3, a cylindrical n-type electrode 108 is formed on one surface 104 c of the n-type semiconductor layer 104. The side surface of the n-type electrode 108 is covered with the insulating protective film 10, but the upper surface 108c is exposed. The upper surface 108c also serves as a bonding pad, and the mounting substrate can be bonded through bumps.
As a material and a configuration of the n-type electrode 108, a well-known electrode material and electrode structure such as a two-layer structure made of Ti / Au can be used, and a formation method thereof is a well-known conventional method well known in this technical field. Means can be used.
The shape of the n-type electrode 108 is not limited to a cylindrical shape, and may be a polygonal column shape.

  Although not shown in the present embodiment, the n-type electrode 108 can have the same configuration as the p-type electrode 111. That is, similarly to the p-type electrode 111, the n-type electrode 108 may have a structure including an inclined surface that gradually decreases in thickness toward the outer peripheral side, and the ohmic contact layer 51 (first diffusion prevention layer). 51), a metal reflection layer 52, a second diffusion prevention layer 53, and a bonding layer 55. Thus, external air or moisture can be prevented from entering the interface between the n-type electrode 108 and the n-type semiconductor layer 104, and the corrosion resistance of the n-type electrode 108 can be improved.

(Manufacturing method of semiconductor light emitting device)
Next, an example of a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention will be described.
<Laminated semiconductor layer forming step>
First, a substrate 101 such as a sapphire substrate is prepared, and a buffer layer 102 is laminated on the upper surface of the substrate 101 by sputtering. In the chamber, pretreatment may be performed to clean the upper surface by exposing the substrate 101 to Ar or N ₂ plasma.
When the buffer layer 102 having a single crystal structure is formed by sputtering, the ratio of the nitrogen flow rate to the nitrogen source flow rate in the chamber and the flow rate of the inert gas is 50% to 100%, preferably about 75%. It is desirable to be
Note that the buffer layer 102 may be formed not only by the sputtering method described above but also by a known MOCVD method.

Next, a single crystal base layer 103 is formed on the upper surface of the buffer layer 102.
The base layer 103 is preferably formed using a sputtering method. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.

  The temperature of the substrate 101 when the base layer 103 is formed, that is, the growth temperature of the base layer 103 is preferably 800 ° C. or higher, more preferably 900 ° C. or higher, and 1000 ° C. or higher. Most preferably. This is because by increasing the temperature of the substrate 101 when forming the base layer 103, atom migration easily occurs and dislocation looping easily proceeds. In addition, the temperature of the substrate 101 when the base layer 103 is formed needs to be lower than the temperature at which the crystal is decomposed, and is preferably less than 1200 ° C. If the temperature of the substrate 101 when forming the base layer 103 is within the above temperature range, the base layer 103 with good crystallinity can be obtained.

Next, an n-type semiconductor layer 104 is formed on the base layer 103 by laminating an n-contact layer 104a and an n-cladding layer 104b. For example, sputtering or MOCVD is used.
Next, the light emitting layer 105 is formed over the n-type semiconductor layer 104. A sputtering method or an MOCVD method is preferably used, and an MOCVD method is more preferably used.
Specifically, the barrier layers 105a and the well layers 105b are alternately and repeatedly stacked, and the barrier layers 105a may be stacked in the order in which the barrier layers 105a are disposed on the n-type semiconductor layer 104 side and the p-type semiconductor layer 106 side. .

Next, the p-type semiconductor layer 106 is formed over the light emitting layer 105. For example, sputtering or MOCVD is used. Specifically, the p-cladding layer 106a and the p-contact layer 106b may be sequentially stacked.
Through the above steps, the buffer layer 102, the base layer 103, and the stacked semiconductor layer 20 are formed on the one surface 101c of the substrate 101.

<Electrode formation process>
The p-type electrode forming step of the present embodiment includes a step of forming a first diffusion preventing layer on the p-type semiconductor layer (hereinafter referred to as a first step), a metal reflective layer and a first layer on the first diffusion preventing layer. And a step of laminating the two diffusion prevention layers in this order (hereinafter referred to as the second step), and a step of laminating the bonding layer and the insulating protective film in this order (hereinafter referred to as the third step).
In addition, you may include the process (henceforth a 4th process) which heat-processes the said 1st diffusion prevention layer in the said p-type electrode formation process. Further, a step of stacking an insulating protective film on the bonding layer (hereinafter referred to as a fifth step) may be performed.
First, the formation process of a p-type electrode is demonstrated using process sectional drawing shown to FIGS.

<First step>
First, as shown in FIG. 6A, a resist is applied to the upper surface 106 c of the p-type semiconductor layer 106, and this is dried to form the insoluble resist portion 21. For example, AZ5200NJ (product name: manufactured by AZ Electronic Materials Co., Ltd.) is used as the resist.

Next, in order to cover the position where the p-type electrode is formed on the front surface of the resist portion 21, a substantially rectangular mask (hereinafter referred to as p-type electrode forming) having a length of 1 ₁ on one side and a length of _{2 on} the other side. Place a mask.
Next, as shown in FIG. 6B, light having a predetermined intensity and wavelength is irradiated as indicated by an arrow to expose a portion of the resist portion 21 that is not covered by the mask 25 (partial exposure). . The exposed resist portion 21 is converted into a first soluble resist portion 22 by a photoreaction. Since this photoreaction proceeds according to the intensity of light, the photoreaction progresses quickly on the light irradiation surface side, and the photoreaction progresses slowly on the p-type semiconductor layer 106 side. Therefore, the first soluble resist portion 22 is formed so as to have an inversely inclined shape (an inversely tapered shape) that recedes as its side faces downward. Conversely, the masked portion of the insoluble resist portion 21 is formed to have an inclined shape (tapered shape) that recedes as the side faces upward.

Next, the substrate 101 on which the first soluble resist portion 22 is formed is heated using, for example, a hot plate or an oven. The first soluble resist portion 22 is cross-linked by the thermal reaction accompanying this heating, and becomes a cured resist portion 23 made of a cross-linked polymer as shown in FIG.
Next, as shown in FIG. 7A, light having a predetermined intensity and wavelength is irradiated as indicated by an arrow without using a mask (entire exposure). As a result, the insoluble resist portion 21 that has not been exposed in the partial exposure becomes the second soluble resist portion 24.

Next, the second soluble resist portion 24 is dissolved and removed using a predetermined organic solvent. Thereby, as shown in FIG.7 (b), the cured resist part 23 which consists of a bridge | crosslinking polymer is left. The cured resist portion 23 includes an opening 27 c having a width l ₁ that exposes the upper surface 106 c of the p-type semiconductor layer 106. The opening 27c is formed in a substantially rectangular shape having a length l ₁ on _one side and a length l _{2 on} the other side. The side surface (inner wall surface) 27d of the opening 27c has an inversely inclined shape (inversely tapered shape) that recedes as it goes downward, and the area of the opening 27c increases as it approaches the p-type semiconductor layer 106. The inclination angle of the side surface 27d of the opening 27c is substantially constant. This is referred to as a mask 27.

Next, as shown in FIG. 7C, the first diffusion prevention layer 51 is formed on the upper surface 106c of the p-type semiconductor layer 106 through the mask 27 by sputtering.
The first diffusion prevention layer 51 is slightly wider than the lengths l ₁ and l ₂ of each side of the opening 27 c of the mask 27 and extends to the vicinity of the inner wall surface 27 d of the mask 27 on the upper surface 106 c of the p-type semiconductor layer 106. Formed. Further, since the inner wall surface 27d of the opening 27c of the mask 27 recedes as it goes downward, the outer peripheral portion 51g is formed in a portion that is shaded from the sputtering direction, that is, in the outer edge portion 51f of the first diffusion prevention layer 51. An inclined surface 51e is formed so that the film thickness gradually decreases toward the side. The inclination angle of the inclined surface 51e is determined according to the film thickness.

<Second step>
Next, the metal reflective layer 52 is formed on the first diffusion preventing layer 51 through the mask 27 by sputtering.
In the formation of the metal reflection layer 52, the sputtering method is used as in the case of the first diffusion prevention layer 51. Therefore, the metal reflection layer 52 is slightly wider than the lengths l ₁ and l ₂ of each side of the opening 27 c of the mask 27 and extends to the vicinity of the inner wall surface 27 d of the mask 27 on the upper surface 106 c of the p-type semiconductor layer 106. It is formed.
Further, since the inner wall surface 27d of the opening 27c of the mask 27 recedes toward the lower side, as shown in FIG. 8A, in the portion shadowed from the sputtering direction, that is, the outer edge of the metal reflective layer 52 An inclined surface 52e is formed on the portion 52f so that the film thickness gradually decreases toward the outer periphery 52g. The inclination angle of the inclined surface 52e is determined according to the film thickness.
The metal reflection layer 52 is formed so as to completely cover the first diffusion preventing layer 51.

  In addition, before forming the metal reflective layer 52, a pretreatment for cleaning the surface of the first diffusion preventing layer 51 may be performed. As a cleaning method, there are a dry process that is exposed to plasma or the like and a wet process that is brought into contact with a chemical solution. The dry process is desirable from the viewpoint of simplicity of the process.

In addition, when forming into a film using Ag or an Ag alloy as the metal reflective layer 52, it is preferable to perform heat treatment (annealing) after the film formation. Thereby, the reflectance of the metal reflective layer 52 can be increased. For example, when heat treatment is performed at 380 to 400 ° C., the reflectance of the metal reflective layer 52 is improved by about 8%. This is because the metal reflection layer 52 is surrounded by the first diffusion prevention layer 51 and the second diffusion prevention layer 53, so that Ag does not diffuse during heat treatment, and the density of the metal reflection layer 52 increases. I guess it was because of this.
The heat treatment may be performed as an independent process, or may be performed by heating the electrode at the time of flip chip connection.

Next, a second diffusion preventing layer 53 is formed on the metal reflective layer 52 through the mask 27 by sputtering.
In the formation of the second diffusion prevention layer 53, a sputtering method is used as in the case of the first diffusion prevention layer 51. Therefore, the second diffusion prevention layer 53 is slightly wider than the lengths l ₁ and l ₂ of each side of the opening 27c of the mask 27, and is near the inner wall surface 27d of the mask 27 on the upper surface 106c of the p-type semiconductor layer 106. It is spread and formed.
Further, since the inner wall surface 27d of the opening 27c of the mask 27 recedes toward the lower side, as shown in FIG. 8B, in the portion that is shaded from the sputtering direction, that is, the second diffusion preventing layer. An inclined surface 53e is formed on the outer edge 53f of 53 so that the film thickness gradually decreases toward the outer periphery 53g. The inclination angle of the inclined surface 53e is determined according to the film thickness.
The second diffusion preventing layer 53 is formed so as to completely cover the metal reflective layer 52.

<Third step>
Next, a bonding layer 55 is formed on the second diffusion prevention layer 53 through the mask 27 by sputtering.
In the formation of the bonding layer 55, a sputtering method is used as in the case of the first diffusion prevention layer 51.
Further, since the inner wall surface 27d of the opening 27c of the mask 27 recedes as it goes downward, the portion that is shaded from the sputtering direction, that is, the outer edge 55f of the bonding layer 55 is directed toward the outer periphery 55g. An inclined surface 55e is formed so that the film thickness is gradually reduced. The inclination angle of the inclined surface 55e is determined according to the film thickness.
The bonding layer 55 is formed so as to completely cover the second diffusion preventing layer 53.

  Next, the first diffusion prevention layer 51, the metal reflection layer 52, and the second diffusion prevention layer 53 formed on the upper surface 106c of the p-type semiconductor layer 106 are removed by removing the mask 27 using a resist stripping material or the like. Thus, a four-layer structure composed of the bonding layer 55 is formed.

  Next, by using a photolithography method, a recess 111c is formed by etching in a predetermined region of the p-type electrode 111 to expose the inner bottom surface 111d. Thereby, the p-type electrode 111 in which the first diffusion prevention layer 51, the metal reflection layer 52, the second diffusion prevention layer 53, and the bonding layer 55 are stacked and the recess 111c is provided is formed on the upper surface of the p-type semiconductor layer 106. 106c. Further, the insulating protective film 10 is optionally laminated on the bonding layer 55 (also referred to as a fifth step).

<4th process>
Next, heat treatment (annealing) of the first diffusion preventing layer 51 can be arbitrarily performed. By heat treatment, the crystallinity of the first diffusion prevention layer 51 can be increased, and the transparency and conductivity of the first diffusion prevention layer 51 can be improved.

Next, an n-type electrode forming process will be described.
First, using a photolithography method, the laminated semiconductor layer 20 in a predetermined region is etched to form the notch 16 so that a part of the n-type semiconductor layer is exposed. Thereby, one surface 104c of the n-type semiconductor layer 104 is exposed. Note that the one surface 104c is preferably formed on the n-contact layer 104a.
Next, the n-type electrode 108 is formed on the one surface 104c of the n-type semiconductor layer 104 by using a sputtering method or the like.
Next, the insulating protective film 10 is formed so as to cover the side surface of the laminated semiconductor layer 20 on the side of the notch 16, the exposed surface 104 c of the n-type semiconductor layer 104, and the side surface of the n-type electrode 108.
Finally, the upper surface of the n-type electrode 108 is exposed using a photolithography method.
As described above, the semiconductor light emitting device 1 shown in FIGS. 1 to 5 is manufactured.

Note that the order of the n-type electrode formation step and the p-type electrode formation step may be first, and some steps may be performed simultaneously.
Moreover, the same metal element may be used for the metal element used for each layer of the p-type electrode 111, and different metal elements may be combined.

  A semiconductor light emitting device 1 according to an embodiment of the present invention includes a substrate 101, a laminated semiconductor layer 20 in which an n-type semiconductor layer 104, a light emitting layer 105, and a p-type semiconductor layer 106 are laminated on the substrate 101 in this order. , A semiconductor light emitting device 1 including one electrode 111 bonded to the p-type semiconductor layer 106 and the other electrode 108 bonded to the n-type semiconductor layer 104, wherein one electrode 111 or the other electrode One or both of 108 has a structure in which the first diffusion prevention layer 51, the metal reflection layer 52, and the second diffusion prevention layer 53 are laminated in this order, and the first diffusion prevention layer 51 has The first diffusion prevention layer 51 and the second diffusion prevention layer 53 are composed of an oxide containing any metal of In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn, and Ni. And Ag of the metal reflective layer 52 Which metal material is prevented from diffusing into the p-type semiconductor layer 106 side and the bonding layer 55 side can be suppressed to reduce the reflectance of the metal reflective layer 52. In particular, even when heat is applied to the electrodes during flip chip bonding, it is possible to suppress a reduction in the reflectance of the metal reflective layer 52. Further, the light transmittance of the first diffusion preventing layer 51 is high, and the light from the light emitting layer 105 is efficiently extracted toward the metal reflection layer 52, and the light reflected by the metal reflection layer 52 is efficiently extracted toward the substrate 101. The light emission efficiency of the semiconductor light emitting device can be improved. Further, the contact resistance between the first diffusion prevention layer 51 and the p-type semiconductor layer 106 is smaller than the contact resistance between the metal reflection layer 52 and the p-type semiconductor layer 106, and the first diffusion prevention layer 51. Can be brought into ohmic contact with the p-type semiconductor layer 106 to ensure conductivity from the p-type electrode to the p-type semiconductor layer 106, thereby improving the light-emitting characteristics of the semiconductor light-emitting element.

  In the semiconductor light emitting device 1 according to the embodiment of the present invention, since the first diffusion prevention layer 51 is preferably composed of ITO, IZO, AZO, or GZO, the diffusion of the material of the metal reflective layer 52 is prevented, and the metal It is possible to improve the luminous efficiency of the semiconductor light emitting element 1 by suppressing the reduction of the reflectance of the reflective layer 52.

  The semiconductor light emitting device 1 according to the embodiment of the present invention has a configuration in which the maximum thickness of the first diffusion preventing layer 51 is preferably 1 to 500 nm. It can be set as the electrode which suppressed the reduction | decrease of the reflectance of the layer 52. FIG. In addition, light can be transmitted efficiently, and the light emission characteristics of the semiconductor light emitting element can be improved.

  In the semiconductor light emitting device 1 according to the embodiment of the present invention, the metal reflective layer 52 is preferably composed of Ag, Rh, or an alloy containing any of the above metals, so that the reflectance of the metal reflective layer 52 is increased and light is emitted. The light emission characteristics of the semiconductor light emitting device 1 can be improved by efficiently reflecting the light.

  In the semiconductor light emitting device 1 according to the embodiment of the present invention, since the metal reflective layer 52 is preferably an APC alloy or an ANC alloy, the reflectivity of the metal reflective layer 52 is increased, and light is efficiently reflected. The light emission characteristics of the light emitting element 1 can be improved.

  Since the semiconductor light emitting device 1 according to the embodiment of the present invention has a configuration in which the maximum thickness of the metal reflection layer 52 is preferably 20 to 3000 nm, the reflectance of the metal reflection layer 52 is increased and light is efficiently reflected. The light emission characteristics of the semiconductor light emitting device 1 can be improved.

  The semiconductor light emitting device 1 according to the embodiment of the present invention has a configuration in which an inclined surface 52e is formed on the outer edge portion of the metal reflective layer 52, preferably with a gradually decreasing thickness toward the outer peripheral side. The second diffusion preventing layer 53 formed on the 52 can cover the metal reflective layer 52 with high shielding properties.

  In the semiconductor light emitting device 1 according to the embodiment of the present invention, the second diffusion prevention layer 53 is preferably made of any one of Ti, Ni, Ta, Cr, and Nb, the metal nitride, or the metal. The second diffusion prevention layer 53 prevents the diffusion of the material of the metal reflection layer 52 to the bonding layer 55 side and suppresses the reduction of the reflectivity of the metal reflection layer 52 because it is composed of an alloy including the electrode. Can do. In particular, even when heat is applied to the electrodes during flip chip bonding, it is possible to suppress a reduction in the reflectance of the metal reflective layer 52.

  The semiconductor light emitting device 1 according to the embodiment of the present invention has a configuration in which an inclined surface is formed on the outer edge portion of the second diffusion prevention layer 53 so that the thickness gradually decreases toward the outer peripheral side. The bonding layer 55 formed on the second diffusion barrier layer 53 can cover the second diffusion barrier layer 53 with high shielding properties.

  Since the semiconductor light emitting device 1 according to the embodiment of the present invention has a configuration in which the laminated semiconductor layer 20 is mainly composed of a gallium nitride based semiconductor, it can be a semiconductor light emitting device with high light emission efficiency.

In the method for manufacturing a semiconductor light emitting device of the present invention, the step of forming either one or both of one electrode or the other electrode is performed by either one or both of the p-type semiconductor layer 111 and the n-type semiconductor layer 108. A step of forming the first diffusion prevention layer 51 on the layer, and a step of laminating the metal reflection layer 52 and the second diffusion prevention layer 53 on the first diffusion prevention layer 51 in this order. In addition, a step of optionally heat-treating the first diffusion prevention layer 51 may be included.
In the heat treatment step, after the first diffusion prevention layer 51 is crystallized to improve the diffusion prevention property, transparency, and conductivity of the constituent material of the metal reflection layer 52, the metal reflection layer 52 can be laminated. . Thereby, in order to improve the reflectance of the metal reflective layer 52, even if the metal reflective layer 52 is subsequently heat-treated, the constituent material of the metal reflective layer 52 can be prevented from diffusing to the p semiconductor layer 106 side. Further, even if heat is applied to the p-type electrode 111 in the lamp manufacturing process, the constituent material of the metal reflective layer 52 can be prevented from diffusing to the p semiconductor layer 106 side. Further, by forming the second diffusion preventing layer 53 on the metal reflective layer 52, when heat is applied to the p-type electrode 111 in the lamp manufacturing process, the constituent material of the metal reflective layer 52 is the bonding layer 55. It is also possible to prevent diffusion to the side. Thereby, the semiconductor light emitting device 1 with improved light emission efficiency can be easily manufactured.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view showing an example of a lamp according to an embodiment of the present invention.
As shown in FIG. 9, the lamp 4 according to the embodiment of the present invention is a substrate mounting chip type, and the semiconductor light emitting device 1 shown in the first embodiment is used.
The lamp 4 according to the embodiment of the present invention is, for example, a combination of the semiconductor light emitting element 1 and a phosphor, and can have a configuration well known to those skilled in the art by means well known to those skilled in the art. Further, it is known that the emission color can be changed by combining the semiconductor light emitting element 1 and the phosphor, but such a technique is adopted without any limitation in the lamp which is an embodiment of the present invention. It is possible.

  In the lamp 4 according to the embodiment of the present invention, another lead wire 62 and one lead wire 63 are disposed on one surface 61a of a mounting substrate 61 using white alumina ceramics with high visible light reflectance. One end 62a and one end 63a thereof are located at substantially the center of the mounting substrate 61, and the other end 62b and the other end 63b are respectively exposed to the outside and serve as electrodes to be soldered when mounted on the electric substrate.

  The semiconductor light emitting device 1 is arranged such that one electrode (p-type electrode) 111 and the other electrode (n-type electrode) 108 face the one surface 61 a of the mounting substrate 61. That is, the semiconductor light emitting element 1 is arranged (flip chip arrangement) so that the substrate 101 side is opposite to the mounting substrate 61. Therefore, the light from the semiconductor light emitting element 1 is mainly emitted from the mounting substrate side toward the substrate 101 side.

  The p-type electrode 111 and the n-type electrode 108 of the semiconductor light emitting device 1 are joined to one end 62 a of another lead wire 62 and one end 63 a of one lead wire 63 by a bump 74, respectively. Thereby, the p-type electrode 111 of the semiconductor light emitting element 1 is electrically connected to one lead wire 63, and the n-type electrode 108 is electrically connected to another lead wire 62.

  A rectangular parallelepiped wall member 70 is fixed on the substrate 61. At the center of the wall member 70, a bowl-shaped hole 70a for holding the semiconductor light emitting element 1 is formed. The inclined surface 70b of the hole 70a is formed of a white or metallic glossy surface having a high visible light reflectivity, and its curved surface shape is determined in consideration of the light reflection direction to extract light forward. A reflecting surface (reflector surface) is used.

  A transparent sealing resin (mold) 76 covers the semiconductor light emitting element 1 disposed inside the hole 70a in a dome shape. Further, another transparent sealing resin (mold) 78 is filled in the hole 70 a so as to cover the sealing resin 76.

The material of the sealing resins 76 and 78 is preferably a silicone resin having high heat resistance, but may be another resin such as a polycarbonate resin or an epoxy resin, or a transparent material such as glass. It is preferable to select a material with as little deterioration by ultraviolet light as possible.
As the sealing resins 76 and 78, the same resin may be used or different resins may be used. However, it is preferable to use the same resin from the viewpoint of ease of manufacture and good adhesion.
Further, phosphors may be dispersed in the sealing resins 76 and 78. Thereby, various light emission colors can be exhibited, and in the case of white light emission, color rendering can be enhanced.

The mounting substrate 61 and / or the wall member 70 preferably includes a resin member or a ceramic member. Resin members are inexpensive and can reduce manufacturing costs. In particular, by using a thermosetting resin, it can be made excellent in heat resistance. As the resin, for example, high heat resistance and high reflectance nylon resin, white silicone resin, or the like is used. Moreover, since the ceramic member is very excellent in heat resistance, it can be made excellent in heat resistance.
In addition, it is good also as a chip-on-board type device which used the epoxy substrate containing glass (henceforth a wiring board) printed and wired as the mounting board | substrate 61, and mounted the semiconductor light-emitting device 1 directly on the said wiring board.
In this embodiment, the bump 74 is used for bonding, but eutectic bonding may be used.

  The lamp 4 according to the embodiment of the present invention includes a substrate 101, a laminated semiconductor layer 20 in which an n-type semiconductor layer 104, a light emitting layer 105, and a p-type semiconductor layer 106 are laminated in this order on the substrate 101, and p A lamp 4 including a semiconductor light emitting element 1 including one electrode 111 bonded to the type semiconductor layer 106 and the other electrode 108 bonded to the n-type semiconductor layer 104, and a mounting substrate 61. The mounting substrate 61 includes one wiring portion 63 on one surface and another wiring portion 62 that is spaced apart from the one wiring portion 63. In the semiconductor light emitting device 1, the substrate 101 is the mounting substrate 61. The other electrode 108 is connected to the other wiring part 62 and the other electrode 108 is connected to the other wiring part 62, so that one of the electrodes 111 is connected to the other wiring part 62. Prevent material diffusion, And suppressing a decrease in reflectance of the genus reflective layer may be a lamp equipped with a semiconductor light emitting element luminous efficiency is improved.

Moreover, the semiconductor light-emitting element 1 which is embodiment of this invention and the lamp | ramp 4 which is embodiment of this invention can be used, for example, incorporating in an illuminating device. In this case, although not shown, the substrate on which wirings, through-holes and the like are formed, the lamp 4 using the plurality of semiconductor light emitting elements 1 attached to the substrate surface, and a concave cross-sectional shape, It is possible to use in a lighting device by providing a reflector or a shade configured to be attached with a lamp 4 using the semiconductor light emitting element 1 at the bottom of the lamp. Moreover, the lamp 4 using the semiconductor light-emitting element 1 described in the first embodiment is fixed in the reflector for the lighting device according to the content described in Japanese Patent Application Laid-Open No. 2008-16412, and includes a plurality of the reflectors. Can be made into equipment.
In addition, the lamp 4 according to the embodiment of the present invention can be used for electronic devices such as mobile phones, displays, and panels, and mechanical devices such as automobiles, computers, and game machines incorporating the electronic devices.
Hereinafter, the present invention will be specifically described based on examples. However, the present invention is not limited only to these examples.

Example 1
<Fabrication of semiconductor light emitting device>
The semiconductor light emitting element made of the gallium nitride compound semiconductor shown in the first embodiment was manufactured as follows.
First, an underlayer made of undoped GaN having a thickness of 8 μm was formed on a substrate made of sapphire via a buffer layer made of AlN.
Next, after forming a Si-doped n-type GaN contact layer having a thickness of 2 μm and an n-type In _0.1 Ga _0.9 N cladding layer having a thickness of 250 nm, a Si-doped GaN barrier layer having a thickness of 16 nm and a thickness of 2 A .5 nm In _0.2 Ga _0.8 N well layer was stacked five times, and finally a light emitting layer having a multiple quantum well structure in which a barrier layer was provided was formed.
Further, a Mg-doped p-type Al _0.07 Ga _0.93 N cladding layer having a thickness of 10 nm and an Mg-doped p-type GaN contact layer having a thickness of 150 nm were sequentially formed.
The gallium nitride-based compound semiconductor layer was stacked by MOCVD under normal conditions well known in the technical field.

  Next, etching was performed using a photolithography technique to expose the n-type GaN contact layer in a desired region, and an n-type electrode having a two-layer structure of Ti / Au was formed on the exposed surface.

Next, in accordance with the mask formation process shown in the first embodiment, in order to produce a 350 μm-square light emitting element, a mask having a substantially square opening with a side length of 320 μm was formed. As the resist, AZ5200NJ (product name: manufactured by AZ Electronic Materials Co., Ltd.) was used.
Next, a first diffusion prevention layer made of IZO having a thickness of 5 nm was formed by sputtering while the mask was provided.
Next, a metal reflective layer made of Ag with a thickness of 100 nm and a second diffusion prevention layer made of TaN with a thickness of 50 nm were formed by sputtering while the mask was provided.
Next, after removing the mask and placing it in the oven, in a state where the pressure is reduced to a predetermined degree of vacuum, the temperature is raised to 300 ° C. and held for 1 hour to perform heat treatment for densifying Ag. went.
Next, a mask was formed again to form a bonding layer made of Au having a thickness of 300 nm, and then the mask was removed.

Next, an insulating protective film made of SiO ₂ having a thickness of 250 nm was formed by sputtering so as to cover the upper and side surfaces of the p-type semiconductor layer 106 and the exposed surface of the n-type semiconductor layer.
Next, patterning is performed by a known photolithography technique, and a recess is etched in a predetermined region of the p-type electrode to expose a part of the bonding layer and to expose the upper surface of the n-type electrode. The semiconductor light emitting device of Example 1 was manufactured.

<Evaluation of semiconductor light emitting device>
When the forward voltage of the semiconductor light emitting device of Example 1 was measured, the forward voltage at a current application value of 20 mA was 3.1 V when energized by the probe needle.
The light emission output at an applied current of 20 mA was 22 mW. Moreover, it was confirmed that the light emission distribution on the light emitting surface emitted light on the entire surface under the positive electrode.

(Example 2) to (Example 7), (Comparative Example 1), (Comparative Example 2)
A semiconductor light emitting device was fabricated in the same manner as in Example 1 except that the conditions described in Table 1 were used.
The chip is a chip having a 460 nm emission wavelength, as in Example 1. After holding the chip under a N ₂ atmosphere at room temperature, 200 ° C., 300 ° C., and 400 ° C. for 10 minutes, Forward voltage (Vf) measurement and light emission output (Po) were measured.
For the measurement of the light emission output, the semiconductor light emitting element was mounted in a TO-18 can package, and the light emission output at an applied current of 20 mA was measured by a tester.
The luminous efficiency of the semiconductor light emitting devices of Examples 1 to 7 at an applied current of 20 mA was 20 mW or more at 20 ° C. However, under the conditions described in Comparative Examples 1 and 2, the diffusion of the elements forming the metal reflection layer at high temperatures could not be suppressed, the reflectivity of the metal reflection layer was deteriorated, and the light emission efficiency was lowered.
Although details are omitted, a lamp including the chip of the present invention described in Table 1 on various mounting substrates and the lamp are fixed in a reflector for a lighting device according to the contents described in Japanese Patent Application Laid-Open No. 2008-16412, The lighting device was provided with a plurality of the reflectors. Such lamps were used in electronic equipment and various mechanical devices.

  The present invention relates to a semiconductor light emitting device, a method for manufacturing the same, a lamp, an electronic device, and a mechanical device, and in particular, an industry for manufacturing and using a semiconductor light emitting device having an electrode that prevents diffusion of constituent materials of a metal reflective layer. May be available in

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 4 ... Lamp, 10 ... Insulating protective film, 10e ... Inclined surface, 10f ... Outer edge part, 10g ... Outer periphery, 16 ... Notch part, 17 ... Notch remaining part, 19 ... Outer part, 20 ... Multilayer semiconductor layer, DESCRIPTION OF SYMBOLS 21 ... Insoluble resist part, 22 ... 1st soluble resist part, 23 ... Hardened resist part, 24 ... 2nd soluble resist part, 27 ... Mask, 27c ... Opening part, 27d ... Inner wall surface, 51 ... 1st diffusion Prevention layer, 51e ... inclined surface, 51f ... outer edge portion, 51g ... outer periphery, 52 ... metal reflection layer, 52e ... inclined surface, 52f ... outer edge portion, 52g ... outer periphery, 53 ... second diffusion prevention layer, 53e ... inclined surface 53f ... outer edge part, 53g ... outer periphery, 55 ... bonding layer, 55e ... inclined surface, 55f ... outer edge part, 55g ... outer periphery, 61 ... mounting substrate, 62 ... other lead wires, 62a ... one end, 62b ... other end, 63 ... One lead Ear, 63a ... one end, 63b ... the other end, 70 ... wall surface member, 74 ... bump, 76, 78 ... sealing resin (mold), 101 ... substrate, 102 ... buffer layer, 103 ... underlayer, 104 ... n-type semiconductor 104a ... n contact layer, 104b ... n cladding layer, 104c ... exposed surface, 105 ... light emitting layer, 105a ... barrier layer, 105b ... well layer, 106 ... p-type semiconductor layer, 106a ... p cladding layer, 106b ... p Contact layer, 106c ... upper surface, 108 ... n-type electrode, 111 ... p-type electrode, 111c ... concave portion, 111d ... inner bottom surface, 111e ... inclined surface.

Claims (16)

A substrate, a stacked semiconductor layer in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are stacked in this order on the substrate; one electrode bonded to the p-type semiconductor layer; and the n-type semiconductor layer A semiconductor light emitting device comprising the other electrode joined to the semiconductor layer,
Either one or both of the one electrode or the other electrode has a structure in which a first diffusion prevention layer, a metal reflection layer, and a second diffusion prevention layer are laminated in this order, and A semiconductor light emitting element, wherein the first diffusion preventing layer is made of an oxide containing any one of In, Zn, Al, Ga, Ti, Bi, Mg, W, Ce, Sn, and Ni.   2. The semiconductor light emitting element according to claim 1, wherein the first diffusion preventing layer is any one of ITO, IZO, AZO, and GZO.   3. The semiconductor light emitting element according to claim 1, wherein a maximum thickness of the first diffusion prevention layer is 1 nm to 500 nm.   4. The semiconductor according to claim 1, wherein an inclined surface is formed on the outer edge of the first diffusion prevention layer so that the film thickness gradually decreases toward the outer peripheral side. 5. Light emitting element.   5. The semiconductor light emitting element according to claim 1, wherein the metal reflection layer is made of Ag, Rh, or an alloy containing any of the metals.   The semiconductor light emitting element according to claim 1, wherein the metal reflective layer is an APC alloy or an ANC alloy.   7. The semiconductor light emitting element according to claim 1, wherein a maximum thickness of the metal reflective layer is 20 to 3000 nm.   8. The semiconductor light emitting element according to claim 1, wherein an inclined surface is formed on the outer edge portion of the metal reflective layer so that the film thickness gradually decreases toward the outer peripheral side.   The second diffusion prevention layer is made of a metal selected from Ti, Ni, Ta, Cr, and Nb, a nitride of the metal, or an alloy containing any of the metals. The semiconductor light emitting element of any one of Claims.   10. The semiconductor according to claim 1, wherein an inclined surface is formed on the outer edge portion of the second diffusion prevention layer so that the film thickness gradually decreases toward the outer peripheral side. Light emitting element.   The semiconductor light-emitting element according to claim 1, wherein the stacked semiconductor layer is mainly composed of a gallium nitride-based semiconductor. A lamp comprising the semiconductor light-emitting device according to any one of claims 1 to 11 and a mounting substrate,
The mounting substrate includes one wiring portion on the one surface and another wiring portion disposed apart from the one wiring portion, and the semiconductor light emitting device has the substrate of the semiconductor light emitting device as the mounting substrate. The one electrode of the semiconductor light emitting element is connected to the one wiring part, and the other electrode of the semiconductor light emitting element is connected to the other wiring part. A lamp characterized by being. It is a manufacturing method of the semiconductor light emitting element given in any 1 paragraph of Claims 1-11,
The step of forming one or both of the one electrode and the other electrode of the semiconductor light emitting element is a first diffusion prevention on either or both of the p-type semiconductor layer and the n-type semiconductor layer. Forming a layer, heat-treating the first diffusion prevention layer, and laminating a metal reflection layer and a second diffusion prevention layer in this order on the first diffusion prevention layer. A method for producing a semiconductor light emitting element, comprising:   A lamp comprising the semiconductor light-emitting device according to claim 1.   15. An electronic device in which the lamp according to claim 12 or 14 is incorporated.   16. A mechanical apparatus in which the electronic device according to claim 15 is incorporated.

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