JPH0590281A - Two-way high breakdown strength semiconductor element - Google Patents

Abstract

PURPOSE:To lessen a two-way high breakdown strength semiconductor element in area. CONSTITUTION:An N<->-type high resistive silicon layer 3 isolated from others by an oxide film 2 serve as a common base layer, P-type base layers 4 and 5 and P-type drain layers 6, 7, 8, and 9 are formed on the surface of the above common base layer, +-type source layers 10, 11, and 12, 13 are formed on the P-type base layers 4 and 5 respectively, and two IGBTs Q1 and Q2 are formed into an integral structure source electrodes 14 and 15 are provided onto the P-type base layers 4 and 5, drain electrodes 16, 17, 18, and 19 are provided to the P-type drain layers 6, 7, 8, and 9 respectively, and these source and drain electrodes are divided into two systems, E1 and E2, and alternately connected together, and two-way elements are formed between the terminals E1 and E2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional high breakdown voltage semiconductor device using dielectric separation.

[0002]

2. Description of the Related Art In a telephone exchange or the like, a bidirectional high withstand voltage element is used which can pass current in both forward and reverse directions and has a high withstand voltage in both directions.

11 and 12 show an example of a conventional bidirectional high breakdown voltage element. FIG. 11 is a layout of electrodes and wirings, FIG. 12 (a) is a sectional view taken along the line AA ′ of FIG. 11, and FIG. 12 (b) is an equivalent circuit. Proceedings of 1988 Int
ernational Symposium on Power Semiconductor D
A similar device is reported in evices, p.117. 101
Is a support substrate formed of polycrystalline silicon, and n ⁻ is dielectrically separated from the surroundings by the oxide films 102 and 103.
The high-resistivity silicon layers 104 and 105 serve as element regions.
IGBT-Q1 and Q2 are formed in each of these element regions, and two IGBT-Q1 and Q2 are paired to form one bidirectional high breakdown voltage element.

[0004] will be described the IGBT-Q1, n ^- The p-type base layer 106 and the p-type drain layer 107 are formed on the surface of the p-type high resistance silicon layer 104, respectively, and the p-type base layer 10 is formed.
N ^{+ on} the surface of 6 The mold source layer 108 is formed. p
Mold base layer 106 and n ⁺ A source electrode 109 is provided so as to contact both of the type source layers 108, and a drain electrode 110 is formed on the p-type drain layer 107. n ⁺ -Type source layer 108 and the n ^- A gate electrode 112 is formed on the surface of the p-type base layer 106 sandwiched between the high-resistance silicon layers 104 with a gate oxide film 111 interposed therebetween. Also, n ⁻ -Type high-resistance silicon layer 104 has n ^{+ on} its bottom and side surfaces in contact with oxide film 102. Mold layer 11
3 is formed.

This IGBT-Q1 has a high breakdown voltage characteristic in both forward and reverse directions between the source and drain. When passing a current, a positive drain voltage is applied to the drain electrode 110 with reference to the source potential, and a positive gate voltage is applied. At this time, a current flows from the drain to the source.

The IGBT-Q2 has the same structure as the IGBT-Q1. The drain electrode 114 of the IGBT-Q2 is IG
Is connected to the source electrode 109 of the BT-Q1, this is the first main terminal E _1. The source electrode of the IGBT-Q2 115 is connected to the drain electrode 110 of the IGBT-Q1, which is the second main terminal E _2. Also, IGB
First control terminal G ₁ summarizes the gate electrode of T-Q1,
Second and control terminal G ₂ together gate electrodes of the IGBT-Q2.

The broken line areas in FIG. 11 are the IGBT-Q, respectively.
The element regions of 1 and IGBT-Q2 are shown. The intersecting portions of the wirings of the terminals G ₁ and E _{1 and} the wirings of the terminals G ₂ and E ₂ have a multilayer structure, and the wirings of the terminals G ₁ and G ₂ are usually polycrystalline silicon electrodes, and There is an insulating film,
Furthermore, metal wirings of terminals E ₁ and E ₂ pass therethrough.

When a positive voltage is applied to the terminal E ₂ with reference to the potential of the terminal E ₁ , the IGBT-Q 2 receives a voltage in the reverse direction to the normal direction, but no current flows because of the reverse breakdown voltage. .. If a positive gate voltage is applied to the terminal G ₁ in this state, a current flows in the IGBT-Q _{1 in} the direction from the terminals E ₂ to E ₁ . On the contrary, with reference to the potential of terminal E ₁ , terminal E ₂
To when it places a negative voltage, the voltage of the normal and reverse directions according to the IGBT-Q1 but with reverse breakdown voltage no current flow, by multiplying the positive gate voltage in this state to the terminal G _2,
Current flows from the terminal E ₁ in the direction of E ₂ to IGBT-Q2. The device thus acts as a bidirectional switch.

To form this element, an IGBT-
An isolation region is required between Q1 and IGBT-Q2. I
P-type drain layer 1 in order to provide reverse breakdown voltage to the GBT
07 and n ⁺ If the distance provided between the mold layers 113 is a and the width of the separation groove is b, the shortest distance c between the p-type drain layers of the two IGBT-Q1 and Q2 needs to be 2a + b or more. This situation does not change even when the arrangement of the p-type drain layer and the p-type base layer of the IGBT is reversed.

[0010]

As described above, in the conventional bidirectional high withstand voltage element, the isolation area is required between the two high withstand voltage elements forming the bidirectional high withstand voltage element, so that the area of the entire element becomes large. There was a problem that it would end up. An object of the present invention is to provide a bidirectional high withstand voltage semiconductor element having a small total area by eliminating this isolation region.

[0011]

In a bidirectional high breakdown voltage semiconductor element according to the present invention, a second conductivity type base layer is formed on a surface portion of a first conductivity type high resistance base layer, and a second conductivity type base layer is formed.
A first conductivity type first layer is formed on the inner and outer surfaces of the conductivity type base layer.
Of the two lateral pnpn high breakdown voltage elements in which the main electrode region and the second main electrode region of the second conductivity type are formed, the high resistance base layer is shared as one dielectric-isolated island semiconductor layer. It is characterized in that it is configured and is connected in anti-parallel.

[0012]

In the bidirectional high breakdown voltage semiconductor device according to the present invention, for example, when an IGBT is used, the first conductivity type source layer (first main electrode region) and the second conductivity type base are provided inside the second conductivity type base layer. When two drain layers (second main electrode regions) of the second conductivity type were formed outside the layer and connected in parallel, two main electrodes were alternately arranged in two systems E ₁ and E ₂ . It becomes a state. In this state, bidirectional current can flow between E ₁ and E ₂ . IGBT with a similar structure
A thyristor can be used instead of. And according to the present invention, since the separation groove unlike the conventional example is not used,
The element area can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are a layout of a bidirectional high breakdown voltage semiconductor element using a lateral IGBT focusing on electrode wiring and a sectional view taken along the line AA '. An island-shaped n ⁻ -around the support substrate 1 made of single crystal or polycrystalline silicon, which is dielectrically separated by an oxide film 2. A high-resistivity silicon layer 3 is formed. Two lateral IGBTs-Q1 and Q2 are formed on the island-shaped silicon layer 3 as a common n-type base layer.

[0015] n ^- On the surface of the high-resistance silicon layer 3 are two p-type base layers 4 and 5 and the respective p-type base layers 4 and 5.
Four p-type drain layers 6, 7, 8 and 9 are formed on the outside of 5, and these are arranged side by side as shown in FIG. n ⁺ is formed on the surface of the p-type base layer 4. Type source layers 10 and 11 are n ^{+ on} the surface of the p type base layer 5. Mold source layers 12 and 13 are formed, respectively. Planarly n ⁺ Mold source layers 10 and 1
1 is connected to one donut shape, n ⁺ The mold source layers 12 and 13 are similarly connected.

P-type base layer 4 and n ⁺ Type source layer 10, 1
Source electrode 14 of one IGBT-Q1 straddling 1
But the p-type base layer 5 and n ⁺ The source electrode 15 of the other IGBT-Q2 is provided across the mold source layers 12 and 13. The p-type drain layers 6, 7, 8 and 9 are provided with drain electrodes 16, 17, 18 and 19, respectively.

[0017] n ^- Type high resistance silicon layer 3 and n ⁺ A gate electrode 21 is formed on the surface of the p-type base layer 4 sandwiched between the type source layers 10 with a gate oxide film 20 interposed therebetween, and n ⁺ Gate electrodes 22, 23, 24 are similarly formed on the mold source layers 11, 12, 13, respectively. In plan view, the gate electrodes 21 and 22, 23 and 24 are connected in a donut shape.

[0018] n ^- -Type high resistance silicon layer 3 is surrounded by n ^{+ at} the interface with the oxide film 2. The mold layer 25 is formed. Source electrodes 14, 15 and drain electrodes 16, 17, 18,
Every other 19 is divided into two systems and connected.
That is, the source electrode 14 and the drain electrodes 18 and 19 are connected and wired, and the source electrode 15 and the drain electrodes 16 and 17 are connected and wired. The former will be called the terminal E ₁ system, and the latter will be called the terminal E ₂ system. The gate electrodes 21 and 22 are collectively referred to as a gate terminal G ₁ , and the gate electrodes 23 and 24 are collectively referred to as a gate terminal G ₂ .

When the arrangement of these electrodes is viewed two-dimensionally, the wirings of the terminals E ₁ and G _{1 and} the wirings of the terminals E ₂ and G ₂ intersect as shown in FIG. This portion has a multilayer structure, and an insulating film is provided between the electrodes. Figure 1
The dashed rectangle in the plan view represents the element region surrounded by the isolation oxide film 2.

In this device, when a positive voltage is applied to the terminal E ₂ with the terminal E ₁ as a reference, a depletion layer spreads around the p-type base layer 4, p-type drain layers 8 and 9 and exhibits a high withstand voltage characteristic. .. When a positive gate voltage is applied to the terminal G ₁ in this state, an n channel is formed on the surface of the p-type base layer 4 below the gate electrodes 21 and 22, and n ⁺ An electron current flows from the type source layers 10 and 11 to the p-type drain layers 6 and 7, respectively, and conversely, a hole current flows from the p-type drain layers 6 and 7 to the p-type base layer 4. Thus, a current flows from the terminal E ₂ to E ₁ .

When a positive voltage is applied to the terminal E ₁ with the terminal E ₂ as a reference, a depletion layer spreads around the p-type base layer 5, the p-type drain layers 6 and 7 and exhibits a high breakdown voltage characteristic. When a positive gate voltage is applied to the terminal G ₂ in this state, a current flows from the terminal E ₁ to E ₂ this time.

As described above, this device has terminals E ₁ and E ₂
It has a withstand voltage in both directions and can control the current in both directions. Therefore, the bidirectional high breakdown voltage element is constituted by one element region, and the separation groove unlike the conventional example is not required. In this device, the p-type drain layer 7 shown in FIG.
The distance d between 2 and 8 corresponds to the distance c between the p-type drain layers of the two IGBTs in the conventional example shown in FIG. n
^- If the impurity concentration and the breakdown voltage of the high-resistivity silicon layer are the same, the distance d may be the same as the distance a in the example of FIG.
Therefore, d can be made shorter than c by at least a + b, and the area can be reduced by this amount.

In this device, a p-type base layer and n ⁺ More source layers and p-type drain layers may be provided. By doing so, it becomes possible to flow a larger current. Also, n ⁺ The type source layers 10 and 11 and the gate electrodes 21 and 22 do not necessarily have to be connected in a donut shape.

In addition, a p-type base layer and n⁺ Type source layer
N instead of the wobbled source electrode⁺ Only the type source layer
Remove the mitter electrode and replace the MOS gate electrode with a p-type
If the gate electrode is directly attached to the surface of the source layer, two horizontal
It is possible to form a bidirectional element in which the lister is integrated.

FIG. 3 shows a lateral isolation of the periphery of the device of the embodiment of FIGS. 1 and 2 by means of trenches. The vertical separation is performed, for example, by direct bonding of the silicon wafer via the oxide film 2. For lateral isolation, V-shaped isolation trenches may be used instead of vertical sidewall trenches. n ^- When the thickness of the mold high resistance silicon layer 3 is thin,
It is also possible to perform element isolation with a LOCOS oxide film that reaches the oxide film 2 from the element surface.

FIG. 4 is based on the embodiment of FIGS. 1 and 2 and has a high resistance film 2 such as SIPOS for increasing the breakdown voltage.
6 shows a part of the embodiment in which No. 6 is provided. The structure of the portion other than the high resistance film of this embodiment is the same as that of the embodiment of FIGS. FIG. 5 shows a pattern of the high resistance film 26 in this embodiment. As shown, the p-type base layer 4 and the p-type drain layers 6, 7, n ⁺ The high resistance film 2 is formed by connecting between the mold layers 25.
6 are provided. The plan view shows the high resistance film 26, the p-type base layer, the p-type drain layer, and the n ⁺ The positional relationship of the mold layer 25 is shown as n ⁺ The mold source layer and electrodes are omitted. By providing the high resistance film 26 in this way, the potential distribution between the low resistance regions on the element surface becomes smooth, and the influence of the potential of the wiring can be shielded, so that the breakdown voltage becomes higher. For reference, FIG. 6 shows an equipotential diagram of the element surface when a voltage is applied between the terminals E ₁ and E ₂ . This is an equipotential diagram of a portion surrounded by a broken line in the plan view of FIG.

N ⁺ By changing the shape of the mold layer 25, the high resistance film 2
It is also possible to make the width of 6 constant. FIG. 7 is a plan view of such an example. After all n ⁺ The mold source layer and electrodes are omitted. However, rather than this example, n ⁺ The pressure resistance is higher when the edge of the mold layer 25 is smooth. The reason is clear by comparing FIG. 6, which is an equipotential diagram in the case of FIG. 5, with FIG. 8, which is an equipotential diagram in the case of FIG. 7. In FIG. 8, the equipotential line is sharply bent and the electric field is strong at the portion indicated by the arrow. On the other hand, FIG.
There is no such part in the equipotential diagram of.

FIGS. 9 and 10 show a horizontal type I according to another embodiment.
It is a bidirectional high withstand voltage element using GBT. n ^- P-type base layers 27, 28, 29, on the surface of the high-resistivity silicon layer 3,
30 and the p-type drain layer 31 are formed side by side in this order. The surface of each of the p-type base layers 27, 28, 29, 30 has n ⁺ Type source layers 32, 33, 34, 3
5 are formed on the same side, offset. p-type base layer 2
On the electrodes 7, 28, 29 and 30, electrodes 36, 37,
38 and 39 are n ⁺ The mold source layers 32, 33, 34, 35 are also provided so as to straddle. A drain electrode 40 is provided on the p-type drain layer 31.

[0029] n ^- Type high resistance silicon layer 3 and n ⁺ A gate electrode 42 is formed on the surface of the p-type base layer 27 sandwiched between the type source layers 32 via a gate oxide film 41, and n ⁺ Gate electrodes 43, 44 and 45 are similarly formed on the mold source layers 33, 34 and 35, respectively.

The electrodes 36, 38 and 40 are commonly connected,
This system is called a terminal E ₁ system, and the electrodes 37 and 39 are commonly connected to make this system a terminal E ₂ system. The gate electrodes 42 and 44 and the gate electrodes 43 and 45 are also connected,
These are referred to as gate terminals G ₁ and G ₂ , respectively.

The broken line in FIG. 9 also represents one element region. In a plan view, the wirings of the terminals E ₁ and G _{1 and} the wirings of the terminals E ₂ and G ₂ intersect, but this portion has a multi-layered structure as in the embodiment of FIGS. 1 and 2. An insulating film is provided between the electrodes.

In this element, when a positive voltage is applied to E ₂ with the terminal E ₁ as a reference, a depletion layer spreads around the p-type base layers 27 and 29 and the p-type drain layer 31 and exhibits a high withstand voltage characteristic. When a positive gate voltage is applied to G ₁ in this state, n channels are formed on the surfaces of the p-type base layers 27 and 29 below the gate electrodes 42 and 44. The p-type base layers 28 and 30 are n ⁺ It acts as a drain for the type source layer 32, 34, n ⁺ Electrons are emitted from the p-type source layers 32 and 34 toward the p-type base layers 28 and 30, respectively.
Holes flow from the type base layers 28 and 30 to the p-type base layers 27 and 29. Thus, a current flows from the terminal E ₂ to E ₁ .

When a positive voltage is applied to E ₁ with the terminal E ₂ as a reference, the depletion layer spreads around the p-type base layers 28 and 30 and exhibits a high withstand voltage characteristic. In this state, terminal G ₂
When applying a positive gate voltage, p-type base layer 29 is n ⁺
It functions as a drain for the source layer 33, and the terminal E ₁
A current flows from E to E ₂ .

As described above, this element is a bidirectional high breakdown voltage element in which the p-type base layer is used as it is as the drain layer. Further, this embodiment has the same performance as the embodiments of FIGS. 1 and 2, but has a structure with one less p-type region, and further area reduction is realized.

Also in this embodiment, n ⁺ It is possible to increase the current by increasing the number of p-type base layers having the type source layer. As in the example of FIG. 4, a high resistance film can be formed to increase the breakdown voltage. N ⁺ electrodes 36, 37, 38, 39
A thyristor may be formed on the surface of the p-type source layer so as not to contact the p-type base layer, and the gate electrode may be directly formed on the surface of the p-type base layer. The isolation between elements in the lateral direction may be performed by trenches as in the example of FIG.
You may use a COS oxide film. Further, these modifications are independent of each other, and can be combined.

[0036]

As described above, according to the present invention, a bidirectional high withstand voltage element can be constituted by one element region having no dielectric groove and having a dielectric isolation, and the area of the element can be reduced. Is.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a bidirectional high withstand voltage element according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.

FIG. 3 is a diagram of an example in which trench isolation is applied to the device of the above example.

FIG. 4 is a diagram of an example in which a high resistance film is provided on the element of the example of FIG.

5 is a diagram showing a layout of the high resistance film of FIG.

6 is an equipotential diagram for the high resistance film layout of FIG.

FIG. 7 is a diagram showing another example of the layout of the high resistance film of FIG.

8 is an equipotential diagram in the high resistance film layout of FIG. 7. FIG.

FIG. 9 is a layout diagram showing a bidirectional high withstand voltage element of another embodiment.

10 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 11 is a layout diagram of a conventional bidirectional high withstand voltage element.

12 is a sectional view taken along the line AA ′ of FIG. 11 and an equivalent circuit diagram.

[Explanation of reference numerals] 1 ... Single-crystal or polycrystalline silicon substrate, 2 ... Isolation oxide film, 3 ... n ⁻ Type high resistance silicon layer (high resistance base layer), 4, 5 ... P type base layer, 6-9 ... P type drain layer, 10-13 ... N ⁺ Type source layer, 14, 15 ... Source electrode, 16-19 ... Drain electrode, 20 ... Gate oxide film, 21-24 ... Gate electrode, 25 ... N ⁺ Type source layer, 26 ... High resistance film, 27-30 ... p-type base layer, 31 ... p-type drain layer, 32-35 ... n ⁺ Type source layer, 36-40 ... Electrode, 41 ... Gate oxide film, 42-45 ... Gate electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (1)

[Claims] 1. A second conductive type base layer is formed on a surface portion of a first conductive type high resistance base layer, and a first main conductive type main layer is formed on inner and outer surfaces of the second conductive type base layer. Two lateral pnpn high breakdown voltage elements in which an electrode region and a second main electrode region of the second conductivity type are formed are configured by sharing the high resistance base layer as one dielectric-isolated island semiconductor layer. And a bidirectional high breakdown voltage semiconductor element characterized by being connected in anti-parallel.