JPH0589692A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To realize a nonvolatile memory in which the area of a chip can be reduced and components can be mounted on a circuit board in high density. CONSTITUTION:A memory cell 3 having a capacitor 1 using a ferroelectric film and a MOS transistor 2 is connected to a bit line BL connected to a sense amplifier 30 and a bar BL. Dummy cells 17a, 17b formed of one MOS transistor 171 and a dummy capacitor 170 having 1/2 of the capacity of the capacitor 1 by using a ferroelectric film are connected to the BE,, and similar dummy cells 17c, 17d are connected to the other bar BL. Before data is read, the cells 17a, 17b, 17c, 17d are written, the ferroelectric films of the two capacitors 170 connected to the BL and the bar BL are polarized reversely, polarized charge from the cell 3 is read in the one BL, polarized charges from the cells 17c, 17d are read in the other bar BL, and a potential difference presented in both the BL and the bar BL is read by the amplifier 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line to which a plurality of memory cells each composed of one capacitor using a ferroelectric film and one MOS transistor are connected, and the bit line 2.
The present invention relates to a nonvolatile memory device in which a plurality of sense amplifiers connected to a book are arranged on a semiconductor substrate and the polarization direction of a ferroelectric film of the capacitor is stored in correspondence with binary information.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of a non-volatile memory device using a ferroelectric film of this type. FIG. 3 shows a part of this non-volatile memory device, that is, two of the bit lines wired in the column direction and the peripheral structure thereof, and between two adjacent bit lines BL and bars BL. A plurality of memory cells 25 are connected to. Moreover, both bit lines B and B are connected to one terminal of these bit lines BL and BL.
A sense amplifier 30 for amplifying and detecting the potential between L and BL is connected.

A memory cell 25 is constructed by connecting two N-channel MOS transistors 21 and 22 to two capacitors 23 and 24 having two ferroelectric films provided in pairs.
The drain of one of the MOS transistors 21 is a bit line B
Connected to L. The source of the MOS transistor 21 is connected to one end of the capacitor 23, and the gate is connected to the word line 28. The word line 28 is a bit line BL,
A plurality of wires are arranged in the row direction orthogonal to the bar BL. Also,
The same number of drive lines DL are arranged in parallel with the word lines 28.

The drain of the other MOS transistor 22 is connected to the bit line bar BL, and the source thereof is the capacitor 2.
The gate is connected to the word line 28 at one end of each of the four. The other ends of the capacitors 23 and 24 are connected to the drive line D.
Connected to L.

In the nonvolatile memory device having the above structure, 2
The writing of the value data “1” and “0” is performed as follows. First, as shown in FIGS. 4 and 5, the writing of the data “1” is performed by applying the power supply voltage V to one bit line BL.
While supplying _CC , the word line 28 is set to "H" level and the MOS transistor 21 is turned on. As a result, the power supply voltage V _CC is supplied to one end of the capacitor 23. At this time, the drive line DL has G
The voltage rising and falling from the ND level to the V _CC level is applied in pulses.

When the drive line DL is at the GND level, a voltage of V _CC is applied between both electrodes of the capacitor 23. Corresponding to this, an electric field E _VCC appears as shown in FIG. The electric charge P _S is accumulated in 23. When the drive line DL reaches the V _CC level from this state, the external electric field disappears, but even in this state, the charge P _r remains due to the polarization of the ferroelectric conductive film.

On the other hand, the other bit line bar BL has a GND
The level is supplied, and at the same time, the word line is set to the "H" level to turn on the MOS transistor 22, and the GND level is supplied to one end of the capacitor 24. The above pulse is applied to the drive line DL. Therefore, when the drive line DL is at the GND level, the external electric field is not applied between both electrodes of the capacitor 24. From this state, the drive line DL is V
_When it becomes _CC level, -V will be applied between both electrodes of the capacitor 23.
_Since the voltage of _CC is applied, an electric field −E _VCC corresponding to this appears between both electrodes, and the charge −P _r is accumulated in the capacitor 24 as shown in FIG. 5B. Even if the drive line DL becomes the GND level and the external electric field disappears from this state, the charge -P _r remains due to the polarization of the ferroelectric film.

These residual charges P _r and -P _r are retained even when the power supply voltage V _CC is no longer supplied to this device. Therefore, information can be held in a nonvolatile manner.

When writing data "0", the voltage level supplied to the bit line BL and the bit line bar BL is opposite to the above. That is, the GND level is supplied to the bit line BL and the V _CC level is supplied to the bit line bar BL. As a result, contrary to the above, the electric charge of −P _r remains in the capacitor 23,
The electric charge of P _r remains in the capacitor 24.
That is, the data “0” is written in the capacitor 24.

The data written as described above
The reading of "1" is performed as follows, but both bit lines BL and BL are discharged to the GND level prior to the reading. Subsequently, as shown in FIGS. 6 and 7. The word line 28 is set to "H" level, the MOS transistors 21 and 22 are turned on to start the read operation, and then the drive line DL is raised from the GND level to the V _CC level as shown in the figure. In the case of reading "1", the electric field is applied to the capacitor 23 in the direction opposite to that at the time of writing, so that the polarization is inverted, but the electric field is applied to the capacitor 24 in the same direction as at the time of writing, so that the polarization is not inverted. At this time, the potential of the bit line BL is slightly higher than that of the bit line BL due to the difference in the amount of charge flowing into the bit line BL and the bit line BL. Sense amplifier 30 the potential difference detected by amplification of. Thus the read data "1" is performed.

On the other hand, in the case of reading data "0", the electric field is applied to the capacitor 24 in the direction opposite to that during writing, so that the polarization is reversed, but the electric field is applied to the capacitor 23 in the same direction as during writing. Therefore, the polarization does not reverse. At this time, the bit line bar BL has a potential slightly higher than that of the bit line BL due to the difference in the amount of charge flowing into the bit line BL and the bit line BL. Then, this potential difference is amplified by the sense amplifier 30 in the same manner as above, and the data "0" is read.

[0012]

By the way, since the memory cell 25 having the above-described structure has the capacitors 23 and 24 using the two ferroelectric films and the two N-channel MOS transistors 21 and 22 as the constituent elements. It has the following drawbacks. That is, since four elements are required to store 1-bit information, the chip area becomes large, which has been a bottleneck in achieving high mounting of the circuit board.

Therefore, the applicant of the present application first proposed a non-volatile memory device capable of solving the above-mentioned drawbacks of the prior art in Japanese Patent Application No.
No. 235074. FIG. 8 shows a part of the circuit configuration of this non-volatile memory device, that is, two of the bit lines wired in the column direction and the peripheral configuration thereof.
A sense amplifier 30 for amplifying and detecting the potential difference between the two bit lines 8 and 9 is provided at one terminal of two adjacent bit lines 8 and 9.
Are connected. A plurality of word lines 15 and 16 are arranged in the row direction orthogonal to the bit lines 8 and 9. Memory cells 3 are arranged in regions surrounded by the bit lines 8 and 9 and the word lines 15 and 16, respectively.

The memory cell 3 comprises a capacitor 1 using a ferroelectric film and an N-channel MOS transistor 2 and is connected to the bit lines 8 and 9 and the word lines 15 and 16 as follows. That is, of the memory cells 3 and 3 arranged opposite to each other across the word line 16, one of the memory cells 3 has the drain of the MOS transistor 2 connected to the bit line 8 and the source connected to one end of the capacitor 1 and the gate connected to the bit line 8. Each is connected to a word line 15. In the other memory cell 3, the drain of the MOS transistor 2 is connected to the bit line 9, and the source is connected to one end of the capacitor 1.
The gates are connected to the word lines 16, respectively. The other end of each of the capacitors 1 and 1 has a voltage half the power supply voltage V _CC ,
That is, the voltage of 1/2 V _CC is supplied from the outside.

In addition to the above structure, two dummy cells are connected to each bit line 8 and 9. That is, the dummy cells 7a and 7b are connected to the bit line 8 and the dummy cells 7c and 7d are connected to the bit line 9. These dummy cells 7a, 7b, 7c and 7d are composed of a dummy capacitor 4 using a ferroelectric film and MOS transistors 5 and 6. These MOS transistors 5 are all N-channel MOS transistors. On the other hand, MO
Of the S transistors 6, the MOS transistors 6 forming the dummy cells 7a and 7d are P-channel MOS transistors, and the MOS transistors forming the dummy cells 7b and 7c are N-channel MOS transistors.

The concrete connection mode between the dummy cell 7a and the bit line 8 is as follows. That is, the drain of the MOS transistor 5 is connected to the bit line 8, the source is connected to one end of the dummy capacitor 4, and the gate is connected to the word lines 15 and 16.
Are connected to the dummy cell word lines 17 which are wired in parallel. The dummy capacitor 4 is formed by using a ferroelectric film, and its capacitance is set to half the capacitance of the capacitor 1 of the memory cell 3. That is, as shown in the figure, C _D = 1 / 2C _S. A voltage of 1/2 V _CC is externally supplied to the other end of the dummy capacitor 4. The drain of the MOS transistor 6 is a MOS
It is connected to the source of the transistor 5 and one end of the dummy capacitor 4, and the source is connected to the V _CC terminal. Furthermore,
The gate of the MOS transistor 6 is connected to the bar Φ _PDUM signal line 19 which is wired in parallel with the dummy cell word line 17.

The connection between the dummy cell 7b and the bit line 8 is M
This is performed by connecting the drain of the OS transistor 5 to the bit line 8. The gate of the MOS transistor 5 is the MOS
It is connected to the gate of the transistor 5. Further, the source is connected to one end of the dummy capacitor 4 which constitutes the dummy cell 7b as in the above. The drain of the MOS transistor 6 is connected to the source of the MOS transistor 5 and one end of the dummy capacitor 4, and the source is connected to the GND terminal. The gate is connected to the Φ _PDUM signal line 20.

The Φ _PDUM signal line 20 is also connected to the gate of the MOS transistor 6 forming the dummy cell 7c. The connection between the dummy cell 7c and the bit line 9 is M
This is performed by connecting the drain of the OS transistor 5 to the bit line 9. The source of the MOS transistor 5 is connected to one end of the dummy capacitor 4 and the drain of the MOS transistor 6. The source of the MOS transistor 6 is GND
Connected to the terminal. The gate is connected to the gate of the MOS transistor 5 which constitutes the dummy cell 7d. The gate of the MOS transistor 5 is a dummy cell word line 1
8 is connected.

The connection between the dummy cell 7d and the bit line 9 is
This is performed by connecting the drain of the MOS transistor 5 to the bit line 9. The source is connected to one end of the dummy capacitor 4 and the drain of the MOS transistor 6.
The gate is connected to the dummy cell word line 18. MOS
The source of the transistor 6 is connected to the V _cc terminal, and the gate is connected to the bar Φ _PDUM signal line 19 _provided between the dummy cells 7c and 7d.

Further, the sense amplifier 3 between the bit lines 8 and 9
0 A bit line equalize circuit 13 is provided in a portion corresponding to the memory cell 3 adjacent to the bit line. The bit line equalize circuit 13 is composed of three P-channel MOS transistors 10, 11 and 12, and the gates of these MOS transistors 10, 11 and 12 are all between the sense amplifier 30 and the word line 15 adjacent thereto. It is connected to the bar Φ _BEQ signal line 21 that is wired to the. Also,
The sources of MOS transistors 10 and 12 are connected to V _CC , and the drains are connected to bit line 8 and bit line 9, respectively. On the other hand, the drain of the MOS transistor 11 is connected to the bit line 8 and the source is connected to the bit line 9.

The sense amplifier 30 is a circuit which is connected to the bit lines 8 and 9 as described above and amplifies and detects a minute potential difference appearing between the bit lines 8 and 9, and a Φ _s signal for instructing the start of amplification, that is, When the Φ _s signal of “H” level is input, the amplification operation is started.

Next, the operation principle of the memory cell 3 in the nonvolatile memory device having the above-mentioned structure, that is, the operation principle of the memory cell 3 in writing and reading data will be described with reference to FIGS. Binary data ”
The writing of "1" and "0" will be described taking the memory cell 3 connected to the word line 15 as an example. First, the word line 15 is set to the "H" level and the MOS transistor 2 of the memory cell 3 connected to this is set. Is turned on to select the memory cell 3. Then, the bit line 8 is set to a predetermined level (V _CC or GND), and a half voltage is applied between both electrodes of the capacitor 1.
A voltage of V _CC or -1/2 V _CC / 2 is applied, whereby the polarization direction of the ferroelectric film is associated with binary data. The details will be described below.

First, for writing data "1", as shown in FIG. 9, the power supply voltage V _CC is supplied to the bit line 8 and the word line 15 is set to "H" level to turn on the MOS transistor 2 to turn on the capacitor. The power supply voltage V _CC is supplied to one end of 1. As shown in FIG. 9, 1 is placed at the other end of the capacitor 1.
A voltage of / 2V _CC is applied. As a result, capacitor 1
Since a voltage of 1/2 V _CC is applied between the two electrodes, the electric field E _VCC shown in FIG. 10 appears correspondingly, and the electric charge P _s is accumulated in the capacitor 1.

Subsequently, the word line 15 is changed from this state.
When the MOS transistor 2 is turned off at the L "level,
Although the external electric field disappears, the electric charge P _r remains due to the polarization of the ferroelectric film. The supply of the power supply voltage V _CC to the nonvolatile memory device is stopped, and the other end of the capacitor 1 is
This residual charge P _r is retained even if the voltage of / 2V _CC is not supplied. That is, the data "1" written in the memory cell 3 in a nonvolatile manner can be retained.

The reading of the data "1" is performed as follows. First, as shown in FIG. 11, the bit line 8 is precharged to the V _CC level prior to the read operation. Subsequently, the word line 15 is set to the “H” level and the MOS
Turn on the transistor 2. As a result, the power supply voltage V _CC
The charge of the bit line 8 precharged to the capacitor 1
Will be supplied to and cause charge sharing. Here, the capacitance of the bit line 8 is considered to be 10 times or more larger than that of the capacitor 1 of the memory cell 3 in the normal case. Therefore, a voltage close to the power supply voltage V _CC is supplied to one end of the capacitor.

The other end of the capacitor 1 has a voltage of 1/2 V _CC.
Is applied. As a result, since a voltage close to 1/2 V _CC is applied between both electrodes of the capacitor 1,
As shown in, electric field E _VCC corresponding to this appears, and charge P _s
Is accumulated. At this time, the amount of charge transferred from bit line 8 to the capacitor 1 becomes P _s -P _r. Now, _assuming that the capacitance of the bit line 8 is C _B and the capacitance of the capacitor 1 is C _s , data "
Voltage level V _BIT1 of bit line 8 when 1 ”is read
Is represented by the following formula.

That is, V _CC · C _B − (P _s −P _r ) = V
_Since the relationship of _BIT1 · (C _B + C _s ) is established, V _BIT1 = (V _CC · C _B − (P _s −P _r )) / (C _B + C _s ) ...

To write the data "0", as shown in FIG. 13, the GND level is supplied to the bit line 8 and the word line 15 is set to the "H" level to make the MOS transistor 2
Is turned on to supply the GND level to one end of the capacitor 1. As shown in FIG. 13, the other end of the capacitor 1 is 1 /
A voltage of 2V _CC is applied. As a result, a voltage of -1/2 V _CC is applied between both electrodes of the capacitor 1, and correspondingly, an electric field E _GND appears between both electrodes of the capacitor 1 as shown in FIG. P _s is accumulated. When the word line 15 is set to the "L" level and the MOS transistor 2 is turned off from this state, the external electric field disappears, but the electric charge -P _r remains in the capacitor 1 due to the polarization of the ferroelectric film. Power supply voltage V _CC for this nonvolatile memory device
Supply is stopped and the other end of capacitor 1 has 1/2 V _CC
This residual charge -P _r is retained even when the voltage of is no longer supplied. That is, the data "0" written in the memory cell 3 can be held in a nonvolatile manner.

The reading of the data "0" is performed as follows. First, as shown in FIG. 15, the bit line 8 is precharged to the V _CC level prior to the read operation. Subsequently, the word line 15 is set to the “H” level and the MOS
Turn on the transistor 2. As a result, the bit line 8 precharged to the power supply voltage V _CC is supplied to the capacitor 1 to cause charge sharing. As described above, since the capacitance of the bit line 8 is sufficiently larger than that of the capacitor 1,
A voltage close to the power supply voltage V _CC is supplied to one end of the capacitor 1. A voltage of 1/2 V _CC is applied to the other end of the capacitor 1, as shown in FIG. As a result, a voltage close to 1/2 V _CC is applied between both electrodes of the capacitor 1, so that the electric field E corresponding to this is applied as shown in FIG.
_VCC appears and the charge P _s is accumulated. At this time, the amount of charge transferred from the bit line to the capacitor 1 is P _s + P _r .
Now, the capacitance of the bit line 8 is C _B , and the capacitance of the capacitor 1 is C _s
Then, the bit line 8 when the data “0” is read
The voltage V _{BIT0 of} is expressed by the following equation.

That is, V _CC · C _B − (P _s + P _r ) = V
_{Since the relationship of BIT0} · (C _B + C _s ) is established, V _BIT0 = (V _CC · C _B − (P _s + P _r )) / (C _B + C _s ) ...

Next, the specific procedure of the read operation in this nonvolatile memory device will be described with reference to FIG. First, prior to the read operation, the Φ _BEQ signal is input to the bit line equalize circuit 13 from the bar Φ _BEQ signal line 21 at the timing shown in FIG. 17A to operate the bit line equalize circuit 13. That is, the P-channel transistors 10, 11 and 12 are turned on and the bit lines 8 and 9 are connected to V _CC.
Precharge to a level. At the same time, as shown in FIG.
As shown in (b) and (c), the dummy cells 7a, 7b, 7 are connected from the Φ _PDUM signal line 20 and the bar Φ _PDUM signal lines 19, 19 respectively.
The Φ _PDUM signal and the bar Φ _PDUM signal are input to c and 7d, respectively. Thereby, the two dummy cells 7a and 7b (or 7c and 7d) connected to the same bit line 8 (or 9)
The ferroelectric films of the dummy capacitor 4 are polarized in opposite directions.

Subsequently, when the word line 15 becomes "H" level at the timing shown in FIG. 17 (d), the dummy cell word line 18 simultaneously becomes "H" level as shown in FIG. 17 (e).
H level, and the Φ _s signal input to the sense amplifier 30 becomes “H” at the timing shown in FIG.
When the level is reached, at the same time, the sense amplifier 14 starts amplification operation. More specifically, the sense amplifier 30 reads the polarization charge from the selected memory cell 3 from one bit line 8 (or 9) of the two bit lines 8 and 9 and reads the polarized charge from the other bit line 9 ( Or 8), two dummy cells 7c and 7d (or 7) whose polarization directions are opposite to each other.
The charge from a, 7b) is read out.

17 (g) shows the voltage level of the bit line connected to the memory cell 3 at the time of reading data "1", and FIG. 17 (h) shows the memory at the time of reading data "0". The change in voltage level of the bit line connected to the cell 3 is shown.

When the read data is "1", the voltage level V _BIT1 represented by the above formula appears on the bit line 8 (or 9) from which the polarization charge is read from the memory cell 3, and the read data is "0". In the case of ", the voltage level V _BIT0 expressed by the above equation appears. On the other hand, the dummy cells 7c and 7d
The voltage level V _BITD of the bit line 9 (or 8) from which the charge from (or 7a, 7b) is read is expressed by the following equation.

That is, V _CC · C _B − (P _s −P _r ) / 2
Since the relationship of − (P _s + P _r ) / 2 = V _BITD · (C _B + C _s ) is established, V _BITD = (V _CC · C _B −P _s ) / (C _B + C _s ) ...

From the above description, according to this nonvolatile memory device, when reading data "1", ΔV ₁ = between the two bit lines 8 and 9 connected to the sense amplifier 30.
A potential difference of V _BIT1 -V _BITD appears, and the potential difference ΔV ₁ becomes an input to the sense amplifier 30. The sense amplifier 30 is
This potential difference ΔV ₁ is amplified at the timing shown in FIG. 17 (f) when the H ″ level Φs signal is input. Similarly, when the read data is “0”, ΔV ₀ = V _BITD −
The potential difference of V _BIT0 becomes the input of the sense amplifier 30,
When the Φ _s signal at the H ”level is input, this potential difference Δ
Amplify V ₀ .

The specific values of the potential differences ΔV ₁ and ΔV ₀ are the values shown in the following formulas and formulas when the above formulas and formulas are used.

ΔV ₁ = (V _CC · C _B − (P _s −P _r )) / (C _B + C _s ) − (V _CC · C _B −P _s ) / (C _B + C _s ) = P _r / (C _B + C _s ) ... ΔV ₀ = (V _CC · C _B −P _s ) / (C _B + C _s ) − (V _CC · C _B − (P _s + P _r )) / (C _B + C _s) ) = P _r / (C _B + C _s ) ... As can be seen from the above formulas and formulas, in this nonvolatile memory device, when data “1” and “0” are read out, the absolute value is kept between the bit lines 8 and 9. Since a minute potential difference having the same value but the opposite polarity appears, if the potential difference is amplified to a predetermined level by the sense amplifier 30, data "
It is possible to discriminate between 1 "and" 0 ". That is, according to this nonvolatile storage device, it is possible to reliably read the binary information held in the nonvolatile state.

According to the nonvolatile memory device having such a structure, since the memory cell is composed of two elements, one capacitor and one MOS transistor, the chip area can be greatly reduced as compared with the above conventional example. There is an advantage that an efficient layout is possible.

However, it is necessary to connect two dummy cells to one bit line, and since the dummy cells are composed of one dummy capacitor and two MOS transistors, one bit line is eventually obtained. For that, 6 elements are required. For this reason, there is still room for improvement in reducing the chip area.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile memory device capable of further reducing the chip area and improving the mounting density on a circuit board.

[0042]

A nonvolatile memory device according to the present invention comprises a bit line to which a plurality of memory cells each including one capacitor using a ferroelectric film and one MOS transistor are connected, A nonvolatile memory device in which a plurality of sense amplifiers connected to two bit lines are arranged on a semiconductor substrate and the polarization direction of a ferroelectric film of the capacitor is stored in association with binary information. Two dummy cells are formed for each of the two bit lines by using a body film and including one dummy capacitor having a capacitance that is half the capacitance of the memory cell and one access MOS transistor. The MO for access is connected before connecting and reading the polarization charge from the capacitor of the memory cell to the bit line.
The dummy film in one of the two dummy cells connected to the bit line is written from the bit line via the S transistor to polarize the ferroelectric film of the dummy capacitor in the one dummy cell. Then, the potential of the bit line is inverted, and writing is performed from the bit line to the other dummy cell connected to the bit line through the access MOS transistor, and the dummy capacitor of the dummy capacitor in the other dummy cell is written. The ferroelectric film is polarized in the direction opposite to the polarization direction of one dummy capacitor, and then the polarization charge from the memory cell is read to the one bit line connected to the sense amplifier, and at the same time, the sense amplifier is read. The polarization charges from the two dummy cells are read to the other connected bit line, and the potential difference appearing between the two bit lines is amplified by the sense amplifier to output the data. Will be performed the reading,
Thereby, the above object is achieved.

[0043]

According to the structure in which the ferroelectric films of the dummy capacitors in the two dummy cells connected to the same bit line are polarized in the opposite directions as described above, one MOS transistor is provided in the dummy cell. Should be provided. Therefore,
The number of MOS transistors in the dummy cell can be reduced by one as compared with the nonvolatile memory device previously proposed by the applicant of the present application.

[0044]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a part of the circuit configuration of this nonvolatile memory device, that is, two of the bit lines wired in the column direction and the peripheral configuration thereof. A sense amplifier 30 for amplifying and detecting a potential difference between the two bit lines BL and BL is provided at one terminal of two adjacent bit lines BL and BL.
Are connected. In addition, a plurality of word lines Xi and Yi (i = 0) are arranged in the row direction orthogonal to the bit lines BL and bars BL.
~ N) are wired. The word line Xi represents a word line connected to the gate of the memory cell 3 connected to one bit line BL, and the word line Yi connected to the gate of the memory cell 3 connected to the other bit line bar BL. Shows the word line to be written.

The memory cells 3 and 3 are bit lines BL and bars B.
A capacitor 1 and an N-channel MOS which are arranged in a region surrounded by L and word lines Xi and Yi and which use a ferroelectric film
It is composed of a transistor 2. The specific connection mode between the memory cells 3 and 3 and the word lines Xi and Yi and the bit lines BL and bar BL is as follows.

That is, X is defined as the word lines Xi and Yi.
Taking 0 and Y0 as an example, one memory cell 3
Has the drain of the MOS transistor 2 connected to the bit line BL, the source connected to one end of the capacitor 1, and the gate connected to the word line X0. In the other memory cell 3, the drain of the MOS transistor 2 is connected to the bit line bar BL, the source is connected to one end of the capacitor 1, and the gate is connected to the word line Y0.
The other end of the capacitor 1,1, 1/2 of the voltage of the power supply voltage V _CC, that is, the voltage of 1 / 2V _CC is adapted to be supplied from the outside.

In addition to the above structure, two dummy cells are connected to each bit line BL and bar BL. That is,
Dummy cells 17a and 17b are connected to the bit line BL, and dummy cells 17c and 17d are connected to the bit line bar BL. These dummy cells 17a, 17b, 17
c and 17d are dummy capacitors 17 using a ferroelectric film
0 and a MOS transistor 171. The capacity of the dummy capacitor 170 is the capacitor 1 of the memory cell 3.
1/2 of the capacity of C, ie, as shown in the figure, C _D = 1 /
It is 2C _S. The MOS transistors 171 are all N-channel MOS transistors.

These dummy cells 17a, 17b, 17
c and 17d are dummy cell word lines DXi and DYi.
(I = 0, 1). Dummy cells 17a, 17
The specific connection modes of b, 17c, 17d and the bit lines BL, BL and the dummy cell word lines DXi, DYi are as follows.

That is, in the dummy cell 17a, the drain of the MOS transistor 171 is connected to the bit line BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DX0. On the other hand, in the dummy cell 17b, the drain of the MOS transistor 171 is connected to the bit line BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DX1. Further, the dummy cell 17c is M
The drain of the OS transistor 171 is connected to the bit line bar BL.
The source is connected to one end of the dummy capacitor 170 and the gate is connected to the dummy cell word line DY0.
On the other hand, in the dummy cell 17d, the drain of the MOS transistor 171 is connected to the bit line bar BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DY1. A voltage of 1/2 V _CC is externally supplied to the other ends of the four dummy capacitors 170, 170, 170, 170 described above.

Further, a bit line equalize circuit 13 is arranged between the sense amplifier 30 between the bit line BL and the bar BL and the memory cell 3 adjacent thereto. The bit line equalize circuit 13 is composed of three P-channel MOS transistors 10, 11 and 12, and the gates of these MOS transistors 10, 11 and 12 are all between the sense amplifier 30 and the word line X0 adjacent thereto. It is connected to the bar Φ _BEQ signal line 21 that is wired to the. Also,
The sources of the MOS transistors 10 and 12 are connected to V _CC , and the drains thereof are the bit lines BL and B, respectively.
Connected to L. On the other hand, the drain of the MOS transistor 11 is connected to the bit line BL, and the source is connected to the bit line bar BL.

The sense amplifier 30 is a circuit which is connected to the bit line BL and the bar BL as described above and which amplifies and detects a minute potential difference appearing between the bit line BL and the bar BL, and a Φ _s signal for instructing the start of amplification. That is, when the "H" level Φ _s signal is input, the amplification operation is started.

In the nonvolatile memory device having the above-described structure, the binary data "1" and "0" are written in the memory cell 3 connected to the word line X0 as an example. First, the word line X0 is set to "H". Then, the MOS transistor 2 connected thereto is turned on to select the memory cell 3 connected thereto. Subsequently, the bit line BL, and the bar BL to a predetermined level (V _CC or GND), 1 / 2V between the electrodes of the capacitor 1 _CC or -1 / 2V _CC
Voltage is applied to change the polarization direction of the ferroelectric film to 2
Corresponding to the value data. The details of data writing are the same as in the case of the nonvolatile storage device previously proposed by the applicant of the present application.

Next, a data read procedure in the nonvolatile memory device of the present invention will be described with reference to FIG. First, FIG.
At the timings shown in (b) and (e), the dummy cell word lines DX0 and DY1 are set to "H" level (= V _CC + ΔV level), and two are connected to each bit line BL and bar BL. Dummy cells 17a, 17b, 17c, 17d
The bit lines BL and BL are written to one of the two 17a and 17d to polarize the ferroelectric films of the dummy capacitors 170 and 170 of the dummy cells 17a and 17d.

Subsequently, the potentials of the bit lines BL and BL are inverted, and the dummy cell word lines DX1 and DY0 are set to the "H" level (= V _CC + Δ) at the timings shown in FIGS. 2 (c) and 2 (d).
V level), and the other dummy cells 17b and 17c connected to the bit line BL and the bar BL are connected to the bit line BL,
Data is written from the bar BL to the dummy cells 17b, 1
The ferroelectric films of the dummy capacitors 170, 170 of 7c are polarized. Since writing is performed in a state where the potentials of the bit lines BL and BL are inverted, by such writing before the data reading, the polarization directions of the ferroelectric films of the dummy capacitors 170, 170 of the dummy cells 17a and 17b are mutually changed. To the opposite direction. Similarly, the dummy cell 1
The polarization directions of the ferroelectric films of the dummy capacitors 170, 170 of 7c and 17d are also opposite to each other.

Then, as shown in FIG. 2A, the bit line equalize circuit 13 is _{supplied with a} signal from the bar Φ _BEQ signal line 21.
The _HΦ level (= V _CC level) bar Φ _BEQ signal is input to operate the bit line equalize circuit 13. That is, the MOS transistors 10, 11 and 12 are turned on, and the bit lines BL and bar BL are set to the V _CC level. Precharge to.

Then, at the timing shown in FIG. 2F, the word line Xi (or word line Yi) is at the "H" level (= V).
_CC + ΔV level), as shown in FIGS. 2 (d) and 2 (e), at the same time, the dummy cell word lines DY0, DY1
(Or DX0, DX1) becomes "H" level. As a result, the two bit lines B connected to the sense amplifier 30
One of the bit lines BL (or bar B) among L and bar BL
The polarization charge from the selected memory cell 3 is read out to L), and the polarization directions of the ferroelectric films of the dummy capacitors 170 are opposite to each other on the other bit line bar BL (or BL). Individual dummy cells 17c, 17d (or 17
The charges from a, 17b) are read out.

FIG. 2 (h) shows changes in the voltage level appearing on the bit lines BL and BL when the data "1" is read, and FIG. 2 (i) shows the bit line when the data "0" is read. The changes in the voltage levels appearing at BL and BL are shown. This read operation is performed in the same manner as the nonvolatile storage device previously proposed by the applicant of the present application. Therefore, in the case of reading data "1" to the bit line BL (or bar BL) from which the polarization charge from the memory cell 3 is read,
The voltage level V _BIT1 shown by the above formula appears, and the data “
In the case of reading "0", the voltage level V _BIT0 expressed by the above expression appears. On the other hand, the bit line BL (or BL) from which the polarization charges from the dummy cells 17c and 17d (or 17a and 17b) are read out, The voltage level V _BITD shown by the equation appears.

As a result, according to the nonvolatile memory device of the present invention, the bit line B is read when the data "1" is read.
A potential difference ΔV ₁ represented by the above expression appears between L and bar BL. That is, the potential difference ΔV ₁ becomes the input signal of the sense amplifier 30. The sense amplifier 30 sends this input signal to the timing shown in FIG. 2 (g), that is, the "H" level (=
The amplification operation is started at the time point when the Φ _s signal of V _CC level) is input. Similarly, in the case of reading the data “0”, the potential difference ΔV ₀ represented by the above equation becomes the input signal of the sense amplifier 30.

Therefore, also in the nonvolatile memory device of the present invention, when reading data "1" and "0", a minute potential difference having the same absolute value but opposite polarity is generated between the bit lines BL and BL. Since it appears, if the potential difference is amplified to a predetermined level by the sense amplifier 30, the data "1", "
It is possible to discriminate "0". That is, according to the nonvolatile memory device of the present invention, it is possible to reliably read the binary information held in the nonvolatile state.

[0061]

According to the above nonvolatile memory device of the present invention, it is possible to reliably read out the binary information held in the nonvolatile state, and to significantly increase the chip area as compared with the conventional nonvolatile memory device. The number of MOS transistors in the dummy cell can be reduced by one as compared with the nonvolatile memory device previously proposed by the applicant of the present application. Therefore, it is even more preferable for reducing the chip area, and can greatly contribute to the high mounting on the circuit board.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a nonvolatile memory device of the present invention.

FIG. 2 is a timing chart showing a read operation in the nonvolatile memory device of the present invention.

FIG. 3 is a diagram showing a conventional example of a nonvolatile memory device.

FIG. 4 is a diagram for explaining the operation of a conventional memory cell at the time of writing data “1”.

FIG. 5 is a diagram showing a change in accumulated charge of a conventional memory cell when writing data “1”.

FIG. 6 is a diagram for explaining the operation of a conventional memory cell when reading data “1”.

FIG. 7 is a diagram showing changes in accumulated charges of a conventional memory cell when reading data “1”.

FIG. 8 is a circuit diagram showing a part of a nonvolatile memory device previously proposed by the applicant of the present application.

9 is a drawing for explaining the operation of the memory cell of the nonvolatile memory device shown in FIG. 8 when writing data “1”. FIG.

10 is a drawing showing changes in the accumulated charge of the capacitor of the nonvolatile memory device shown in FIG. 8 when writing data “1”. FIG.

FIG. 11 is a diagram for explaining the operation of the memory cell of the nonvolatile memory device shown in FIG. 8 at the time of reading data “1”.

FIG. 12 is a drawing showing changes in the accumulated charge of the capacitor of the nonvolatile memory device shown in FIG. 8 when reading data “1”.

FIG. 13 is a diagram for explaining the operation of the memory cell of the nonvolatile memory device shown in FIG. 8 when writing data “0”.

FIG. 14 is a drawing showing changes in the accumulated charge of the capacitor of the nonvolatile memory device shown in FIG. 8 when writing data “0”.

FIG. 15 is a view for explaining the operation of the memory cell of the nonvolatile memory device shown in FIG. 8 when reading data “0”.

16 is a drawing for explaining the operation of the memory cell of the nonvolatile memory device shown in FIG. 8 when reading data “0”. FIG.

FIG. 17 is a timing chart showing a read operation in the nonvolatile memory device shown in FIG.

[Explanation of symbols]

1 Memory Cell Capacitor 2 Memory Cell MOS Transistor 3 Memory Cell 13 Bit Line Equalizer 17a, 17b, 17c, 17d Dummy Cell 170 Dummy Cell Dummy Capacitor 171 Dummy Cell MOS Transistor 30 Sense Amplifier BL, Bar BL Bit Line Xi, Yi ( i = 0 to n) Word line DXi, DYi (i = 0, 1) Dummy cell Word line Φ _s Signal for instructing amplification start

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 27/115 29/788 29/792 8225-4M H01L 29/78 371

Claims (1)

[Claims] 1. A capacitor and a MO using a ferroelectric film.
A plurality of bit lines connected to a plurality of memory cells each including one S transistor and a plurality of sense amplifiers connected to the two bit lines are arranged on a semiconductor substrate to polarize the ferroelectric film of the capacitor. A non-volatile memory device that stores a direction in correspondence with binary information, wherein a ferroelectric film is used, and a half of a capacitor of the memory cell is used.
Two dummy cells each consisting of a dummy capacitor having a capacitance of 1 and a MOS transistor for access are connected to each of the two bit lines, and the capacitor of the memory cell is connected to the bit line. Before reading the polarization charge of the dummy cell, one of the two dummy cells connected to the bit line is written via the access MOS transistor to write the data in the dummy cell of the one dummy cell. The ferroelectric film of the dummy capacitor is polarized, and then the potential of the bit line is inverted to write data from the bit line to the other dummy cell connected to the bit line via the access MOS transistor. Then, the ferroelectric film of the dummy capacitor in the other dummy cell is polarized in the direction opposite to the polarization direction of the one dummy capacitor, and then the The polarization charge from the memory cell is read to one of the bit lines connected to the amplifier, and at the same time, the polarization charge from the two dummy cells is read to the other bit line connected to the sense amplifier. A non-volatile memory device in which a potential difference appearing between lines is amplified by the sense amplifier to read data.