JPH0588577B2 - - Google Patents

Info

Publication number
JPH0588577B2
JPH0588577B2 JP59191505A JP19150584A JPH0588577B2 JP H0588577 B2 JPH0588577 B2 JP H0588577B2 JP 59191505 A JP59191505 A JP 59191505A JP 19150584 A JP19150584 A JP 19150584A JP H0588577 B2 JPH0588577 B2 JP H0588577B2
Authority
JP
Japan
Prior art keywords
clock
signal level
data
threshold
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59191505A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6170830A (ja
Inventor
Yukio Iino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59191505A priority Critical patent/JPS6170830A/ja
Publication of JPS6170830A publication Critical patent/JPS6170830A/ja
Publication of JPH0588577B2 publication Critical patent/JPH0588577B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59191505A 1984-09-14 1984-09-14 クロツク位相自動調整回路 Granted JPS6170830A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59191505A JPS6170830A (ja) 1984-09-14 1984-09-14 クロツク位相自動調整回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59191505A JPS6170830A (ja) 1984-09-14 1984-09-14 クロツク位相自動調整回路

Publications (2)

Publication Number Publication Date
JPS6170830A JPS6170830A (ja) 1986-04-11
JPH0588577B2 true JPH0588577B2 (enrdf_load_stackoverflow) 1993-12-22

Family

ID=16275765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59191505A Granted JPS6170830A (ja) 1984-09-14 1984-09-14 クロツク位相自動調整回路

Country Status (1)

Country Link
JP (1) JPS6170830A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01295541A (ja) * 1988-01-08 1989-11-29 Japan Radio Co Ltd 波形整形識別回路
US7136441B2 (en) 2001-01-24 2006-11-14 Matsushita Electric Industrial Co., Ltd. Clock recovery circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851400U (ja) * 1981-09-30 1983-04-07 富士通株式会社 零交差点検出回路

Also Published As

Publication number Publication date
JPS6170830A (ja) 1986-04-11

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