JPH0588200A - Liquid crystal display device and its manufacture - Google Patents

Liquid crystal display device and its manufacture

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Publication number
JPH0588200A
JPH0588200A JP25216791A JP25216791A JPH0588200A JP H0588200 A JPH0588200 A JP H0588200A JP 25216791 A JP25216791 A JP 25216791A JP 25216791 A JP25216791 A JP 25216791A JP H0588200 A JPH0588200 A JP H0588200A
Authority
JP
Japan
Prior art keywords
pixel electrode
liquid crystal
black matrix
film
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25216791A
Other languages
Japanese (ja)
Inventor
Shiyuuichi Uchikoga
修一 内古閑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25216791A priority Critical patent/JPH0588200A/en
Publication of JPH0588200A publication Critical patent/JPH0588200A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To provide the liquid crystal display device which has superior display characteristics such as a numeric aperture. CONSTITUTION:This liquid crystal display device is equipped with picture element electrodes 4 arrayed in matrix on a substrate 1, a picture element electrode protection film 6 provided on the picture element electrodes 4, a black matrix 7 which is formed in an area other than the picture element electrode protection film 6, thin film transistors as switching elements provided to the respective picture element electrodes 4, gate lines 2 connected to the gates of the thin film transistors of the same row, and signal lines 5 connected to the source and drain of one thin film transistor of the same column.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アクティブマトリック
ス型の液晶表示装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a manufacturing method thereof.

【0002】[0002]

【従来の技術】アクティブマトリックス型の液晶表示装
置は、他の液晶表示装置と同様に薄型・軽量であるのは
勿論のこと、多画素にしてもコントラスト,レスポンス
の劣化がなく、更に、中間調表示も可能である等の特徴
を有しているため、パ―ソナルコンピュ―タや大画面カ
ラ―テレビ等の表示装置として期待されている。
2. Description of the Related Art An active matrix type liquid crystal display device is not only thin and lightweight like other liquid crystal display devices, but also has no deterioration in contrast and response even if it has a large number of pixels. Since it has features such as display capability, it is expected as a display device for personal computers and large-screen color televisions.

【0003】図7はスイッチング素子として薄膜トラン
ジスタ(TFT)を用いた従来のアクティブマトリック
ス型液晶表示装置の一画素分の断面図であり、図8は同
液晶表示装置の一画素分の平面図である。
FIG. 7 is a sectional view of one pixel of a conventional active matrix type liquid crystal display device using a thin film transistor (TFT) as a switching element, and FIG. 8 is a plan view of one pixel of the liquid crystal display device. ..

【0004】この液晶表示装置は、2枚の平面ガラスか
らなるアレイ基板67及び対向基板68と、これら基板
67,68間に挟まれた液晶層55とからなる基本構成
をとっている。アレイ基板67は、透光性絶縁基板51
と、この基板51上にマトリックス状に配列された透光
性の画素電極54と、この画素電極54に接続されたT
FT69等からなる。このTFT69のゲ―ト電極52
はゲ−ト線65に接続され、ドレイン電極63はゲ−ト
線65と直角方向に設けられた信号線66に接続され、
ソ−ス電極64は画素電極54に接続されている。一
方、対向基板68は、透光性絶縁基板59と、この基板
59上に形成された各画素に対応したカラ―フィルタ―
57と、透光性の対向電極56と、ブラックマトリクス
58とからなる。TFT69の作成は通常以下のように
行なわれる。
This liquid crystal display device has a basic structure composed of an array substrate 67 and a counter substrate 68 made of two flat glasses, and a liquid crystal layer 55 sandwiched between these substrates 67 and 68. The array substrate 67 is the translucent insulating substrate 51.
A transparent pixel electrode 54 arranged in a matrix on the substrate 51, and a T connected to the pixel electrode 54.
It consists of FT69 etc. The gate electrode 52 of this TFT 69
Is connected to a gate line 65, the drain electrode 63 is connected to a signal line 66 provided in a direction perpendicular to the gate line 65,
The source electrode 64 is connected to the pixel electrode 54. On the other hand, the counter substrate 68 is a translucent insulating substrate 59 and a color filter corresponding to each pixel formed on the substrate 59.
57, a translucent counter electrode 56, and a black matrix 58. The TFT 69 is normally produced as follows.

【0005】まず最初に、透光性絶縁基板51上にゲ−
ト電極52となるMoやMo‐Ta等の低抵抗金属膜を
スパッタ堆積する。次にこの低抵抗金属膜上にゲ−ト電
極状のフォトレジストパタ−ンを形成し、これをマスク
にして低抵抗金属膜をエッチングしてゲ−ト電極52を
形成する。
First, a gate is formed on the translucent insulating substrate 51.
A low resistance metal film such as Mo or Mo-Ta that will become the cathode electrode 52 is deposited by sputtering. Next, a gate electrode-shaped photoresist pattern is formed on the low resistance metal film, and the low resistance metal film is etched using this as a mask to form a gate electrode 52.

【0006】次いでゲ−ト絶縁膜53としてシリコン酸
化膜又はシリコン窒化膜若しくはこれら絶縁膜の積層膜
をプラズマCVD法等を用いて全面に堆積する。次にこ
のゲ−ト絶縁膜53上に活性層60となるアモルファス
シリコン膜,チャネル保護膜61となるシリコン窒化膜
を順次堆積する。次にこのアモルファスシリコン膜及び
シリコン窒化膜をフォトリソグラフィを用いてパタ−ン
ニングし、活性層60,チャネル保護膜61を形成す
る。
Next, as the gate insulating film 53, a silicon oxide film, a silicon nitride film, or a laminated film of these insulating films is deposited on the entire surface by plasma CVD or the like. Next, an amorphous silicon film to be the active layer 60 and a silicon nitride film to be the channel protection film 61 are sequentially deposited on the gate insulating film 53. Next, the amorphous silicon film and the silicon nitride film are patterned using photolithography to form an active layer 60 and a channel protection film 61.

【0007】次いで活性層60,チャネル保護膜61上
にコンタクト層62を形成した後、TFT部を島状にパ
タ−ニングする。次に画素電極54となる透明導電膜、
例えば、ITO(Indium Tin Oxide)
膜を堆積し、これをフォトリソグラフィを用いて所定の
形状にパタ−ンニングして画素電極54を形成し、続い
てゲ−ト電極65のコンタクトを捕るためのスルーホ−
ルを開口する。最後に、Al等の電極材料を基板51上
に堆積し、これを所定の形状にパタ−ニングしてドレイ
ン電極63,ソ−ス電極64を形成する。
Next, after forming a contact layer 62 on the active layer 60 and the channel protective film 61, the TFT portion is patterned in an island shape. Next, a transparent conductive film to be the pixel electrode 54,
For example, ITO (Indium Tin Oxide)
A film is deposited, and the film is patterned into a predetermined shape by photolithography to form a pixel electrode 54, and then a through hole for capturing a contact of the gate electrode 65.
Open the door. Finally, an electrode material such as Al is deposited on the substrate 51 and patterned into a predetermined shape to form a drain electrode 63 and a source electrode 64.

【0008】以上述べたTFTの製造方法では、フォト
リソグラフィ技術を用いてTFTを構成する各種膜や層
等を形成している。このため、フォトリソグラフィ技術
におけるマスクパタ−ン間の位置合せの良否は、TFT
に大きな影響を与える。
In the above-mentioned TFT manufacturing method, various films and layers constituting the TFT are formed by using the photolithography technique. Therefore, the quality of the alignment between the mask patterns in the photolithography technique depends on the TFT.
Have a great influence on.

【0009】即ち、上記の如きTFTの製造方法では、
6枚から7枚程度のフォトマスクを必要するが、各フォ
トマスク間のずれを全て所定の精度内に収めるのが困難
であるため、TFT特性や表示特性が低下し、製造歩留
まりが悪いという問題があった。
That is, in the method of manufacturing a TFT as described above,
Although about 6 to 7 photomasks are required, it is difficult to keep all the shifts between the photomasks within a predetermined accuracy, so that the TFT characteristics and display characteristics are deteriorated and the manufacturing yield is low. was there.

【0010】また、従来の対向基板68においては、ブ
ラックマトリクス58が画素電極54上まで延在してい
た。これはアレイ基板67と対向基板68とで液晶層5
5を挾持する際に、アレイ基板67と対向基板68とが
ずれても、TFT69がブラックマトリクス58で覆わ
れるように、ブラックマトリクス58に合わせマ−ジン
を与えたからである。
Further, in the conventional counter substrate 68, the black matrix 58 extends onto the pixel electrode 54. The liquid crystal layer 5 is formed by the array substrate 67 and the counter substrate 68.
This is because the margin is applied to the black matrix 58 so that the TFT 69 is covered with the black matrix 58 even if the array substrate 67 and the counter substrate 68 are deviated when holding 5.

【0011】ブラックマトリクス58とTFT69との
位置合わせの良否は、表示装置の特性や性能や製造コス
トに大きな影響を与えるため上述した合わせマ−ジンの
導入は必要であるが、これにより各画素の表示面積は画
素電極54より小くなるため、開口率の低下が起こる。
The quality of the alignment between the black matrix 58 and the TFT 69 has a great influence on the characteristics and performance of the display device and the manufacturing cost. Therefore, it is necessary to introduce the alignment margin described above. Since the display area is smaller than that of the pixel electrode 54, the aperture ratio is reduced.

【0012】そこで、この種の不都合を解消するため
に、電解重合法を用いた製造方法が提案された。この方
法では、所望の電極と自己整合的に電解重合膜を形成で
きるので、フォトリソグラフィを用いずに所望の形状の
活性層やブラックマトリクスの形成が可能となる。
Therefore, in order to eliminate this kind of inconvenience, a manufacturing method using an electrolytic polymerization method has been proposed. In this method, the electrolytic polymerized film can be formed in a self-aligning manner with a desired electrode, so that it is possible to form an active layer and a black matrix having a desired shape without using photolithography.

【0013】しかしながら、フォトリソグラフィを用い
ずに成膜を行なうには、複雑なパタ−ンの電極を形成す
る必要があるので、製造プロセスや設計プロセスの点で
問題が生じる。また、電極パタ−ンを簡単にすれば、こ
のような問題が生じないが、不要な電解重合膜を除去す
る必要が生じるので、フォトリソグラフィ工程が不可欠
となる。これによりフォトマスク間のずれの問題が生じ
るのは勿論のこと、電解重合膜はポリマ−材料からなる
のでパタ−ニングに困難が生じ、この結果、必要精度で
の微細加工が行なえなくなり、信頼性が低下するという
問題も生じる。
However, in order to form a film without using photolithography, it is necessary to form an electrode having a complicated pattern, which causes a problem in the manufacturing process and the design process. Further, if the electrode pattern is simplified, such a problem does not occur, but it is necessary to remove an unnecessary electrolytically polymerized film, so that the photolithography process is indispensable. This causes a problem of misalignment between the photomasks, and the electrolytically polymerized film is made of a polymer material, which makes it difficult to perform patterning. As a result, it becomes impossible to perform fine processing with a required accuracy, resulting in reliability. There is also a problem that

【0014】[0014]

【発明が解決しようとする課題】上述の如く従来の液晶
表示装置では、アレイ基板の作成の際のフォトマスク間
のずれによりTFT特性や表示特性が低下し、製造歩留
まりが悪いという問題があった。また、TFTがブラッ
クマトリクスで確実に覆われるように、ブラックマトリ
クスに合わせマ−ジンを与えていたが、これにより開口
率が低下するという問題があった。また、電解重合法を
用いた合わせマ−ジン不要なブラックマトリクスの形成
方法も提案されたが、電極パタ−ンの複雑化を招くため
製造及び設計が困難になるという問題があった。
As described above, the conventional liquid crystal display device has a problem that the TFT characteristics and the display characteristics are deteriorated due to the displacement between the photomasks when the array substrate is formed, and the manufacturing yield is low. .. Further, a margin is provided in accordance with the black matrix so that the TFT is surely covered with the black matrix, but this causes a problem that the aperture ratio is lowered. Further, a method for forming a black matrix which does not require a composite margin using an electrolytic polymerization method has been proposed, but there is a problem in that manufacturing and designing becomes difficult because the electrode pattern becomes complicated.

【0015】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、製造や設計の困難を招
くことがない表示特性が優れた液晶表示装置及びその製
造方法を提供することにある。
The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display device having excellent display characteristics which does not cause difficulties in manufacturing and designing, and a manufacturing method thereof. Especially.

【0016】[0016]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の液晶表示装置は、マトリクス配列された
画素電極と、各画素電極に設けられた薄膜トランジスタ
と、この薄膜トランジスタを制御して画素電極に所望の
電圧を印加するためのゲ−ト線及び信号線とを有する液
晶表示装置において、前記画素電極上に形成された画素
電極保護膜と、この画素電極保護膜上以外の領域に形成
されたブラックマトリクスとを備えていることを特徴と
する。
In order to achieve the above object, the liquid crystal display device of the present invention controls pixel electrodes arranged in a matrix, thin film transistors provided in each pixel electrode, and controlling the thin film transistors. In a liquid crystal display device having a gate line and a signal line for applying a desired voltage to a pixel electrode, a pixel electrode protective film formed on the pixel electrode and a region other than the pixel electrode protective film And a formed black matrix.

【0017】また、本発明の液晶表示装置の製造方法
は、マトリクス配列された画素電極と、各画素電極に設
けられた薄膜トランジスタと、この薄膜トランジスタを
制御して画素電極に所望の電圧を印加するためのゲ−ト
線及び信号線とを有する液晶表示装置において、前記画
素電極上に画素電極保護膜を形成した後、電解重合法に
より画素電極保護膜以外の基板上の領域にブラックマト
リクスを形成することを特徴とする。
Further, according to the method of manufacturing a liquid crystal display device of the present invention, the pixel electrodes arranged in a matrix, the thin film transistors provided in each pixel electrode, and the thin film transistors are controlled to apply a desired voltage to the pixel electrodes. In a liquid crystal display device having a gate line and a signal line, a pixel electrode protective film is formed on the pixel electrode, and then a black matrix is formed on a region other than the pixel electrode protective film on the substrate by an electrolytic polymerization method. It is characterized by

【0018】[0018]

【作用】本発明の液晶表示装置では、ブラックマトリク
スが画素電極保護膜以外の領域に形成されている。即
ち、薄膜トランジスタが設けられた基板上に形成されて
いるので、上記基板と対向基板との合わせずれで、ブラ
ックマトリクスと薄膜トランジスタアレイとがずれるこ
とはない。したがって、ブラックマトリクスに合わせマ
−ジンを持たす必要がなくるので開口率の低下を防止で
き、もって表示特性の改善が図れる。
In the liquid crystal display device of the present invention, the black matrix is formed in a region other than the pixel electrode protective film. That is, since the thin film transistor is formed on the substrate, the black matrix and the thin film transistor array do not shift due to misalignment between the substrate and the counter substrate. Therefore, since it is not necessary to have a margin for the black matrix, it is possible to prevent the aperture ratio from lowering, thereby improving the display characteristics.

【0019】また、本発明の液晶表示装置の製造方法で
は、画素電極上に画素電極保護膜を設けているので、画
素電極保護膜と自己整合的にブラックマトリクスを形成
できる。したがって、複雑な電極配線を設計したり製造
する必要がないので容易に表示特性の改善が図れる。
Further, in the method for manufacturing a liquid crystal display device of the present invention, since the pixel electrode protective film is provided on the pixel electrode, the black matrix can be formed in self-alignment with the pixel electrode protective film. Therefore, it is not necessary to design or manufacture a complicated electrode wiring, so that the display characteristics can be easily improved.

【0020】[0020]

【実施例】本実施例の液晶表示装置の構成は基本的には
従来のものと同じで、スイッチング素子としてのTFT
や画素電極等からなるアレイ基板及び対向基板と、この
アレイ基板と対向基板とに挟まれた液晶層とからなる基
本構成をとっている。本実施例の液晶表示装置の特徴
は、マトリクス配列された各画素電極上に画素電極保護
膜が設けられ、この画素電極保護膜以外にブラックマト
リクスが形成されていることにある。
EXAMPLE The structure of the liquid crystal display device of this example is basically the same as that of the conventional one, and a TFT as a switching element is used.
It has a basic configuration including an array substrate and a counter substrate including pixel electrodes and the like, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. A feature of the liquid crystal display device of the present embodiment is that a pixel electrode protective film is provided on each pixel electrode arranged in a matrix, and a black matrix is formed in addition to the pixel electrode protective film.

【0021】図1は本実施例に係る液晶表示装置のアレ
イ基板の製造工程平面図であり、図2は図1のアレイ基
板のA−A´断面図であり、図3は図1(c)のB−B
´断面図である。
FIG. 1 is a plan view of a manufacturing process of an array substrate of a liquid crystal display device according to this embodiment, FIG. 2 is a sectional view taken along the line AA ′ of the array substrate of FIG. 1, and FIG. ) BB
′ It is a cross-sectional view.

【0022】上記の如き液晶表示装置を作成するには、
まず、図1(a),図2(a)に示すように、透光性絶
縁基板1上にゲ−ト線2(ゲ−ト電極)となるMoやM
o‐Ta等の低抵抗金属をスパッタ堆積し、これをパタ
−ニングしてゲ−ト線2を形成する。次にゲ−ト線2を
シリコン酸化膜又はシリコン窒化膜若しくはこれら絶縁
膜の積層膜等からなるゲ−ト絶縁膜3で覆う。
To make a liquid crystal display device as described above,
First, as shown in FIGS. 1 (a) and 2 (a), Mo or M to be the gate line 2 (gate electrode) is formed on the translucent insulating substrate 1.
A low resistance metal such as o-Ta is sputter-deposited and patterned to form a gate line 2. Next, the gate line 2 is covered with a gate insulating film 3 made of a silicon oxide film, a silicon nitride film, or a laminated film of these insulating films.

【0023】次いで画素電極4及びソ−ス電極となる透
明導電膜、例えば、ITO(Indium Tin O
xide)膜を基板1上に堆積し、これをフォトリソグ
ラフィを用いてパタ−ンニングして画素電極4を形成す
る。このとき全ての画素電極4が互いに電気的に短絡し
ているように透明導電膜をパタ−ニングする。更に、画
素電極4間の透明電極配線4aの幅をプロセス上可能な
最小幅とし、ゲ−ト線2と画素電極4との重なり面積を
できる限り小さくする。この後、ゲ−ト線2とのコンタ
クトを取るためのスルーホ−ルをゲ−ト絶縁膜3に開口
する。
Next, a transparent conductive film which becomes the pixel electrode 4 and the source electrode, for example, ITO (Indium Tin O) is used.
xide) film is deposited on the substrate 1 and patterned by photolithography to form the pixel electrode 4. At this time, the transparent conductive film is patterned so that all the pixel electrodes 4 are electrically short-circuited with each other. Further, the width of the transparent electrode wiring 4a between the pixel electrodes 4 is set to the minimum width that can be processed, and the overlapping area between the gate line 2 and the pixel electrode 4 is made as small as possible. After that, a through hole for making contact with the gate line 2 is opened in the gate insulating film 3.

【0024】次いで図1(b),図2(b)に示す如
く、信号線5となる金属膜、例えば、Mo/Al膜やC
r/Al膜等の積層金属膜をゲ−ト絶縁膜3上に堆積
し、これをフォトリソグラフィを用いてパタ−ニングし
所定パタ−ンの信号線5を形成する。次に画素電極4上
にシリコン窒化膜等の絶縁膜からなる画素電極保護膜6
を形成する。次に電解重合法を用いてブラックマトリク
ス7を形成する。この電解重合法を3電極式で行なう場
合には、信号線5と画素電極4(透明電極配線4a)と
を作用電極として用いる。このとき十分大きな電流を作
用電極に与えることで画素電極保護膜6を除く全ての領
域にブラックマトリクス7を形成することができる。即
ち、画素電極保護膜6と自己整合的にブラックマトリク
ス7を形成できる。
Then, as shown in FIGS. 1B and 2B, a metal film to be the signal line 5, such as a Mo / Al film or C, is formed.
A laminated metal film such as an r / Al film is deposited on the gate insulating film 3 and patterned by photolithography to form the signal line 5 having a predetermined pattern. Next, a pixel electrode protective film 6 made of an insulating film such as a silicon nitride film is formed on the pixel electrode 4.
To form. Next, the black matrix 7 is formed by using the electrolytic polymerization method. When this electrolytic polymerization method is performed by a three-electrode system, the signal line 5 and the pixel electrode 4 (transparent electrode wiring 4a) are used as working electrodes. At this time, by supplying a sufficiently large current to the working electrode, the black matrix 7 can be formed in all regions except the pixel electrode protective film 6. That is, the black matrix 7 can be formed in self-alignment with the pixel electrode protection film 6.

【0025】ここでブラックマトリクス7が他の膜に影
響を与えないために、その絶縁性を確保する必要があ
る。ブラックマトリクス7の絶縁性を確保するには、ブ
ラックマトリクス7の材料に応じて還元又は酸化すれば
良い。例えば、ブラックマトリクス7がポリピロ−ルか
らなる場合には、ポリピロ−ルを還元すれば良い。これ
は酸化状態では良導電性を示すが、還元状態ではその導
電性を殆ど失うというポリピロ−ルの性質による。な
お、画素電極保護膜6は上記還元処理又は酸化処理の影
響が他の膜には及ぶのを防止する役割も果たしている。
Here, since the black matrix 7 does not affect other films, it is necessary to ensure its insulating property. In order to ensure the insulating property of the black matrix 7, it may be reduced or oxidized depending on the material of the black matrix 7. For example, when the black matrix 7 is made of polypyrrole, the polypyrrole may be reduced. This is due to the property of polypyrrole that it exhibits good conductivity in the oxidized state but loses its conductivity in the reduced state. The pixel electrode protection film 6 also plays a role of preventing the influence of the reduction treatment or the oxidation treatment from reaching other films.

【0026】次いで図1(c),図2(c),図3に示
す如く、保護膜8を全面に堆積した後、活性層9となる
領域の保護膜8に開口部を形成し、続いて、この開口部
内のブラックマトリクス7を溶媒を用いて除去する。ブ
ラックマトリクス7は通常のフォトリソグラフィでは精
度の良い加工ができないが、このように開口部をマスク
を用いた溶媒による除去処理を行なえば、精度の良い加
工ができる。次に信号線5と画素電極4とを作用電極に
用いた電解重合法により活性層9を形成する。このとき
開口部以外は保護膜8が形成されているので、活性層9
は開口部と自己整合的に形成される。ことのき活性層9
以外は保護膜8で覆われているので、活性層9の電気的
特性を確保するために、作用電極に電圧を印加して活性
層9のド−ピング又は脱ド−ピングを行なっても、活性
層9のみが電解液に浸されるので他の膜に悪影響が及ぶ
ことはない。
Then, as shown in FIGS. 1C, 2C, and 3, after depositing the protective film 8 on the entire surface, an opening is formed in the protective film 8 in the region to be the active layer 9. Then, the black matrix 7 in this opening is removed using a solvent. The black matrix 7 cannot be processed with high precision by ordinary photolithography, but by performing the removal processing of the opening portion with a solvent using a mask in this manner, high-precision processing can be performed. Next, the active layer 9 is formed by an electrolytic polymerization method using the signal line 5 and the pixel electrode 4 as working electrodes. At this time, since the protective film 8 is formed except the opening, the active layer 9
Are formed in self-alignment with the openings. Kotonoki Active Layer 9
Since the others are covered with the protective film 8, even if a voltage is applied to the working electrode to dope or de-dope the active layer 9 in order to secure the electrical characteristics of the active layer 9, Since only the active layer 9 is immersed in the electrolytic solution, the other films are not adversely affected.

【0027】最後に、チャネル保護膜10を形成した
後、各画素電極4を分離するために、ゲ−ト線2と透明
電極配線4aとが重なっている部分にスルーホ−ル11
を開口する。上述したように透明電極配線4aの幅はで
きる限り小さくしてあるので、残った透明電極配線4a
とゲ−ト線2とで形成される寄生容量は十分小さくな
り、その影響は無視できる。
Finally, after forming the channel protective film 10, in order to separate each pixel electrode 4, a through hole 11 is formed in a portion where the gate line 2 and the transparent electrode wiring 4a overlap each other.
To open. Since the width of the transparent electrode wiring 4a is made as small as possible as described above, the remaining transparent electrode wiring 4a
The parasitic capacitance formed by the gate line 2 and the gate line 2 becomes sufficiently small, and its influence can be ignored.

【0028】かくして本実施例によれば、ブラックマト
リクス7をアレイ基板上に自己整合的に形成できるの
で、ブラックマトリクス7の合わせマ−ジンが不要とな
り、もって開口率の低下を防止できる。また、活性層9
もフォトリソグラフィを用いずに形成できるのでフォト
マスク合わせの回数が少なくなり、もってTFT特性や
表示特性を改善や信頼性の向上が図れる。
Thus, according to this embodiment, since the black matrix 7 can be formed on the array substrate in a self-aligning manner, the alignment margin of the black matrix 7 is not required, so that the reduction of the aperture ratio can be prevented. In addition, the active layer 9
Since it can be formed without using photolithography, the number of times of photomask alignment is reduced, so that TFT characteristics and display characteristics can be improved and reliability can be improved.

【0029】図4は本発明の第2の実施例に係る液晶表
示装置のアレイ基板の平面図であり、図5,図6はそれ
ぞれ図4のアレイ基板のA−A´,B−B´断面図であ
る。なお、図1〜図3のアレイ基板と対応する部分には
図1〜図3と同一符号を付し、詳細な説明は省略する。
FIG. 4 is a plan view of an array substrate of a liquid crystal display device according to a second embodiment of the present invention, and FIGS. 5 and 6 are AA ′ and BB ′ of the array substrate of FIG. 4, respectively. FIG. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0030】これを製造工程に従い説明すると、まず、
透光性絶縁基板1上にゲ−ト線2を形成する際に、補助
容量電極12も同時に形成する。このとき補助容量電極
12の形状として図4に示すように後工程で形成する画
素電極4が囲まれるようなものを採用する。
This will be described according to the manufacturing process.
When the gate line 2 is formed on the translucent insulating substrate 1, the auxiliary capacitance electrode 12 is also formed at the same time. At this time, as the shape of the auxiliary capacitance electrode 12, a shape that surrounds the pixel electrode 4 formed in a later step as shown in FIG. 4 is adopted.

【0031】次いで先の実施例と同様に、ゲ−ト絶縁膜
3,画素電極4,信号線5,画素電極保護膜6を順次形
成した後、ネガ型フォトレジストを塗布し、基板1の裏
面から光を照射してフォトレジストの感光を行ない、続
いてフォトレジストの現像を行なうことでゲ−ト線2,
補助容量電極12上のフォトレジストを選択的に除去で
きる。
Then, similarly to the previous embodiment, the gate insulating film 3, the pixel electrode 4, the signal line 5 and the pixel electrode protective film 6 are sequentially formed, and then a negative photoresist is applied to the back surface of the substrate 1. The photoresist is exposed by irradiating light from the gate line, and then the photoresist is developed.
The photoresist on the auxiliary capacitance electrode 12 can be selectively removed.

【0032】次いで残ったフォトレジストをマスクに用
いて画素電極保護膜6をエッチングした後、電解重合法
を用いてブラックマトリクス7を形成する。次にブラッ
クマトリクス7上に保護膜8を形成し、この保護膜8上
にネガ型フォトレジストを塗布する。そして裏面露光に
よりレジストパタ−ンを形成し、これをマスクにして保
護膜8を除去し、続いてこの除去した保護膜8下部のブ
ラックマトリクス7も除去する。この結果、ゲ−ト線2
及び補助容量電極12と自己整合的に同じ配線幅を有す
る開口を形成できる。次に電解重合法を用いて活性等9
となる半導体層を形成した後、この半導体層にチャネル
幅方向のパタ−ンニングを施し、活性層9を形成する。
このとき素子として機能しない半導体層13が形成され
るが、これは装置に何等影響を与えないのでこのまま残
す。最後に、チャネル保護膜10を形成してTFTが完
成する。
Next, the pixel electrode protective film 6 is etched using the remaining photoresist as a mask, and then the black matrix 7 is formed by electrolytic polymerization. Next, a protective film 8 is formed on the black matrix 7, and a negative photoresist is applied on the protective film 8. Then, a resist pattern is formed by backside exposure, the protective film 8 is removed by using this as a mask, and then the black matrix 7 under the removed protective film 8 is also removed. As a result, the gate line 2
Also, an opening having the same wiring width as the auxiliary capacitance electrode 12 can be formed in a self-aligning manner. Next, using an electrolytic polymerization method, activity 9
After forming the semiconductor layer to be the active layer 9, the semiconductor layer is patterned in the channel width direction to form the active layer 9.
At this time, the semiconductor layer 13 that does not function as an element is formed, but this does not affect the device at all and is left as it is. Finally, the channel protection film 10 is formed to complete the TFT.

【0033】本実施例の場合でも先に述べた実施例と同
様な効果が得られる。更に、本実施例では、画素電極4
を囲うような補助容量電極12を形成したので、画素電
極保護膜6を位置を正確に決めることができ、所定の領
域にブラックマトリクス7を確実に形成できる。加えて
保護膜8はゲ−ト線2と自己整合的に形成されるので、
これによりチャネル方向の寸法が正確な活性層9が得ら
れる。以上の結果、TFT特性や表示特性が更に改善さ
れる。
Also in the case of this embodiment, the same effect as that of the above-mentioned embodiment can be obtained. Further, in this embodiment, the pixel electrode 4
Since the auxiliary capacitance electrode 12 that surrounds the pixel electrode protective film 6 is formed, the position of the pixel electrode protective film 6 can be accurately determined, and the black matrix 7 can be reliably formed in a predetermined region. In addition, since the protective film 8 is formed in self-alignment with the gate line 2,
As a result, the active layer 9 having an accurate dimension in the channel direction can be obtained. As a result, the TFT characteristics and display characteristics are further improved.

【0034】なお、本発明は上述した実施例に限定され
るものではない。例えば、上記実施例では、信号線を形
成した後に画素電極保護膜を形成したが、画素電極保護
膜を形成した後に信号線を形成しても同様な効果が得ら
れる。また、TFT以外のスイッチング素子を用いた場
合にも同様にして自己整合的にブラックマトリクスをア
レイ基板上に形成できる。その他、本発明の要旨を逸脱
しない範囲で、種々変形して実施できる。
The present invention is not limited to the above embodiment. For example, in the above embodiment, the pixel electrode protective film is formed after forming the signal line, but the same effect can be obtained by forming the signal line after forming the pixel electrode protective film. Also, when a switching element other than the TFT is used, the black matrix can be similarly formed on the array substrate in a self-aligning manner. Besides, various modifications can be made without departing from the scope of the present invention.

【0035】[0035]

【発明の効果】以上詳述したように本発明によれば、ア
レイ基板上にブラックマトリクスを自己整合的に形成で
きるので、ブラックマトリクスの合わせマ−ジンや複雑
な電極が不必要になり、もって製造プロセスや設計プロ
セスに困難をきたすことなく、開口率等の表示特性の向
上を図ることができる。
As described above in detail, according to the present invention, since the black matrix can be formed on the array substrate in a self-aligning manner, the alignment matrix of the black matrix and the complicated electrode are not necessary. The display characteristics such as the aperture ratio can be improved without causing any difficulty in the manufacturing process and the design process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る液晶表示装置のアレイ
基板の製造工程平面図。
FIG. 1 is a plan view of a manufacturing process of an array substrate of a liquid crystal display device according to an embodiment of the present invention.

【図2】図1のアレイ基板のA−A´断面図。FIG. 2 is a cross-sectional view taken along the line AA ′ of the array substrate of FIG.

【図3】図1のアレイ基板のB−B´断面図。3 is a cross-sectional view of the array substrate of FIG. 1 taken along the line BB ′.

【図4】本発明の第2の実施例に係る液晶表示装置のア
レイ基板の平面図。
FIG. 4 is a plan view of an array substrate of a liquid crystal display device according to a second embodiment of the present invention.

【図5】図4のアレイ基板のA−A´断面図。5 is a cross-sectional view taken along the line AA ′ of the array substrate of FIG.

【図6】図4のアレイ基板のB−B´断面図。6 is a cross-sectional view taken along the line BB ′ of the array substrate of FIG.

【図7】従来の液晶表示装置の断面図。FIG. 7 is a cross-sectional view of a conventional liquid crystal display device.

【図8】従来のアレイ基板の平面図。FIG. 8 is a plan view of a conventional array substrate.

【符号の説明】 1…透光性絶縁基板、2…ゲ−ト線、3…ゲ−ト絶縁
膜、4…画素電極、5…信号線、6…画素電極保護膜、
7…ブラックマトリクス、8…保護膜、9…活性層、1
0…チャネル保護膜、11…スルーホ−ル、12…補助
容量電極、51…透光性絶縁基板、52…ゲ―ト電極,
53…ゲ−ト絶縁膜,54…画素電極,55…液晶層,
56…対向電極,57…カラ―フィルタ―,58…ブラ
ックマトリクス,59…透光性絶縁基板,60…活性
層,61…保護膜,62…コンタクト層,63…ドレイ
ン電極,64…ソ―ス電極,65…ゲ−ト線,66…信
号線,67…アレイ基板,68…対向基板,69…TF
T。
[Explanation of Codes] 1 ... Transparent insulating substrate, 2 ... Gate line, 3 ... Gate insulating film, 4 ... Pixel electrode, 5 ... Signal line, 6 ... Pixel electrode protective film,
7 ... Black matrix, 8 ... Protective film, 9 ... Active layer, 1
0 ... Channel protective film, 11 ... Through hole, 12 ... Auxiliary capacitance electrode, 51 ... Translucent insulating substrate, 52 ... Gate electrode,
53 ... Gate insulating film, 54 ... Pixel electrode, 55 ... Liquid crystal layer,
56 ... Counter electrode, 57 ... Color filter, 58 ... Black matrix, 59 ... Translucent insulating substrate, 60 ... Active layer, 61 ... Protective film, 62 ... Contact layer, 63 ... Drain electrode, 64 ... Source Electrodes, 65 ... Gate lines, 66 ... Signal lines, 67 ... Array substrate, 68 ... Counter substrate, 69 ... TF
T.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板上にマトリクス配列された画素電極
と、 各画素電極に設けられたスイッチング素子としての薄膜
トランジスタと、 前記画素電極上に設けられ画素電極保護膜と、 この画素電極保護膜上以外の領域に形成されたブラック
マトリクスと、 同一行の前記薄膜トランジスタのゲ−トに接続されたゲ
−ト線と、 同一列の前記薄膜トランジスタの一方のソ−ス・ドレイ
ンに接続された信号線とを具備してなることを特徴とす
る液晶表示装置。
1. A pixel electrode arranged in a matrix on a substrate, a thin film transistor as a switching element provided on each pixel electrode, a pixel electrode protective film provided on the pixel electrode, and other than on the pixel electrode protective film. A black matrix formed in the region of, a gate line connected to the gates of the thin film transistors in the same row, and a signal line connected to one source / drain of the thin film transistors in the same column. A liquid crystal display device comprising:
【請求項2】基板上にゲ−ト線を形成する工程と、 信号線及び画素電極を形成する工程と、 前記画素電極上に画素電極保護膜を形成する工程と、 電解重合法により前記画素電極保護膜以外の前記基板上
の領域にブラックマトリクスを形成する工程とを具備し
てなることを特徴とする液晶表示装置の製造方法。
2. A step of forming a gate line on a substrate, a step of forming a signal line and a pixel electrode, a step of forming a pixel electrode protective film on the pixel electrode, and the pixel by an electrolytic polymerization method. And a step of forming a black matrix in a region on the substrate other than the electrode protection film.
JP25216791A 1991-09-30 1991-09-30 Liquid crystal display device and its manufacture Pending JPH0588200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25216791A JPH0588200A (en) 1991-09-30 1991-09-30 Liquid crystal display device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25216791A JPH0588200A (en) 1991-09-30 1991-09-30 Liquid crystal display device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0588200A true JPH0588200A (en) 1993-04-09

Family

ID=17233424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25216791A Pending JPH0588200A (en) 1991-09-30 1991-09-30 Liquid crystal display device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0588200A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7391052B2 (en) 1999-07-16 2008-06-24 Seiko Epson Corporation TFT structure for suppressing parasitic MOSFET in active display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7391052B2 (en) 1999-07-16 2008-06-24 Seiko Epson Corporation TFT structure for suppressing parasitic MOSFET in active display

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