JPH0587007B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to semiconductor manufacturing equipment, and more particularly to a semiconductor manufacturing equipment that initializes only the faulty part when a partial fault occurs in the equipment, and allows the entire equipment to continue operating.

[Background Art] With the automation of manufacturing in semiconductor manufacturing processes, efforts have been made to improve the functionality, automation, and throughput of semiconductor manufacturing equipment. With these advances in functionality, automation, etc., the devices themselves are becoming more complex and larger. Under such circumstances, when a device failure such as a malfunction occurs even once, the speed, simplicity, and reliability of recovery are extremely important.

Generally, the operations of a semiconductor manufacturing apparatus are as follows, and these operations are performed sequentially.

Device initialization.

Setting and capturing equipment operating parameters.

Select and transport the reticle to be used and align it with the device.

Supply and delivery of wafers.

Alignment and exposure of wafer and mask.

Collection and removal of wafers.

Regarding ~ above, the process of ~ is executed sequentially for one wafer,
This process is repeated for multiple wafers.

Now, for example, during the wafer supply and loading operation,
Assume that a failure occurs in the wafer transfer system and the operation sequence cannot proceed any further. At this time, in conventional semiconductor manufacturing equipment, the entire equipment is initialized (reset) at once. Therefore, in order to continue the previous process, the process from ~ to ~ must be repeated in the same way after resetting, which is inconvenient in that the equipment stops operating during this time, resulting in a drop in productivity (throughput). . Also, the masks that have already been adjusted will shift due to initialization. In this case, even if the misaligned masks are re-aligned, it is difficult to return them to the exact same condition as before, making it impossible to maintain the uniformity of the product, which also has a major drawback.

[Object of the Invention] In view of the above-mentioned problems of the prior art, the present invention makes it possible to recover from a failure by initializing only the failed unit without initializing the entire device when a partial failure occurs. It is an object of the present invention to provide a semiconductor manufacturing apparatus that can perform semiconductor manufacturing simply, quickly, and reliably.

[Description of Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows the appearance of a projection exposure apparatus according to an embodiment of the present invention. In the figure, 1 is a mask (reticle) provided with an integrated circuit pattern, and is also provided with mask alignment marks and mask-wafer alignment marks. 2 is a mask stage that holds mask 1 and moves mask 1 within a plane (XY
direction) and rotational direction (θ direction).
3 is a reduction projection lens; 4 is a wafer provided with a photosensitive layer, and is provided with a mask/wafer alignment mark and a television/wafer alignment mark. 5
is the wafer stage. The wafer stage 5 holds the wafer 4 and moves it in the plane and in the rotational direction, and also moves between the wafer printing position (within the projection field of view) and the television/wafer alignment position. 6 is an objective lens of a television/wafer alignment detection device; 7 is an image pickup tube or a solid-state image pickup device; and 9 is a binocular unit, which serves to observe the surface of the wafer 4 through the projection lens 3. 1
0 is an upper unit housing an illumination optical system and a detection device for mask-wafer alignment. 11 is a console monitor receiver (console CRT) that gives commands to the main body of the projection exposure apparatus; 12
is a keyboard for giving commands to the device and inputting parameters. 13 is a wafer transfer unit;
Unexposed wafers are supplied and transported to the wafer stage 5, and exposed wafers are recovered and transported. 14 is a mask changer unit that sets a specified mask on the mask stage 2 or retrieves the mask 1 on the mask stage 2.

FIG. 2 is a block diagram showing the electrical circuit configuration of the projection exposure apparatus of FIG. 1. In the same figure, 21
is the main CPU that controls the entire device and consists of a central processing unit such as a microcomputer or minicomputer. 22 is a wafer stage drive device, 23 is an alignment detection system, 24 is a reticle stage drive device, 25 is an illumination system, 26 is a shutter drive device, 27 is a focus detection system, and 28 is a Z drive device, which are controlled by the main CPU 21. controlled.

Further, 29 is a wafer transport system CPU that controls the entire wafer transport unit 13 (same as the one in FIG. 1) while exchanging information with the main CPU 21.
It consists of a central processing unit such as a microcomputer. A wafer transfer control system 30 controls wafer transfer based on commands from the wafer transfer system CPU 29.
31 exchanges information with the main CPU 21,
Mask changer unit 14 (same as the one in Figure 1) A mask changer that controls the entire mask changer unit 14 (same as the one in Figure 1).
It is the CPU. Reference numeral 32 denotes a mask changer control system, which controls mask change etc. based on commands from the mask changer CPU 31. Reference numeral 33 denotes a console unit for giving various commands and parameters regarding the operation of this exposure apparatus to the main body CPU 21. 34 is a console CPU, and 35 is an external memory for storing parameters and the like. In addition,
The CRT 11 and keyboard 12 are the same as those in FIG.

38 is a reset control system, which is a feature of the present invention. This reset control system 38 generates a signal to initialize (reset) each of the console unit 33, main CPU 21, wafer transfer unit 13, and mask changer unit 14 independently or simultaneously. It consists of a switch, a control circuit, etc.

FIG. 3 is a schematic flowchart focusing on the operation of the main body of this device.

Referring to FIGS. 1 to 3, when the apparatus is first powered on, each part of the apparatus main body 21 to 28, the console unit 33, the wafer transfer unit 13, and the mask changer unit 14 are initialized ( Step S1). Next, operating parameters are set and input from the keyboard 12 of the console unit 33 (step S2). The input parameters are transferred to the main CPU 21 (step S3). Next, according to a command from the main body CPU 21, the mask changer unit 14 transports the specified mask onto the mask stage 2 and sets it (step S4). The mounted mask 1 is positioned at a fixed position on the main body by the reticle stage drive system 24 and alignment detection system 23 (step
S5). Next, the system waits for the start of processing from the console unit 33 (step S6). Here, the start command is from the console keyboard 12.
When an input is made from the , this information is transmitted to the main CPU 21 . The main body CPU 21 issues a command to the wafer transfer unit 13 to place the wafer on the wafer stage 5, and the wafer is thereby supplied to the wafer stage 5 (step S7). Next, the wafer 4 and the mask 1 are aligned (step S8). Then, the shutter is opened and the pattern on the mask 1 is transferred and exposed onto the wafer 4 (step S9). Next, a command is sent from the main body CPU 21 to the wafer transport unit 13, and the exposed wafer is collected (step S10). This completes the exposure of one wafer. Next, it is checked whether exposure has been completed for all the wafers in one lot (step S11), and if there are any unexposed wafers, steps S7 to S11 are repeated to print all the wafers in one lot. When all the batches for one lot are completed in step S11, the process returns to the state of waiting for the start of step S6. The above is a general outline of the normal operation of this device.

Next, as an explanation of the operation of the apparatus of this embodiment, when the wafer is transferred (supplied) in step S7, an accidental failure occurs in the wafer transfer unit 13, and no matter how long the wafer waits, the wafer is not fed onto the wafer stage 4. Taking as an example a situation in which the failure occurs, the recovery operation for this failure will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a detailed flowchart of step S7 in FIG. FIG. 5 is an operational flowchart when the wafer transfer system unit 13 is initialized (reset).

First, normal operation will be explained with reference to FIG.
The main body CPU 21 sends a wafer supply command to the wafer transfer unit 13 (step S7-
1). After that, the CPU 21 transfers the wafer to the wafer transfer unit 1.
3 (step S7-2). When the CPU 21 receives some kind of signal, it exits this loop and enters the next step. Then, it is checked whether the received information indicates that wafer supply is complete (step S7-3). If the supply is complete, this means that the wafer supply in step S7 has been completed normally.
The sequence proceeds to step S8 (FIG. 1).

At this point, an accidental failure occurred in the wafer transport system.
Suppose that the loop of waiting for reception in step S7-2 is kept repeating. Generally, an error message will be displayed here. Here the operator
The wafer transfer unit reset switch in the reset control system 38 initializes (resets) the wafer transfer unit 13. Then, the operation of the unit 13 becomes as shown in the flowchart of FIG. First, the unit 13 is initialized (step S20). Next, the unit 1
3 notifies the main CPU 21 that initialization has started (step S21). Through this communication, the main CPU2
1 exits the loop of step S7-2 and returns to step S7-2.
Make the determination in step S7-4 ``YES'' via S7-3.
Exit with. As a result, the main body CPU 21 detects that the wafer transfer unit 13 has been reset (step S7-4).

Next, the state in which the main body CPU 21 has been waiting is transmitted as corresponding wafer transfer unit state information to the unit 13 (step S7-5). Then, this communication causes the unit 13 to exit the information waiting loop (step S22) and return to the main unit.
The operation sequence advances to the state of the unit 13 corresponding to the state in which the CPU 21 was waiting (step S23). Next, the unit 13 communicates to the main body CPU 21 that the main body CPU 21 has returned to the waiting state as a recovery completion message (step S24). Through this communication, the main body CPU 21 exits the loop of steps S7-6 and S7-7 and starts going through the loop of step S7-2 again. At this point, the operation sequence of the unit 13 that has completed the process of step S24 branches to normal operation, and after the wafer supply is completed, the unit 13 sends the wafer supply completion communication to the main unit.
Send to CPU21. Through this communication, the main CPU 21
exits the loop of step S7-2 and returns to step S7
The determination of -3 is cleared with "YES", indicating that the wafer supply operation has been completed normally. Recovery from a failure is performed in the manner described above.

In addition, in the above embodiment, the main CPU 21
Although the failures with the wafer transfer unit 13 and the wafer transfer unit 13 have been described above, the console unit 33 and the mask changer unit 14 can also be recovered from failures in exactly the same manner.

Further, in the above embodiment, the initialization (resetting) of the wafer transfer system unit is performed by a switch provided in the reset control system 38, but it may also be performed by a command from the keyboard 12 of the console unit 33. .

[Effects of the Invention] As explained above, according to the present invention, since only a partially failed unit in a semiconductor device is initialized and processing is continued, failure recovery of the device can be performed easily, quickly and easily. This can be done reliably and has a great effect on improving productivity (improving throughput). It is also very effective in maintaining uniformity of products.

[Brief explanation of the drawing]

FIG. 1 is an external view of a projection exposure apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing a control circuit of the projection exposure apparatus of the above embodiment, and FIG. 3 is a block diagram of the apparatus of the above embodiment. FIGS. 4 and 5 are flowcharts for explaining the detailed operation of the apparatus of the above embodiment. 1...Mask (reticle), 4...Wafer, 1
1... CRT for monitor, 12... Keyboard, 1
3...Wafer transfer unit, 14...Mask changer unit, 21...Main CPU, 29
...Wafer transfer system CPU, 30...Wafer transfer control system, 31...Mask changer CPU, 32
...Mask changer control system, 33...Console unit, 38...Reset control system.

Claims (1)

[Scope of Claims] 1. Means for individually initializing each component unit when an accidental partial failure occurs in a plurality of component units constituting the device, and continuing the processing of the device after the initialization. A semiconductor manufacturing apparatus characterized by comprising: a control means. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the control means continues processing of the apparatus after automatically restoring the faulty constituent unit to the state immediately before the fault occurred.