JPH058456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a store-in type hierarchical storage device in which data is transferred from a buffer memory that holds a portion of data held in the main memory as a copy to the main memory. Concerning write-back control method.

[Prior art] In conventional store-in buffer memory,
If the data already held in the block where the data is replaced has been written, a change bit is displayed based on the read result of the change array as shown in Tokusei No. 57-162168. It is determined whether to write back to the main memory (referred to as lineback). Therefore, in a hierarchical storage device having a store-in type buffer memory, the address array of the buffer memory is searched based on the request and the address, it is determined whether the corresponding block exists on the buffer memory, and if the block does not exist, it is replaced. A determining circuit determines a replace block, and a corresponding change bit determines a line back.

Generally, in a hierarchical storage device, it is known that when a failure occurs in buffer storage, address array, etc., the failure can be recovered by isolating the failed part. However, in the above-mentioned hierarchical device, when a failure occurs in the buffer storage device, the failed part is isolated and the process is operated in the most reduced configuration.If a failure occurs in the changeable array, the failed part is further isolated and processing cannot continue. This makes it difficult to correctly execute lineback, which becomes a serious problem that can lead to data destruction and system stoppage, and significantly lowers reliability.

[Problem that the invention seeks to solve]

In a store-in type hierarchical storage device, if a failure occurs in the buffer storage device and the buffer storage is operated in the most reduced configuration, and if a failure occurs in the chained array, data destruction will cause a serious failure in the system and reliability will be reduced. There was a problem where the performance decreased significantly.

An object of the present invention is to avoid the occurrence of serious failures in the system during the above-mentioned conditions and to ensure reliability.

[Means for solving problems]

In order to achieve the above object, there is provided a determination circuit that determines whether or not the configuration of the buffer memory from which the failed row is separated is in the most reduced state; and control means that suppresses store-in control only when replacing a block, and always lines back data already held in the block to the main memory, regardless of the value of a change bit corresponding to the block. It has been established.

[Effect]

Control by the store-in method is suppressed only when it is determined that the configuration of the buffer memory from which the faulty row has been separated is in the most reduced state, and only when refreshing a block in the buffer memory is performed. Regardless of the value of the change bit corresponding to the block, the data already held in the block is always line-backed to the main memory, and if the target data is held in the buffer memory, control is performed using the store-in method, and the target data is A lineback to the data main memory is not performed.

This minimizes the amount of data transferred between the buffer storage and the main storage, and furthermore, even if a failure occurs in the change array of the buffer storage, the data can be written to the block even if a failure occurs in the change array of the buffer storage. Since the data that has been replaced is always line-backed to the main storage device during replacement, data is not destroyed and serious failures such as system stoppage do not occur.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a buffer storage control unit according to an embodiment of the present invention, where 110 is an address array for the buffer storage, which is divided into rows 111 to 114, and processing can be executed by separating rows 111 to 114. . In the buffer address array 110, address information is registered for each block. 1
20 is a replacement array in which LRU (Least Recertly Used) algorithm information is registered, and 130 and 140 are duplicated change arrays in which change bits are stored in one-to-one correspondence for each block in the buffer memory. ing. 150
is a disconnection status register that sets the row information of the buffer memory disconnected due to a failure, and has a 1-bit flipflop for each row.
Reference numeral 51 denotes a line back control circuit which controls whether or not to enter a mode in which line back is always performed. An example of the processing operation will be sequentially explained below.

Request address is address register 100
When set to , buffer address array 110 is searched by part of the address and row 111
The corresponding address information is read from each of the circuits 115 to 114 and input to the comparison circuits 115 to 118, respectively. The address information input to the comparison circuits 115 to 118 is compared with the comparison part of the address register 110, and the comparison result is sent to the comparison judgment circuit 11.
9, and if there is no data for the address in the buffer memory, the comparison/judgment circuit 11
9, the main memory request register 168 is set. The request address is input to the address register 101 via the address register 100, the replacement array 120 is searched using a part of the address of the address register 101, and the read result is input to the replacement block determination circuit 161. At the same time, some of the addresses in the address register 101 are used in the change arrays 130 and 140.
Search for rows 131-134, 141-144
The corresponding change bits are read out from each of the bits and input to OR circuits 162-165, respectively. The read results of the chained arrays 130 and 140 are also input to the fault detection circuit 160, and if a fault is detected, it is reported to the fault processing section. OR
The outputs of the circuits 162 to 165 and the replace block determined by the replace block determining circuit 161 are input to a line back determining circuit 166, and if writing has been performed in the buffer memory block to be replaced, the line back request register 167 is input. Set. The outputs of the main memory request register 168 and the lineback request register 167 are transmitted to the main memory request control circuit 1.
69 and sent to the main memory as a line back request.

In one embodiment, chain arrays 130, 140
If a failure is detected in the failure processing unit, a disconnection request is issued and the disconnection status register 15 is
The disconnection information is set to 0 and input to the lineback mode control circuit 151. The disconnect status register 150 is connected to the buffer address array 11.
The information is set in units of rows of 0, and the output of the register is input to a comparison/judgment circuit 119, which performs control to suppress comparison/judgment for disconnected rows.

If a fault is detected in the chain arrays 130 and 140 while two rows are disconnected and operating due to a fault, that is, two bits are set corresponding to the row in the disconnect status register 150, the fault processing unit issues a disconnection request. is sent. The disconnection request is input to the lineback mode control circuit 151 and the disconnection status register 15
With the current operating state set to 0, if the buffer storage is to be separated to the most reduced state by the disconnection request, the lineback mode register 152 is set. The outputs of the line back mode registers are input to the OR circuits 162 to 165, respectively, so the change array 13
The read result of 0,140 always has a change bit value of 1, and replacing the buffer memory is as follows:
The line back request register 167 is always set, and line back is always performed. As a result, the chain array 130, 140
Furthermore, even if a failure is detected, lineback is always performed and data is written back to the main memory, so reliability can be ensured without causing data destruction.

〔Effect of the invention〕

As explained above, according to the present invention, when the buffer memory operates in the most reduced configuration, and only when replacing a block, the data already held in the block can be transferred to the main memory without depending on the value of the change bit. Since lineback is performed to the device and not to the main memory when replacement is not necessary, the amount of data transferred between the buffer memory and the main memory is minimized, and the configuration of the buffer memory is minimized. Therefore, even if a failure occurs in the chain array, data will not be destroyed and reliability can be ensured.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 100, 101...Request address register, 110...Buffer address array, 115
~118... Compare circuit, 119... Comparison/judgment circuit, 120... Replacement array, 13
0,140...Change array, 150...Disconnection status register, 151...Line back mode control circuit, 152...Line back mode register, 160...Failure detection circuit, 161...Replace block determination circuit, 162-165 ……
OR circuit, 166... Line back judgment circuit, 1
67... Line back request register, 168...
Main memory request register, 169...Main memory request control circuit.

Claims (1)

[Scope of Claims] 1. A main storage device, which is divided into a plurality of rows, holds part of the data held by the main storage device in block units, and when a failure occurs, the failed part is a buffer memory that can be operated separately on a row-by-row basis; and a change array that stores a change bit that corresponds to each block in the buffer memory and indicates whether or not data held in the block has been written. A determination circuit that determines whether the configuration of the buffer memory from which the failed row is separated is in the most reduced state, and a determination circuit that determines that the configuration is in the most reduced state. control by the store-in method is suppressed only when the data in the block is replaced, and the control by the store-in method is suppressed, and the data already held in the block is 1. A hierarchical storage control method, comprising: a control means for always writing back data stored in the main storage device.