JPH0582951A - Mounting method of semiconductor component - Google Patents

Mounting method of semiconductor component

Info

Publication number
JPH0582951A
JPH0582951A JP3241869A JP24186991A JPH0582951A JP H0582951 A JPH0582951 A JP H0582951A JP 3241869 A JP3241869 A JP 3241869A JP 24186991 A JP24186991 A JP 24186991A JP H0582951 A JPH0582951 A JP H0582951A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
wiring pattern
pattern
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3241869A
Other languages
Japanese (ja)
Inventor
Masakatsu Takaishi
雅克 高石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3241869A priority Critical patent/JPH0582951A/en
Publication of JPH0582951A publication Critical patent/JPH0582951A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns

Abstract

PURPOSE:To mount a semiconductor component accurately to a printed circuit board, in which a wide wiring pattern such as a power line and a narrow wiring pattern such as a signal line are mixed. CONSTITUTION:When bumps 2a, 2b formed to the electrodes of a semiconductor chip 1 are abutted against corresponding wiring patterns 3a, 3b composed of conductive ink printed on a printed circuit board 4 and the semiconductor chip 1 is connected electrically to the printed circuit board 4, the wiring pattern 3a having board line width in the wiring patterns 3a, 3b on the printed circuit board 4 side is formed by printing narrow wiring patterns 3a1, 3a2 consisting of conductive ink in parallel at an interval A2 of a limiting minimum interval or less capable of separating lines by printing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップなどの半
導体部品をフリップチップボンディングの手法によって
印刷回路基板上に実装する半導体部品の実装方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor component mounting method for mounting a semiconductor component such as a semiconductor chip on a printed circuit board by a flip chip bonding technique.

【0002】[0002]

【従来の技術】図2は、従来の半導体部品の実装方法の
各工程を示す図である。
2. Description of the Related Art FIG. 2 is a diagram showing each step of a conventional semiconductor component mounting method.

【0003】この実装方法は図2(A)に平面図で示す
ように半導体チップ11の各電極に形成されたバンプ1
2a,12bを介して、一般的なフリップチップボンデ
ィングの手法によって半導体チップ11を図2(B)に
示す印刷回路基板14上に実装する方法である。
In this mounting method, the bump 1 formed on each electrode of the semiconductor chip 11 as shown in the plan view of FIG.
This is a method of mounting the semiconductor chip 11 on the printed circuit board 14 shown in FIG. 2B by a general flip-chip bonding method via 2a and 12b.

【0004】半導体チップ11側の各バンプ12a,1
2bは、これらに対応させて印刷回路基板14上にスク
リーン印刷法によって描かれた導電性インクの配線パタ
ーン13a,13bに図2(B)に示すように対向配置
され、これらの間が仮圧着され、加熱溶融によって図2
(C)に示すように半導体チップ11のバンプ12a,
12bが印刷回路基板4の配線パターン13a,13b
に接続される。
The bumps 12a, 1 on the semiconductor chip 11 side
Corresponding to these, 2b are arranged opposite to the conductive ink wiring patterns 13a and 13b drawn on the printed circuit board 14 by the screen printing method, as shown in FIG. And is heated and melted, as shown in FIG.
As shown in (C), the bumps 12a of the semiconductor chip 11,
12b is the wiring patterns 13a and 13b of the printed circuit board 4.
Connected to.

【0005】[0005]

【発明が解決しようとする課題】ところで、上述した従
来の半導体部品の実装方法では、電源ラインなどの配線
抵抗を低く抑える必要から、印刷回路基板14上の配線
パターン13a,13bのうち、電源ラインなどに相当
する配線パターン13aの線幅は信号ラインなどの他の
配線パターン13bよりも線幅が広く設定されている。
By the way, in the above-described conventional method for mounting a semiconductor component, since it is necessary to suppress the wiring resistance of the power supply line or the like to a low level, the power supply line of the wiring patterns 13a and 13b on the printed circuit board 14 is to be suppressed. The line width of the wiring pattern 13a corresponding to, for example, is set wider than that of other wiring patterns 13b such as signal lines.

【0006】ところで、上記印刷回路基板14のような
微細回路をスクリーン印刷する場合の特性として、印刷
回路基板14における導電性インクの配線パターン13
a,13bの線幅と膜厚は比例関係にあり、線幅の広い
配線パターン13aは線幅の狭い配線パターン13bよ
りも膜厚が厚くなる。すなわち、上記印刷回路基板14
において配線パターン13aの線幅を50μm、配線パ
ターン13bの線幅を130μm、各配線パターン13
a,13b間の線間隔を130μmとした場合、配線パ
ターン13aの膜厚は3μm、配線パターン13bの膜
厚は9μmとなる。
By the way, as a characteristic when screen-printing a fine circuit such as the printed circuit board 14, a conductive ink wiring pattern 13 on the printed circuit board 14 is used.
The line width and the film thickness of a and 13b are in a proportional relationship, and the wiring pattern 13a having a wide line width is thicker than the wiring pattern 13b having a narrow line width. That is, the printed circuit board 14
In, the wiring pattern 13a has a line width of 50 μm, the wiring pattern 13b has a line width of 130 μm,
When the line spacing between a and 13b is 130 μm, the wiring pattern 13a has a film thickness of 3 μm and the wiring pattern 13b has a film thickness of 9 μm.

【0007】その結果、図2(C)に示すように、ボン
ディング時に線幅の広い配線パターン13aが位置ずれ
したりインクつぶれしたりして、隣の配線パターン13
bと短絡状態となってしまうという問題点がある。
As a result, as shown in FIG. 2C, the wiring pattern 13a having a wide line width is displaced or the ink is crushed during bonding, and the adjacent wiring pattern 13 is formed.
There is a problem that it is short-circuited with b.

【0008】したがって、本発明の目的は、電源ライン
など広幅の配線パターンと信号ラインなどの狭幅の配線
パターンとが混在する印刷回路基板への半導体部品の実
装を精度よく行うことのできる半導体部品の実装方法を
提供することである。
Therefore, an object of the present invention is to provide a semiconductor component capable of accurately mounting a semiconductor component on a printed circuit board in which a wide wiring pattern such as a power supply line and a narrow wiring pattern such as a signal line coexist. It is to provide the implementation method of.

【0009】[0009]

【課題を解決するための手段】本発明は、半導体部品の
電極に形成されたバンプを、印刷回路基板に印刷された
導電性インクからなる対応する配線パターンに突き合わ
せ、印刷回路基板に対して半導体部品を電気的に接続す
る実装方法において、印刷回路基板側の配線パターンの
うち線幅の広い配線パターンを、印刷で線間を分離でき
る限界最小間隔以下の間隔を隔てて、狭幅狭間隔の2本
の導電性インクの配線パターンを並列に印刷することに
よって形成することを特徴とする半導体部品の実装方法
である。
SUMMARY OF THE INVENTION According to the present invention, bumps formed on electrodes of a semiconductor component are butted against a corresponding wiring pattern made of conductive ink printed on a printed circuit board, and the semiconductor is mounted on the printed circuit board. In a mounting method for electrically connecting components, a wiring pattern having a wide line width of the wiring pattern on the printed circuit board side is separated by a distance equal to or smaller than a limit minimum distance that can separate the lines by printing, and a narrow width and a narrow space are provided. It is a method of mounting a semiconductor component, which is formed by printing wiring patterns of two conductive inks in parallel.

【0010】[0010]

【作用】本発明に従えば、印刷回路基板側に導電性イン
クの狭線幅・狭間隔配線パターンを2本並列に印刷して
形成される配線パターンは、時間の経過によって2本の
狭線幅・狭間隔配線パターン間が印刷インクの粘性によ
る広がりでつながって1本の配線パターンとなる。この
とき各配線パターンの線幅は狭く設定されているので、
1本になった上記配線パターンは線幅が広い割りに膜厚
は薄く形成されることになる。
According to the present invention, a wiring pattern formed by printing two narrow line width / narrow-spaced wiring patterns of conductive ink in parallel on the printed circuit board side has two narrow lines over time. The width / narrow-spaced wiring patterns are connected by the spread of the viscosity of the printing ink to form one wiring pattern. At this time, the line width of each wiring pattern is set narrow, so
The single wiring pattern has a thin film thickness despite its wide line width.

【0011】その結果、印刷回路基板側において、各配
線パターンは線幅に相違があるにもかかわらず膜厚がほ
ぼ均一になり、ボンディング時に配線パターンのインク
つぶれや位置ずれを起こすことなく半導体部品を印刷回
路基板に精度よく実装できる。
As a result, on the printed circuit board side, although the wiring patterns have different line widths, the film thicknesses are substantially uniform, and the semiconductor components are not crushed or misaligned during bonding. Can be accurately mounted on a printed circuit board.

【0012】[0012]

【実施例】図1は、本発明の一実施例である半導体部品
の実装方法を示す工程図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a process chart showing a semiconductor component mounting method according to an embodiment of the present invention.

【0013】この実装方法は半導体チップ1(図1
(D))の各電極に形成されたバンプ2a,2bを介し
て、フリップチップボンディングの手法によって半導体
チップ1を印刷回路基板4上に実装する方法であって、
まず図1(A)に示す印刷パターン5を用いて図1
(B)に示すようにガラス、セラミック、ポリエステル
フィルムなどからなる絶縁基板4a上に、銅インク、金
インク、銀インク、カーボンインクなどの導電性インク
の配線パターン3a,3bをスクリーン印刷法によって
印刷して印刷回路基板4を得る。
This mounting method is applied to the semiconductor chip 1 (see FIG.
(D) is a method of mounting the semiconductor chip 1 on the printed circuit board 4 by a flip chip bonding method via the bumps 2a and 2b formed on each electrode.
First, using the print pattern 5 shown in FIG.
As shown in (B), wiring patterns 3a and 3b of conductive ink such as copper ink, gold ink, silver ink, and carbon ink are printed on the insulating substrate 4a made of glass, ceramics, polyester film or the like by the screen printing method. The printed circuit board 4 is obtained.

【0014】上記印刷パターン5のうち、パターン5a
は半導体チップ1の電源用電極に形成されるバンプ2a
に対応する配線パターン3aを、ガラス、セラミック、
ポリエステルフィルムなどからなる絶縁基板4a上に印
刷するためのパターンであり、パターン5bは半導体チ
ップ1の信号用電極に形成されるバンプ2bに対応する
配線パターン3bを上記絶縁基板4a上に印刷するため
のパターンである。
Of the above print patterns 5, pattern 5a
Is a bump 2a formed on the power supply electrode of the semiconductor chip 1.
The wiring pattern 3a corresponding to
The pattern 5b is for printing on the insulating substrate 4a made of a polyester film or the like, and the pattern 5b is for printing the wiring pattern 3b corresponding to the bumps 2b formed on the signal electrodes of the semiconductor chip 1 on the insulating substrate 4a. Pattern.

【0015】上記各パターン5a,5bの線間隔Cは1
30μmに、またパターン5aの線幅Aは130μm
に、パターン5bの線幅Bは50μmに設定されてい
る。そのうちパターン5aは、線幅A1(=50μm)
の2本のパターン部5a1,5a2を線間隔A2(=3
0μm)を隔てて並列に配置したものである。この場合
の線間隔A2(=30μm)は、スクリーン印刷法で2
本の配線を分離印刷できる線間隔以下の間隔である。な
お、線幅50μmの配線は、スクリーン印刷法によって
印刷可能な線幅である。
The line spacing C between the patterns 5a and 5b is 1
30 μm and the line width A of the pattern 5a is 130 μm
In addition, the line width B of the pattern 5b is set to 50 μm. The pattern 5a has a line width A1 (= 50 μm)
The two pattern portions 5a1 and 5a2 of the line pattern A2 (= 3
0 μm) and are arranged in parallel. The line spacing A2 (= 30 μm) in this case is 2 by the screen printing method.
The spacing is equal to or less than the line spacing at which the book wiring can be separately printed. The wiring having a line width of 50 μm is a line width that can be printed by the screen printing method.

【0016】したがって、上記印刷パターン5を用いた
スクリーン印刷によって得られた印刷回路基板1上に
は、パターン5bに対応する線幅50μmの配線パター
ン3bと、パターン5aに対応する線幅130μmの配
線パターン3aとが印刷される。
Therefore, on the printed circuit board 1 obtained by screen printing using the above-mentioned printed pattern 5, a wiring pattern 3b having a line width of 50 μm corresponding to the pattern 5b and a wiring pattern having a line width of 130 μm corresponding to the pattern 5a. The pattern 3a is printed.

【0017】配線パターン3aは、印刷直後において
は、印刷パターン5におけるパターン5aの2本のパタ
ーン部5a1,5a2に対応する線幅50μmの配線パ
ターン3a1,3a2を線間隔30μmを隔てて並列配
置したものとなる。
Immediately after printing, the wiring pattern 3a has two wiring patterns 3a1 and 3a2 having a line width of 50 μm, which correspond to the two pattern portions 5a1 and 5a2 of the pattern 5a in the printing pattern 5, and are arranged in parallel at a line interval of 30 μm. Will be things.

【0018】ところが、上記配線パターン3a1,3a
2の線間隔30μmは、スクリーン印刷法によって分離
印刷可能な線間隔以下であるので、時間の経過とともに
印刷インクの粘性による広がりで、2本の配線パターン
3a1,3a2間がつながり、図1(C)に示すように
1本のパターンとなってしまう。
However, the wiring patterns 3a1 and 3a
Since the line interval of 30 μm of 2 is less than the line interval that can be separately printed by the screen printing method, the two wiring patterns 3a1 and 3a2 are connected with each other due to the spread due to the viscosity of the printing ink with the passage of time. ) Results in one pattern.

【0019】従来例で示したように、線幅50μmに印
刷した配線パターンの膜厚は3μmとなるので、上記2
本の配線パターン3a1,3a2から1本化される配線
パターン3aは、線幅130μm、膜厚3μmのパター
ンとなる。すなわち、印刷回路基板1上に印刷形成され
る各配線パターン3a,3bの膜厚は、線幅の相違に関
係なくほぼ均一に揃えられる。
As shown in the conventional example, since the wiring pattern printed with a line width of 50 μm has a film thickness of 3 μm, the above 2
The wiring pattern 3a obtained by unifying the wiring patterns 3a1 and 3a2 has a line width of 130 μm and a film thickness of 3 μm. That is, the film thickness of each wiring pattern 3a, 3b formed by printing on the printed circuit board 1 is made substantially uniform regardless of the difference in line width.

【0020】そこで、半導体チップ1側の各バンプ2
a,2bを、図1(D)に示すように印刷回路基板4側
の対応する各配線パターン3a,3bに突き合わせて仮
圧着し、加熱溶融によってこれらの間を接続し固着す
る。これによって、印刷回路基板4上に半導体チップ1
が実装される。
Therefore, each bump 2 on the semiconductor chip 1 side
As shown in FIG. 1 (D), a and 2b are butted against corresponding wiring patterns 3a and 3b on the printed circuit board 4 side, and are temporarily pressure-bonded, and are connected and fixed by heating and melting. As a result, the semiconductor chip 1 is mounted on the printed circuit board 4.
Will be implemented.

【0021】[0021]

【発明の効果】以上のように、本発明の半導体部品の実
装方法によれば、半導体部品の電極に形成されたバンプ
を、印刷回路基板に印刷された導電性インクからなる対
応する配線パターンに突き合わせ、印刷回路基板に対し
て半導体部品を電気的に接続する場合に、印刷回路基板
側の配線パターンのうち線幅の広い配線パターンを、印
刷で線間を分離できる限界最小間隔以下の間隔を隔て
て、狭幅の2本の導電性インクの配線パターンを並列に
印刷することによって形成するようにしているので、配
線パターンを2本並列に印刷して形成される配線パター
ンは、時間の経過とともに印刷インクの粘性による広が
りでつながって1本の配線パターンとなり、その膜厚が
薄くなって位置ずれや印刷インクのつぶれを起こすこと
なく半導体部品を印刷回路基板上に精度よく実装でき
る。
As described above, according to the semiconductor component mounting method of the present invention, the bumps formed on the electrodes of the semiconductor component are formed into the corresponding wiring patterns made of the conductive ink printed on the printed circuit board. When abutting and electrically connecting a semiconductor component to the printed circuit board, the wiring pattern with the widest line width of the printed circuit board side wiring pattern should be separated by a distance not exceeding the minimum distance that can be separated by printing. Since the wiring patterns of two conductive inks having a narrow width are printed in parallel at a distance from each other, a wiring pattern formed by printing two wiring patterns in parallel is a time-lapse pattern. At the same time, they are connected by spreading due to the viscosity of the printing ink to form a single wiring pattern, and the film thickness is reduced so that semiconductor components can be printed without misalignment or crushing of the printing ink. It can be accurately mounted on a circuit board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である半導体部品の実装方法
の工程を模式的に示す図である。
FIG. 1 is a diagram schematically showing a step of a semiconductor component mounting method according to an embodiment of the present invention.

【図2】従来の半導体部品の実装方法の工程を模式的に
示す図である。
FIG. 2 is a diagram schematically showing a step of a conventional semiconductor component mounting method.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2a,2b バンプ 3a,3b 配線パターン 3a1,3a2 狭線幅・狭間隔配線パターン 4 印刷回路基板 4a 絶縁基板 DESCRIPTION OF SYMBOLS 1 semiconductor chip 2a, 2b bumps 3a, 3b wiring pattern 3a1, 3a2 narrow line width / narrow interval wiring pattern 4 printed circuit board 4a insulating substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体部品の電極に形成されたバンプ
を、印刷回路基板に印刷された導電性インクからなる対
応する配線パターンに突き合わせ、印刷回路基板に対し
て半導体部品を電気的に接続する半導体部品の実装方法
において、 印刷回路基板側の配線パターンのうち線幅の広い配線パ
ターンを、印刷で線間を分離できる限界最小間隔以下の
間隔を隔てて、狭幅狭間隔の2本の導電性インクの配線
パターンを並列に印刷することによって形成することを
特徴とする半導体部品の実装方法。
1. A semiconductor for bumping bumps formed on electrodes of a semiconductor component to a corresponding wiring pattern made of conductive ink printed on a printed circuit board to electrically connect the semiconductor component to the printed circuit board. In the mounting method of components, a wiring pattern having a wide line width of a wiring pattern on the printed circuit board side is separated by two conductive lines having a narrow width and a narrow space with a space equal to or smaller than a minimum limit space for separating the lines by printing. A method for mounting a semiconductor component, which is formed by printing ink wiring patterns in parallel.
JP3241869A 1991-09-20 1991-09-20 Mounting method of semiconductor component Pending JPH0582951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3241869A JPH0582951A (en) 1991-09-20 1991-09-20 Mounting method of semiconductor component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3241869A JPH0582951A (en) 1991-09-20 1991-09-20 Mounting method of semiconductor component

Publications (1)

Publication Number Publication Date
JPH0582951A true JPH0582951A (en) 1993-04-02

Family

ID=17080738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3241869A Pending JPH0582951A (en) 1991-09-20 1991-09-20 Mounting method of semiconductor component

Country Status (1)

Country Link
JP (1) JPH0582951A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701707B1 (en) * 2006-03-03 2007-03-29 주식회사 하이닉스반도체 Flip Chip Package
CN109390244A (en) * 2017-08-10 2019-02-26 艾马克科技公司 The electronic device for manufacturing the method for electronic device and manufacturing whereby

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701707B1 (en) * 2006-03-03 2007-03-29 주식회사 하이닉스반도체 Flip Chip Package
CN109390244A (en) * 2017-08-10 2019-02-26 艾马克科技公司 The electronic device for manufacturing the method for electronic device and manufacturing whereby

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