JPH0582750A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To keep the total height of a storage electrode having a multi-layer fin structure as low as possible and, further, avoid the degradation of a storage capacity caused by the hang of the fin. CONSTITUTION:A dynamic-type memory cell has a storage electrode 6 having a multilayer fin structure which is composed of a plurality of layers of fins which are provided in multistoried layers. Some of or all of a plurality of layers of the fins 6A, 6B and 6C have different thicknesses or at least the thickness of the uppermost layer fin 6C is larger than the thicknesses of the other fins 6A and 6B or, the higher the layer of the fin, the larger the thickness of the layer of the fin (tC> tB>tA).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the structure of a multilayer fin structure capacitor provided in a dynamic memory cell.

In the stacked capacitor type DRAM cell, the occupied area per 1-bit cell is reduced as the degree of integration is increased, the storage capacity of the capacitor is reduced, and the soft error resistance is significantly deteriorated. Therefore, the storage electrode has a fin structure to secure the surface area of the storage electrode,
As a result, the required storage capacity is secured, and in order to further improve the degree of integration, measures are taken to secure the required storage capacity by increasing the number of fin layers of the storage electrode.

On the other hand, when the number of fin layers of the storage electrode is increased, there is a problem that the storage capacitance is decreased due to the fin sagging, and a countermeasure is desired.

[0004]

2. Description of the Related Art FIG. 5 is a schematic sectional view of a DRAM cell having a conventional multilayer fin structure capacitor.
51 is a p-type silicon (Si) substrate, 52 is a cell region, 53 is a field oxide film, 54 is a gate oxide film, 55 is a gate electrode (word line), 55 'is a word line of another cell, and 56 is a bit line. A first n ⁺ type source / drain (S / D) region connected,
57 is a second n ⁺ type S / D region which serves as a storage node, 58 is a first interlayer insulating film, 59 is a silicon nitride (Si ₃ N ₄ ) film, 60 is a first contact window, and 61 is a multi-layer fin. Structure storage electrode, 62 dielectric film, 63 counter electrode (cell plate), 64 second interlayer insulating film, 65 second contact window, 66 bit line (aluminum wiring), 67 third An interlayer insulating film, 68 is a wiring extending from the cell region to the peripheral portion, TT is a transfer transistor, and TC is a storage capacitor.

In a DRAM cell having a multilayer fin structure capacitor as shown in this figure, as the degree of integration increases, the cell becomes finer and the total number of fins increases, the aspect ratio at the time of etching increases, and fin-shaped structure accumulation occurs. At the same time that the processing of the electrode 60 becomes difficult, the step (h) between the upper surface of the cell region 2 and the upper surface of the peripheral portion becomes large, and the focus when patterning the wiring 68 and the like extending from the cell region 2 to the peripheral portion. This causes a problem that the margin is reduced.

Therefore, when increasing the total number of fins, it is important to reduce the thickness of each fin as much as possible to keep the height of the storage electrode low. In the electrode 61, as shown in the schematic sectional view of FIG.
Thickness of fins of each layer eg thickness of fin 61A of the first layer
Since the thickness (t _A ) and the thickness (t _B ) of the second layer fin 61B are all the same, when increasing the number of layers, in order to keep the total height low, The fins had a uniform thin film thickness. Note that the other reference numerals in FIG. 6 indicate the same objects as those in FIG.

On the other hand, a conventional storage electrode having a multi-layer fin structure is formed by the following method shown with reference to the process sectional view of FIG. See FIG. 7A. That is, a Si ₃ N ₄ film 59 serving as an etching stopper is formed on, for example, an interlayer insulating film 58 formed on a Si substrate 51 (specifically, a second S / D region 57), and then, A first spacer insulating film 69 is formed thereon, and then the first-layer fin 61 is formed thereon.
A first poly-Si layer 70 to be A is formed, then a second spacer insulating film 71 is formed thereon, and then the above-mentioned laminated film is formed.
A first contact window 60 exposing the surface of the Si substrate 51 (second S / D region 57) is formed.

Next, referring to FIG. 7B, the first poly-Si layer 70 to be the second layer fin 61B is formed on the second spacer insulating film 71 including the inner surface of the contact window 60.
Forming a second poly-Si layer 72 having a thickness equal to

Referring to FIG. 7C, the Si ₃ N ₄ film 59 is used as a stopper to remove the second poly-Si film.
Layer 72, second insulating film 71 for spacer, first poly-Si layer 70,
The first spacer insulating film 69 is patterned into the collective storage electrode shape 73.

Next, referring to FIG. 7D, the first spacer insulating film 69 and the second spacer insulating film 71 are removed by a wet etching means, for example, a first-layer fin made of a first poly-Si layer 70. This is a method of forming a storage electrode 61 having a multi-layer fin structure having a second-layer fin 61B composed of 61A and a second poly-Si layer 72.

[0011]

However, according to the above forming process, when the film thickness of each layer fin is uniform as in the conventional case,
When the number of fin layers of the storage electrode 61 is increased and the fins 61A, 61B, etc. are thinned in order to suppress the height thereof, as shown in FIG. Even if the layer fins 61A have no or only a small amount of sagging, the uppermost layer, for example, the second layer fins 61B, drastically sags, and the tip end thereof contacts the fins 61A of the lower layer, which causes a decrease in storage capacity. It was

[0012] Therefore, an object of the present invention is to provide a structure of a multi-layer storage electrode capable of suppressing the entire height as low as possible and preventing the storage capacitance from being lowered due to the hanging of fins.

[0013]

SUMMARY OF THE INVENTION The above problems include a dynamic memory cell having a storage electrode having a multi-layer fin structure having a plurality of fins formed in a hierarchical structure, and a part of the fins of the plurality of layers. A semiconductor memory device according to the present invention in which the thickness of all layers is different, or a dynamic memory cell having a storage electrode of a multilayer fin structure having fins of a plurality of layers formed in a layered manner. A semiconductor memory device according to the present invention in which at least the uppermost fin of the plurality of layers of fins is formed thicker than the fins of the other layers, or a multi-layered fin having a plurality of layers of fins formed in layers. A dynamic memory cell having a storage electrode having a structure, the thickness of the fins of the plurality of layers is
This is solved by the semiconductor memory device according to the present invention in which the fins in the upper layer are formed thicker.

[0014]

[Operation] FIG. 1 is a schematic sectional view for explaining the principle of the present invention.
Is the first structure according to the present invention, and (b) is the second structure.

In the figure, 1 is a semiconductor substrate, 2 is a storage node diffusion layer, 3 is an insulating film, 4 is an etching stopper film for patterning the storage electrode, 5 is a contact window, 6 is a multilayer fin structure storage electrode, and 6A. Is the first layer fin, 6B is the second
Layer fins, 6C are third layer (uppermost layer) fins, and 6S is a spindle.

As described in the conventional problems, in the multi-layer fin structure storage electrode, when the fins of each layer are formed to have a uniform thickness and the thickness is extremely thin,
In the process of forming it, when the spacer insulating film and the fin conductive film are alternately laminated, the stress from the lower part is most received, and when the spacer insulating film is removed by etching, the stress is applied to the lower part. There is a phenomenon that the fins in the uppermost layer, which are considered to receive the largest amount of stress, undergo the most sagging deformation, and the degree of the deformation decreases as the fins in the lower layer, in which the stress is considered to decrease gradually.

Therefore, in the first structure according to the present invention, as shown in FIG. 1A, the uppermost fin (third layer) fin 6C, which is most susceptible to the drooping deformation, is thick enough to withstand the drooping stress. The fins of all layers other than the uppermost layer that are formed and are less likely to be deformed than the uppermost fin 6C, that is, the second fin
The thickness of the layer fins 6B and the first layer fins 6C is set to the uppermost layer fins 6C.
Is thinner than the uppermost layer, and is uniformly formed to a minimum thickness that does not cause sagging deformation in the layers other than the uppermost layer, thereby keeping the overall height (h ₆ ) of the storage electrode 6 as low as possible and The reduction of the storage capacity due to the drooping deformation is prevented.

In the second structure according to the present invention,
The second-layer fin 6B, the first layer, in which the thickness of the uppermost fin 6C, which has the most drooping deformation, is formed to be the thickest so as to withstand the deformation, and the degree of the drooping deformation, which is considered to be caused by the stress, gradually decreases. As it goes to the fins 6A, the film thickness of the fins is sequentially reduced to the extent that deformation does not occur, thereby preventing the decrease of the storage capacitance due to the sagging deformation of the fins while keeping the overall height of the storage electrode as low as possible. ..

[0019]

EXAMPLES The present invention will be described below with reference to examples of manufacturing steps. 2 and 3 are process cross-sectional views according to one embodiment of the first structure according to the present invention, and FIG. 4 is a process cross-sectional view according to one embodiment of the second structure according to the present invention.

Throughout the drawings, the same objects are designated by the same reference numerals. See FIG. 2 (a). A DRAM cell having a first structure according to the present invention, which has a storage capacitor configured by using a storage electrode having, for example, a three-layer fin structure, is formed on a surface of a p-type Si substrate 11 by a conventional method. To form a field oxide film 13 that demarcates and exposes the cell region 12, and a gate electrode 15 is formed on the element region 12 with the gate oxide film 14 interposed therebetween. In the region 12, a transfer transistor (TT) is formed by forming a first n ⁺ type S / D region 16 to which a bit line is connected and a second n ⁺ type S / D region 17 serving as a storage node. After that, using the CVD method, the first interlayer insulating film 18 made of, for example, CVD-SiO ₂ and having a thickness of about 3000 Å, and the thickness of 400 to 600 Å serving as an etching stopper at the time of patterning the storage electrode are formed. Si ₃ N ₄ film 19, thickness 3
The first SiO ₂ spacer film 20 having a thickness of about 00Å, the first n ⁺ -type doped poly-Si layer 21 having a thickness of about 200Å, the second SiO ₂ spacer film 22 having a thickness of about 300Å, and the second SiO ₂ film having a thickness of about 200Å An n ⁺ -type doped poly-Si layer 23 and a third SiO ₂ spacer film 24 having a thickness of about 300Å are sequentially formed.

Next, referring to FIG. 2B, the first interlayer insulating film 18, the Si ₃ N ₄ film 19 and the first
SiO ₂ spacer film 20, first n ⁺ -type doped poly-Si layer 21,
Second SiO ₂ spacer film 22, second n ⁺ -type doped poly Si
The layer 23 and the third SiO ₂ spacer film 24 are penetrated through them by the reactive ion etching (RIE) process to obtain the second n ⁺
A first contact window 25 exposing the surface of the mold S / D region 17 is formed. Here, as the etching gas for the RIE process, for example, (CF ₄ + CHF ₃ ) gas is used for the insulating film, the SiO ₂ film, and the Si ₃ N ₄ film,
(HBr) gas is used for each poly-Si layer.

Next, as shown in FIG. 2C, a third n ⁺ -type doped poly-Si layer 26 having a thickness of about 500 Å is formed on the inner surface of the first contact window 25 and the third SiO ₂ spacer film 24 by the CVD method. Form.

Next, referring to FIG. 2 (d), a photolithography method using a RIE process for etching is performed.
By means of Si₃N _FourThe laminated film on top of the film 19 is₃N_Fourfilm
Using 19 as an etching stopper, for example, about 3000 Å □
The product electrode shape 27 is patterned. For etching gas
Is similar to the case of forming the contact window 25, for example.
Are used.

Next, referring to FIG. 3 (a), by wet etching with a hydrofluoric acid-based solution,
By removing the first, second, and third SiO ₂ spacer films 20, 22, and 24, a thick third n ⁺ -type doped poly-Si having a thickness of about 500Å is formed.
A first layer composed of a first n ⁺ -type doped poly-Si layer 21 having a thickness of about 200 Å and having a third layer (uppermost layer) fin 28F ₃ composed of the layer 26 and a support shaft 28S and supported by the support shaft 28S. Layer fin 28
F ₁ and a second n ⁺ -type doped poly-Si layer 23 of similar thickness
A three-layer fin structure storage electrode 28 having a second-layer fin 28F ₂ is formed.

Here, the thickness of the third layer fin is set to the first,
In the present example, there was no sagging deformation reaching the lower fin of the third layer fin, which frequently occurred at a rate of about 30% in the conventional structure having a thickness of 200Å equal to that of the second fin.

Next, as shown in FIG. 3B, on the surface of the three-layer fin structure storage electrode 28 in the conventional manner,
A Si ₃ N ₄ film with a thickness of about 50Å is formed, and the surface of the film is thermally oxidized to form a dielectric film 29 having a (Si ₃ N ₄ + SiO ₂ ) structure. A fourth n ⁺ -type doped poly-Si layer having a thickness of about 1000 Å is formed, and this poly-Si layer is patterned by RIE to form a cell plate (counter electrode) 30 made of n ⁺ -type doped poly-Si.

Next, as shown in FIG. 3C, a second interlayer insulating film 31 is formed on the substrate by a conventional method, and the second interlayer insulating film 31 and the Si film are formed.
_{The 3} N ₄ film 19 and the first interlayer insulating film 18 are penetrated to form the first n ⁺ film.
A second contact window 32 exposing the mold S / D region 16 is formed, a bit line 33 made of Al or the like is formed on the contact window 32, and the storage capacitor according to the first structure of the present invention is provided. The DRAM cell is completed.

As shown in FIG. 4 (a), when forming a DRAM having a storage capacitor according to the second structure of the present invention, the first transistor is formed on the substrate on which the transfer transistor (TT) is formed, as in the above embodiment.
After forming the interlayer insulating film 18 and the Si ₃ N ₄ film 19 of
First SiO ₂ spacer film 20 with a thickness of about 300Å, thickness 200Å
The first n ⁺ -type doped poly Si layer 21 having a thickness of about 300 Å, the second SiO ₂ spacer film 22 having a thickness of about 300 Å, the second n ⁺ type doped poly Si layer 23 ′ having a thickness of about 350 Å, and the third layer having a thickness of about 300 Å. 3's
The SiO ₂ spacer film 24 is sequentially formed, and then the first contact window 25 is formed by the same method as in the above embodiment.

Next, as shown in FIG. 4B, a third n ⁺ -type doped poly-Si layer 26 having a thickness of about 500 Å is formed on the inner surface of the first contact window 25 and the third SiO ₂ spacer film 24 as in the above embodiment. formed by patterning the upper portion of the laminated film of the Si ₃ N ₄ film 19 to Si ₃ N ₄ accumulating layer 19 degree □ example 3000Å as an etching stopper electrode shape 27, by wet etching using a liquid of hydrofluoric acid, the By removing the first, second and third SiO ₂ spacer films 20, 22, 24, the thickness
A third layer (uppermost layer) made of a third n ⁺ -type doped poly-Si layer 26 having a thickness of about 500 Å has a fin 28F ₃ and a support shaft 28S, and a second support having a thickness of about 350 Å supported by the support shaft 28S. N ⁺
Three-layer fin structure storage electrode having a first layer fin 28F ₁ consisting of the first n ⁺ -type doped poly Si layer 21 of the second layer fin 28F ₂ and a thickness of about 200 Å consisting -type doped poly Si layer 23 '
28 'is formed.

Here, the thickness of the third layer fin is set to the first,
The sagging deformation reaching the lower layer fin of the third layer fin, which frequently occurred in the conventional structure having the thickness of 200 Å equal to that of the second fin, is none as in the above embodiment, and rarely occurs in the conventional structure. There was no sagging deformation of the second layer fins.

After that, the DRAM having the storage capacitor according to the second structure of the present invention is subjected to the same steps as in the above-described embodiment.
The cell is complete.

[0032]

As described in the above embodiments, in the storage electrode of the multi-layer fin structure according to the present invention, the height of the storage electrode as a whole is kept low to reduce the step difference on the DRAM surface, and at the time of formation thereof, The storage capacitors of the storage electrodes of all the cells composing the DRAM can be uniformly maintained at a predetermined value without causing sagging deformation such that the fins in the upper layer contact the fins in the lower layer. Therefore, the present invention is a DRAM
It is extremely effective in improving the yield and reliability of.

[Brief description of drawings]

FIG. 1 is a schematic sectional view for explaining the principle of the present invention.

FIG. 2 is a process sectional view (1) of an embodiment of the first structure according to the present invention.

FIG. 3 is a process sectional view according to an embodiment of the first structure according to the present invention (No. 2)

FIG. 4 is a process sectional view of an example of a second structure according to the present invention.

FIG. 5 is a schematic sectional view of a DRAM cell.

FIG. 6 is a schematic cross-sectional view of a conventional multi-layer fin structure storage electrode.

FIG. 7 is a sectional view of a conventional multi-layer fin structure storage electrode forming process.

FIG. 8 is a schematic cross-sectional view showing the problems of the conventional structure.

[Explanation of reference symbols] 1 semiconductor substrate 2 storage node diffusion layer 3 insulating film 4 etching stopper film 5 contact window 6 multilayer fin structure storage electrode 6A first layer fin 6B second layer fin 6C third layer fin 6S spindle h ₆ Storage electrode height T _A , T _B , T _C Fin thickness

Claims (3)

[Claims] 1. A dynamic memory cell comprising a storage electrode having a multi-layer fin structure having fins of a plurality of layers formed in a hierarchical structure, wherein a part or all layers of the fins of the plurality of layers are provided. A semiconductor memory device having different thicknesses. 2. A dynamic memory cell having a storage electrode having a multi-layer fin structure having a plurality of fins formed in a layered structure, wherein at least the uppermost fin of the plurality of fins is a fin.
A semiconductor memory device characterized in that it is formed thicker than the fins of other layers. 3. A dynamic memory cell comprising a storage electrode having a multi-layer fin structure having a plurality of fins formed in a hierarchical structure, wherein the fins of the plurality of layers are thicker as the fins of the upper layer are formed. A semiconductor memory device characterized by being provided.