JPH0582692A - Manufacture of package for accommodating semiconductor element - Google Patents
Manufacture of package for accommodating semiconductor elementInfo
- Publication number
- JPH0582692A JPH0582692A JP3243354A JP24335491A JPH0582692A JP H0582692 A JPH0582692 A JP H0582692A JP 3243354 A JP3243354 A JP 3243354A JP 24335491 A JP24335491 A JP 24335491A JP H0582692 A JPH0582692 A JP H0582692A
- Authority
- JP
- Japan
- Prior art keywords
- metallized wiring
- wiring layer
- external lead
- semiconductor element
- metallized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容する半
導体素子収納用パッケージの製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor element housing package for housing a semiconductor element.
【０００２】[0002]
【従来の技術】従来、半導体素子、例えば多数の電極を
有するゲートアレイ型半導体素子を収容するプラグイン
型半導体素子収納用パッケージは、アルミナセラミック
ス等の電気絶縁材料から成り、上面略中央部に半導体素
子を収容するための凹部及び該凹部周辺から底面にかけ
て導出された多数のメタライズ配線層を有する矩形状絶
縁基体と、半導体素子を外部電気回路に電気的に接続す
るために前記メタライズ配線層に銀ロウ等のロウ材を介
しロウ付けされた外部リードピンと、蓋体とから構成さ
れており、絶縁基体の凹部内に半導体素子を取着収容す
るとともに該半導体素子の各電極をボンディングワイヤ
を介してメタライズ配線層に接続し、しかる後、絶縁基
体上面に蓋体を封止材を介して取着させ、絶縁基体と蓋
体とから成る容器内部に半導体素子を気密に封止するこ
とによって最終製品としての半導体装置となる。2. Description of the Related Art Conventionally, a plug-in type semiconductor element accommodating package for accommodating a semiconductor element, for example, a gate array type semiconductor element having a large number of electrodes, is made of an electrically insulating material such as alumina ceramics, and a semiconductor is formed in a substantially central portion of an upper surface. A rectangular insulating substrate having a recess for accommodating an element and a large number of metallized wiring layers led out from the periphery of the recess to the bottom surface, and silver on the metallized wiring layer for electrically connecting a semiconductor element to an external electric circuit. It is composed of an external lead pin brazed via a brazing material such as a brazing material, and a lid body. The semiconductor element is mounted and accommodated in the recess of the insulating base, and each electrode of the semiconductor element is bonded via a bonding wire. A container composed of an insulating base and a lid, which is connected to the metallized wiring layer, and then a lid is attached to the upper surface of the insulating base via a sealing material. A semiconductor device as a final product by sealing a semiconductor element hermetically section.
【０００３】尚、この従来のプラグイン型半導体素子収
納用パッケージでは、メタライズ配線層及び外部リード
ピンが酸化腐食するのを防止するために、また外部リー
ドピンと外部電気回路との電気的接続を良好となすため
に通常、前記メタライズ配線層及び外部リードピンの露
出する外表面にはニッケル、金等の良導電性で、且つ耐
蝕性に優れた金属がメッキ方法により層着されている。In this conventional plug-in type semiconductor element accommodating package, in order to prevent the metallized wiring layer and the external lead pins from being oxidized and corroded, the electrical connection between the external lead pins and the external electric circuit is improved. For this purpose, a metal having good conductivity and excellent corrosion resistance, such as nickel and gold, is usually layered on the exposed outer surfaces of the metallized wiring layer and the external lead pins by a plating method.
【０００４】またかかるプラグイン型半導体素子収納用
パッケージは各メタライズ配線層及び外部リードピンが
個々に独立しているためこれら全てのメタライズ配線層
及び外部リードピン表面にメッキ金属層を層着させる際
には、その作業性を考慮して以下の方法が採用され
る。。Further, in such a plug-in type semiconductor element accommodating package, each metallized wiring layer and external lead pin are independent of each other, and therefore, when a plated metal layer is layered on the surfaces of all these metallized wiring layers and external lead pins. The following method is adopted considering its workability. ..
【０００５】即ち、（１）外部リードピンがロウ付けさ
れた各メタライズ配線層の一部を矩形状絶縁基体の各側
辺に導出させる、（２）次に絶縁基体の側辺全周に共通
導体を被着させ、該共通導体によって全てのメタライズ
配線層を電気的に接続する、（３）次にメタライズ配線
層及び外部リードピンの外表面に電解メッキ方法により
メッキ金属層を層着させる、（４）最後に共通導体を研
磨除去し、各外部リードピンがロウ付けされたメタライ
ズ配線層を電気的に独立させ、これによって全てのメタ
ライズ配線層及び外部リートピンの露出する外表面に一
度にメッキ金属層を層着させる。That is, (1) a part of each metallized wiring layer to which external lead pins are brazed is led out to each side of the rectangular insulating substrate, and (2) next, a common conductor is provided around the entire side of the insulating substrate. And electrically connecting all the metallized wiring layers by the common conductor. (3) Next, a plated metal layer is deposited on the outer surfaces of the metallized wiring layer and the external lead pins by an electrolytic plating method. ) Finally, the common conductor is removed by polishing to electrically separate the metallized wiring layers to which each external lead pin is brazed, and the plated metal layer is coated on the exposed outer surfaces of all the metallized wiring layers and the external lead pins at once. Layer.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、この従
来のプラグイン型半導体素子収納用パッケージでは絶縁
基体が矩形形状を成し、各側辺の端部に約90°の角張っ
た角部が存在することから全てのメタライズ配線層及び
外部リードピンの露出する外表面に一度にメッキ金属層
を層着させるために外部リードピンがロウ付けされたメ
タライズ配線層の各々の一部を絶縁基体の各側辺に導出
させるとともに該導出されたメタライズ配線層を絶縁基
体の側辺全周に被着させた共通導体で電気的に接続させ
る際、共通導体が前記絶縁基体の角部で断線を発生して
しまい、その結果、外部リードピンがロウ付けされたメ
タライズ配線層の電気的接続が不可となって全てのメタ
ライズ配線層及び外部リードピンの外表面に一度にメッ
キ金属層を層着させるこができないという欠点を有して
いた。However, in this conventional package for accommodating a plug-in type semiconductor element, the insulating substrate has a rectangular shape, and there is an angled corner of about 90 ° at the end of each side. Therefore, a part of each metallized wiring layer on which external lead pins are brazed in order to layer a plated metal layer on the exposed outer surfaces of all metallized wiring layers and external lead pins at one time is attached to each side of the insulating substrate. When the lead-out is performed and the lead-out metallized wiring layer is electrically connected by the common conductor adhered to the entire circumference of the side of the insulating base, the common conductor causes a disconnection at a corner of the insulating base, As a result, the electrical connection of the metallized wiring layer to which the external lead pins are brazed becomes impossible, and the plated metal layer is deposited on the outer surfaces of all the metallized wiring layers and the external lead pins at once. It had the drawback of not being able to run.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体素子収納
用パッケージの製造方法は、半導体素子が載置固定され
る矩形状絶縁基体に、前記半導体素子の各電極が接続さ
れ、且つ外部リードピンがロウ付けされる複数個のメタ
ライズ配線層を設けるとともに各メタライズ配線層の一
部を矩形状絶縁基体の各側辺に分割して導出させる工程
と前記矩形状絶縁基体に、該矩形状絶縁基体の隣接する
各側辺に導出する予備メタライズ配線層を設ける工程と
前記矩形状絶縁基体の各側辺に共通導体を被着させ、矩
形状絶縁基体の各側辺に導出されたメタライズ配線層及
び予備メタライズ配線層の各々を共通に電気的接続する
工程と、前記共通導体で電気的に接続されたメタライズ
配線層の露出表面及び各メタライズ配線層にロウ付けさ
れた外部リードピン表面に電解メッキ方法によりメッキ
金属層を層着させる工程と、前記メタライズ配線層の露
出表面及び外部リードピン表面にメッキ金属層を層着さ
せた後、矩形状絶縁基体の各側辺を研磨し、共通導体を
除去して各メタライズ配線層を電気的に独立させる工程
とを含むことを特徴とするものである。According to the method of manufacturing a package for accommodating a semiconductor element of the present invention, each electrode of the semiconductor element is connected to a rectangular insulating substrate on which the semiconductor element is mounted and fixed, and external lead pins are provided. A step of providing a plurality of brazed metallized wiring layers and dividing a part of each metallized wiring layer into each side of the rectangular insulating base and leading it out; A step of providing a preliminary metallized wiring layer extending to each adjacent side, and a common conductor is applied to each side of the rectangular insulating substrate, and a metallized wiring layer and a preliminary led to each side of the rectangular insulating substrate. A step of electrically connecting each of the metallized wiring layers in common, an exposed surface of the metallized wiring layers electrically connected by the common conductor, and an external lead pin brazed to each metallized wiring layer. A step of depositing a plated metal layer on the surface by an electrolytic plating method, and after depositing a plated metal layer on the exposed surface of the metallized wiring layer and the surface of the external lead pin, polishing each side of the rectangular insulating substrate, A step of removing the common conductor to electrically separate the metallized wiring layers from each other.
【０００８】[0008]
【実施例】次に本発明を添付図面に基づき説明する。The present invention will now be described with reference to the accompanying drawings.
【０００９】図1 は本発明にかかる製造方法によって製
作されたプラグイン型半導体素子収納用パッケージの一
実施例を示す断面図であり、1 は矩形状の絶縁基体、2
は蓋体である。この絶縁基体1 と蓋体2 とで半導体素子
3 を収容するための容器が構成される。FIG. 1 is a cross-sectional view showing an embodiment of a package for accommodating a plug-in type semiconductor device manufactured by the manufacturing method according to the present invention.
Is a lid. With this insulating base 1 and lid 2, a semiconductor element
A container for housing 3 is constructed.
【００１０】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その上面中
央部に半導体素子3 を収容するための空所を形成する凹
部1aが設けてあり、該凹部1a底面には半導体素子3 がガ
ラス、樹脂、ロウ材等の接着材を介して取着固定され
る。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. A concave portion 1a is formed to form a space for accommodating the semiconductor element 3, and the semiconductor element 3 is attached and fixed to the bottom surface of the concave portion 1a via an adhesive material such as glass, resin, or brazing material.
【００１１】また前記絶縁基体1 の凹部1a周辺から底面
にかけて複数個のメタライズ配線層4 が導出されてお
り、該各メタライズ配線層4 の凹部1a周辺部には半導体
素子3の各電極がボンディングワイヤ5 を介して電気的
に接続され、また絶縁基体1 の底面に導出された部位に
は外部電気回路と接続される外部リードピン6 が銀ロウ
等のロウ材を介して取着される。Further, a plurality of metallized wiring layers 4 are led out from the periphery of the recess 1a of the insulating base 1 to the bottom surface, and each electrode of the semiconductor element 3 is bonded with a bonding wire around the recess 1a of each metallized wiring layer 4. External lead pins 6 which are electrically connected via 5 and are connected to an external electric circuit are attached to a portion led out to the bottom surface of the insulating substrate 1 via a brazing material such as silver brazing.
【００１２】前記メタライズ配線層4 にロウ材を介して
取着される外部リードヒン6 は内部に収容する半導体素
子3 を外部電気回路に電気的に接続する作用を成し、該
外部リードピン6 を外部電気回路に設けたソケット等に
挿入し接続することによって内部に収容される半導体素
子3 はメタライズ配線層4 及び外部リードピン6 を介し
て外部電気回路に接続されることとなる。The external lead pins 6 attached to the metallized wiring layer 4 via a brazing material serve to electrically connect the semiconductor element 3 housed therein to an external electric circuit, and connect the external lead pins 6 to the outside. The semiconductor element 3 accommodated inside by being inserted into a socket or the like provided in the electric circuit and connected thereto is connected to the external electric circuit via the metallized wiring layer 4 and the external lead pin 6.
【００１３】尚、前記外部リードピン6 はコバール金属
(Fe-Ni-Co 合金) や42アロイ(Fe-Ni合金）等の金属から
成り、コバール金属等のインゴット( 塊) を圧延加工法
や打ち抜き加工法等、従来周知の金属加工法を採用する
ことによって所定のピン状に形成される。The external lead pins 6 are made of Kovar metal.
Made of metal such as (Fe-Ni-Co alloy) or 42 alloy (Fe-Ni alloy). Ingot (lump) of Kovar metal etc. adopts well-known metal working methods such as rolling and punching. As a result, it is formed into a predetermined pin shape.
【００１４】また前記メタライズ配線層4 及び外部リー
ドピン6 はその露出する外表面にニッケル、金等の耐蝕
性に優れ、且つ良導電性の金属からメッキ金属層７が電
解メッキ方法により1.0 乃至20.0μm の厚みに層着され
ており、該ニッケル、金等のメッキ金属層７によってメ
タライズ配線層4 及び外部リードピン6 の酸化腐食が有
効に防止されるとともにメタライズ配線層4 とボンディ
ングワイヤ5 の電気的接続及び外部リードピン6 と外部
電気回路との電気的接続が良好なものとなっている。The metallized wiring layer 4 and the external lead pins 6 have a corrosion-resistant metal such as nickel or gold on the exposed outer surface of the metalized wiring layer 4 and a plated metal layer 7 of 1.0 to 20.0 .mu.m formed by electrolytic plating. The metallized wiring layer 4 and the external lead pins 6 are effectively prevented from being oxidized and corroded by the plated metal layer 7 such as nickel or gold, and the metallized wiring layer 4 and the bonding wire 5 are electrically connected. Also, the electrical connection between the external lead pin 6 and the external electric circuit is good.
【００１５】かくして上述のプラグイン型半導体素子収
納用パッケージによれば、絶縁基体1 の凹部1a底面に半
導体素子3 を接着材を介して取着固定し、該半導体素子
3 の各電極をボンディングワイヤ5 によりメタライズ配
線層4 に接続させるとともに絶縁基体1 と蓋体2 とを樹
脂等の封止材で接合させ、絶縁基体1 と蓋体2 とから成
る容器内部に半導体素子3 を気密に封止することによっ
て最終製品としての半導体装置が完成する。Thus, according to the above-mentioned package for accommodating the plug-in type semiconductor element, the semiconductor element 3 is attached and fixed to the bottom surface of the recess 1a of the insulating substrate 1 with an adhesive material.
Each electrode of 3 is connected to the metallized wiring layer 4 by the bonding wire 5 and the insulating base 1 and the lid 2 are joined by a sealing material such as resin, and the semiconductor is placed inside the container made of the insulating base 1 and the lid 2. The semiconductor device as a final product is completed by hermetically sealing the element 3.
【００１６】次に本発明のプラグイン型半導体素子収納
用パッケージの製造方法について図2 乃至図6 に基づき
説明する。Next, a method of manufacturing the package for accommodating the plug-in type semiconductor element of the present invention will be described with reference to FIGS.
【００１７】まず図2 に示す如く、3 枚の矩形状セラミ
ックグリーンシート10a 、10b 、10c を準備するととも
に各セラミックグリーンシート10a 、10b 、10c に半導
体素子を収容する空所を形成するための孔11a 及びメタ
ライズ配線層4を引き回すための貫通孔11b を従来周知
の孔開け加工法によりあける。First, as shown in FIG. 2, three rectangular ceramic green sheets 10a, 10b and 10c are prepared and holes are formed in each of the ceramic green sheets 10a, 10b and 10c to form a cavity for accommodating a semiconductor element. A through hole 11b for leading around 11a and the metallized wiring layer 4 is formed by a conventionally known drilling method.
【００１８】前記セラミックグリーンシート10a 、10b
、10c は絶縁基体1 が酸化アルミニウム質焼結体から
なる場合、例えば酸化アルミニウム(Al 2 O 3 ) 、シリ
カ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原
料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれをドクターブード法やカレンダーロー
ル法等を採用し、シート状に成形することによってセラ
ミックグリーンシート(セラミック生シート) を得、し
かる後、前記セラミックグリーンシートに適当な打ち抜
き加工法を施し矩形状となすことによって形成される。The ceramic green sheets 10a and 10b
, 10c, when the insulating substrate 1 is made of a sintered aluminum oxide material, for example, aluminum oxide (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (MgO), etc. A solvent and a solvent are added and mixed to form a slurry, and a doctor green method or calender roll method is adopted to form this into a sheet shape to obtain a ceramic green sheet (ceramic green sheet). It is formed by subjecting the green sheet to an appropriate punching process to form a rectangular shape.
【００１９】次に図3 に示す如く、セラミックグリーン
シート10a の貫通孔11b 内と、セラミックグリーンシー
ト10b の上面及び貫通孔11b 内にメタライズ配線層4 と
なる複数個の配線パターン12を被着する。Next, as shown in FIG. 3, a plurality of wiring patterns 12 to be the metallized wiring layer 4 are deposited in the through holes 11b of the ceramic green sheet 10a and on the upper surface and the through holes 11b of the ceramic green sheet 10b. ..
【００２０】前記メタライズ配線層4 となる配線パター
ン12は例えば、タングステン(W) 、モリブデン(Mo)、マ
ンガン(Mn)等の高融点金属粉末から成り、該高融点金属
粉末に適当な有機溶剤、溶媒を添加混合することによっ
て得た金属ペーストを従来周知のスクリーン印刷法を採
用してセラミックグリーンシート10a 、10b に印刷塗布
することによってセラミックグリーンシート10a 、10b
に被着される。The wiring pattern 12 to be the metallized wiring layer 4 is made of, for example, a refractory metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn) or the like, and an organic solvent suitable for the refractory metal powder, A ceramic green sheet 10a, 10b is obtained by applying a metal paste obtained by adding and mixing a solvent onto the ceramic green sheet 10a, 10b by a conventionally known screen printing method.
Be attached to.
【００２１】また前記セラミックグリーンシート10b に
被着させた各配線パターン12はその各々の一部がセラミ
ックグリーンシート10bの側辺部に導出されており、各
配線パターン12の各々の一部をセラミックグリーンシー
ト10b の側辺部に導出させておくことによって各配線パ
ターン12は後述する共通導体により電気的に接続される
こととなる。Part of each wiring pattern 12 adhered to the ceramic green sheet 10b is led out to the side part of the ceramic green sheet 10b, and each part of each wiring pattern 12 is made of ceramic. The wiring patterns 12 are electrically connected to each other by a common conductor, which will be described later, by being led out to the side portion of the green sheet 10b.
【００２２】更に前記セラミックグリーンシート10b の
上面各角部には隣接する側辺に導出される予備配線パタ
ーン12a が被着されており、該予備配線パターン12a は
後述する予備メタライズ配線層となり、各セラミックグ
リーンシート10a 、10b 、10c を積層しセラミックグリ
ーンシート積層体となした後、セラミックグリーンシー
ト積層体の各側辺に共通導体を被着させる際に隣接する
側辺の共通導体間に電気的な断線が生じるのを有効に防
止する作用を為す。Further, a spare wiring pattern 12a led to an adjacent side is adhered to each corner of the upper surface of the ceramic green sheet 10b, and the spare wiring pattern 12a becomes a spare metallized wiring layer which will be described later. After the ceramic green sheets 10a, 10b, and 10c are laminated to form a ceramic green sheet laminate, when a common conductor is applied to each side of the ceramic green sheet laminate, an electrical connection is made between the common conductors on the adjacent sides. It effectively prevents the occurrence of severe disconnection.
【００２３】次に前記各セラミックグリーンシート10a
、10b 、10c は図4 に示す如く、その各々を上下に積
層してセラミックグリーンシート積層体10となすととも
に該セラミックグリーンシート積層体10の側辺全周に共
通導体13を被着させる。Next, each ceramic green sheet 10a
4, 10b and 10c are laminated on each other to form a ceramic green sheet laminated body 10 and a common conductor 13 is attached to the entire circumference of the side edges of the ceramic green sheet laminated body 10.
【００２４】前記共通導体13はセラミックグリーンシー
ト10a 、10b に被着させた複数個の配線パターン12を共
通に電気的接続する作用を為し、タングステン、モリブ
デン、マンガン等の融点金属粉末から成り、該高融点金
属粉末に適当な有機溶剤、溶媒を添加混合して得た金属
ペーストをセラミックグリーンシート積層体10の各側辺
に従来周知のスクリーン印刷法により印刷塗布すること
によってセラミックグリーンシート積層体10の側辺全周
に被着される。The common conductor 13 serves to electrically connect a plurality of wiring patterns 12 adhered to the ceramic green sheets 10a and 10b in common, and is made of a melting point metal powder such as tungsten, molybdenum and manganese. A ceramic green sheet laminate by printing and applying a metal paste obtained by adding and mixing a suitable organic solvent and a solvent to the high melting point metal powder to each side of the ceramic green sheet laminate 10 by a conventionally known screen printing method. It is attached to the entire circumference of 10 sides.
【００２５】尚、この場合、セラミックグリーンシート
積層体10の側辺全周に被着される共通導体13はセラミッ
クグリーンシート積層体10の側辺端部が角張っているこ
とに起因して断線を生じる危険性が有るがセラミックグ
リーンシート積層体10には予備配線パターン12a が設け
られているため各側辺に被着される共通導体13の電気的
導通は維持される。In this case, the common conductor 13 applied to the entire circumference of the side edges of the ceramic green sheet laminate 10 is broken due to the angular edges of the side edges of the ceramic green sheet laminate 10. Although there is a risk of occurrence, since the ceramic green sheet laminate 10 is provided with the preliminary wiring pattern 12a, the electrical continuity of the common conductor 13 attached to each side is maintained.
【００２６】また前記セラミックグリーンシート積層体
10の各側辺に被着される共通導体13はセラミックグリー
ンシート積層体10に設けた予備配線パターン12a によっ
てその電気的導通が維持されるためセラミックグリーン
シート積層体10の側辺全周にスクリーン印刷法により共
通導体13を被着させる必要はなく、セラミックグリーン
シート積層体10の側辺端部を除いた各側辺に被着させて
もよい。この場合、セラミックグリーンシート積層体10
の側辺全周にスクリーン印刷法により共通導体13を被着
させる際、セラミックグリーンシート積層体10の各側辺
端部に共通導体13が多量に被着され、その一部が積層体
10の底面に流出して各配線パターン12に不要な短絡を発
生させたり、外観不良等を発生させたりするのが有効に
防止されるため好適である。The ceramic green sheet laminate
The common conductor 13 attached to each side of the ceramic green sheet laminate 10 is electrically connected by the preliminary wiring pattern 12a provided in the ceramic green sheet laminate 10, so that the screen is provided around the entire periphery of the ceramic green sheet laminate 10. It is not necessary to apply the common conductor 13 by a printing method, and the common conductor 13 may be applied to each side of the ceramic green sheet laminate 10 excluding the side end. In this case, the ceramic green sheet laminate 10
When the common conductor 13 is applied to the entire circumference of the side edges of the ceramic green sheet laminate 10 by the screen printing method, a large amount of the common conductor 13 is attached to the end portions of each side edge of the ceramic green sheet laminate 10, and a part of the laminate is formed.
It is preferable because it is effectively prevented from flowing out to the bottom surface of the wiring pattern 10 and causing an unnecessary short circuit in each wiring pattern 12 or a defective appearance.
【００２７】次に前記セラミックグリーンシート積層体
10は還元雰囲気中、約1600℃の温度で焼成され、各セラ
ミックグリーンシート10a 、10b 、10c を焼結一体化す
ることにより絶縁基体1 となす。この時、セラミックグ
リーンシート10a 、10b 等に被着された配線パターン12
はメタライズ配線層4 として、また予備配線パターン12
a は予備メタライズ配線層として絶縁基体1 内に埋設さ
れる。Next, the ceramic green sheet laminate
10 is fired in a reducing atmosphere at a temperature of about 1600 ° C., and the ceramic green sheets 10a, 10b, 10c are sintered and integrated to form the insulating substrate 1. At this time, the wiring pattern 12 attached to the ceramic green sheets 10a, 10b, etc.
As the metallized wiring layer 4 and the spare wiring pattern 12
a is embedded in the insulating substrate 1 as a preliminary metallized wiring layer.
【００２８】次に前記絶縁基体1 は図5 に示す如く、そ
の底面に導出されたメタライズ配線層4 に外部リードピ
ン6 を銀ロウ等のロウ材を介して取着されるとともに該
メタライズ4 及び外部リードピン6 の露出する外表面に
メッキ金属層を層着させる。Next, as shown in FIG. 5, the insulating substrate 1 has external lead pins 6 attached to the metallized wiring layer 4 led out to the bottom surface thereof via a brazing material such as silver brazing, and the metallized layer 4 and the external A plated metal layer is deposited on the exposed outer surface of the lead pin 6.
【００２９】前記メタライズ金属層4 及び外部リードピ
ン6 の外表面へのメッキ金属層の層着は電解メッキ方法
によって行われ、具体的には外部リードピン6 がロウ付
けされた絶縁基体1 をメッキ浴中に浸漬するとともにメ
タライズ配線層4 及び外部リードピン6 に一定の電力を
印加することによって行われる。尚、この場合、外部リ
ードピン6 がロウ付けされた各メタライズ配線層4 はそ
の各々が共通導体13及び予備メタライズ配線層によって
電気的に共通に接続されているため、共通導体に電力を
印加すれば全てのメタライズ配線層4 及び外部リードピ
ン6 にメッキのための電力を印加することが可能とな
り、これによって全てのメタライズ配線層4 及び外部リ
ードピン6 の露出する外表面に一度にメッキ金属層を確
実に層着させることが可能となる。The plating metal layer is deposited on the outer surfaces of the metallized metal layer 4 and the external lead pins 6 by an electrolytic plating method. Specifically, the insulating substrate 1 to which the external lead pins 6 are brazed is placed in a plating bath. And the metallized wiring layer 4 and the external lead pins 6 by applying a constant electric power. In this case, since each of the metallized wiring layers 4 to which the external lead pins 6 are brazed is electrically connected in common by the common conductor 13 and the preliminary metallized wiring layer, if power is applied to the common conductor, Power for plating can be applied to all the metallized wiring layers 4 and the external lead pins 6, which ensures that the exposed metal surfaces of all the metallized wiring layers 4 and the external lead pins 6 are plated with a metal layer at a time. It can be layered.
【００３０】そして次に前記絶縁基体1 はその側辺がグ
ラインダー等の機械的研磨装置により研磨され、絶縁基
体1 より共通導体13を除去し、各メタライズ配線層4 を
電気的に独立させることによって図6 に示す如く、製品
としてのプラグイン型半導体素子収納用パッケージが完
成する。Then, the side of the insulating base 1 is polished by a mechanical polishing device such as a grinder, the common conductor 13 is removed from the insulating base 1, and the metallized wiring layers 4 are electrically isolated. As shown in Fig. 6, the plug-in type semiconductor device housing package as a product is completed.
【００３１】尚、本発明は上述した実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能である。It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.
【００３２】[0032]
【発明の効果】本発明の半導体素子収納用パッケージの
製造方法によれば、外部リードピンがロウ付けされてい
るメタライズ配線層の一部を絶縁基体の各側辺に導出さ
せてその各々を絶縁基体の各側辺に被着させた共通導体
により電気的に接続するとともに絶縁基体の隣接する側
辺の共通導体を予備メタライズ配線層により電気的に接
続させたことから外部リードピンがロウ付けされている
各メタライズ配線層はその全てが確実に共通に電気的接
続され、その結果、メタライズ配線層及び外部リードピ
ンの露出する外表面にメッキ金属層を電解メッキ方法に
より層着させる際、共通導体にメッキのための電力を印
加すれば全てのメタライズ配線層及び外部リードピンに
共通にメッキのための電力が印加されることとなり、全
てのメタライズ配線層及び外部リードピンの露出する外
表面に一度にメッキ金属層を確実に層着させることが可
能となる。According to the method of manufacturing a package for accommodating semiconductor elements of the present invention, a part of the metallized wiring layer to which the external lead pins are brazed is led out to each side of the insulating substrate and each of them is insulated substrate. The external lead pins are brazed because they are electrically connected by the common conductors attached to the respective side edges and the common conductors on the adjacent side edges of the insulating substrate are electrically connected by the preliminary metallized wiring layer. All of the metallized wiring layers are surely electrically connected in common, and as a result, when the plated metal layer is deposited on the exposed outer surfaces of the metallized wiring layer and the external lead pins by the electrolytic plating method, the common conductor is plated. Is applied to all metallized wiring layers and external lead pins, the power for plating is commonly applied to all metallized wiring layers and external lead pins. It is possible to particle course a plated metal layer reliably at a time on the outer surface exposed layer and the external lead pins.
【図１】本発明の半導体素子収納用パッケージの製造方
法によって製作されたプラグイン型半導体素子収納用パ
ッケージの一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a plug-in type semiconductor element housing package manufactured by a method for manufacturing a semiconductor element housing package according to the present invention.
【図２】本発明の半導体素子収納用パッケージの製造方
法を説明するための分解斜視図である。FIG. 2 is an exploded perspective view for explaining a method for manufacturing a semiconductor element storage package of the present invention.
【図３】本発明の半導体素子収納用パッケージの製造方
法を説明するための分解斜視図である。FIG. 3 is an exploded perspective view for explaining the method for manufacturing the semiconductor element housing package of the present invention.
【図４】本発明の半導体素子収納用パッケージの製造方
法を説明するための斜視図である。FIG. 4 is a perspective view for explaining the method for manufacturing the semiconductor element housing package of the present invention.
【図５】本発明の半導体素子収納用パッケージの製造方
法を説明するための斜視図である。FIG. 5 is a perspective view for explaining a method for manufacturing a semiconductor element storage package of the present invention.
【図６】本発明の半導体素子収納用パッケージの製造方
法を説明するための斜視図である。FIG. 6 is a perspective view for explaining the method of manufacturing the semiconductor element housing package of the present invention.
１・・・・・・・絶縁基体 ４・・・・・・・メタライズ配線層 ６・・・・・・・外部リードピン ７・・・・・・・メッキ金属層 10・・・・・・・セラミックグリーンシート積層体 10a,10b,10c ・・セラミックグリーンシート 12・・・・・・・メタライズ配線層となる配線パターン 12a ・・・・・・予備メタライズ配線層となる予備配線
パターン 13・・・・・・・共通導体1 ... Insulating substrate 4 ... Metalized wiring layer 6 ... External lead pin 7 ... Plating metal layer 10 ... Ceramic green sheet laminate 10a, 10b, 10c ··· Ceramic green sheet 12 ··· Wiring pattern 12a to be a metallized wiring layer ··· Preliminary wiring pattern 13 to be a preliminary metallized wiring layer .... Common conductor
Claims (1)
体に、前記半導体素子の各電極が接続され、且つ外部リ
ードピンがロウ付けされる複数個のメタライズ配線層を
設けるとともに各メタライズ配線層の一部を矩形状絶縁
基体の各側辺に分割して導出させる工程と前記矩形状絶
縁基体に、該矩形状絶縁基体の隣接する各側辺に導出す
る予備メタライズ配線層を設ける工程と前記矩形状絶縁
基体の各側辺に共通導体を被着させ、矩形状絶縁基体の
各側辺に導出されたメタライズ配線層及び予備メタライ
ズ配線層の各々を共通に電気的接続する工程と、 前記共通導体で電気的に接続されたメタライズ配線層の
露出表面及び各メタライズ配線層にロウ付けされた外部
リードピン表面に電解メッキ方法によりメッキ金属層を
層着させる工程と、 前記メタライズ配線層の露出表面及び外部リードピン表
面にメッキ金属層を層着させた後、矩形状絶縁基体の各
側辺を研磨し、共通導体を除去して各メタライズ配線層
を電気的に独立させる工程とを含む半導体素子収納用パ
ッケージの製造方法。1. A plurality of metallized wiring layers to which respective electrodes of the semiconductor element are connected and external lead pins are brazed are provided on a rectangular insulating substrate on which a semiconductor element is mounted and fixed, and each metallized wiring layer. A part of each of the rectangular insulating bases is divided into respective side edges and led out; and the rectangular insulating base is provided with preliminary metallized wiring layers leading to adjacent side edges of the rectangular insulating base; A step of depositing a common conductor on each side of the rectangular insulating substrate and electrically connecting the metallized wiring layer and the preliminary metallized wiring layer led out to each side of the rectangular insulating substrate in common. A step of depositing a plated metal layer on the exposed surface of the metallized wiring layer electrically connected by a conductor and the surface of the external lead pin brazed to each metallized wiring layer by an electrolytic plating method; After depositing a plated metal layer on the exposed surface of the metallized wiring layer and the surface of the external lead pin, polishing each side of the rectangular insulating substrate and removing the common conductor to electrically separate each metallized wiring layer A method of manufacturing a package for housing a semiconductor device, including:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243354A JP2685158B2 (en) | 1991-09-24 | 1991-09-24 | Manufacturing method of semiconductor device storage package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3243354A JP2685158B2 (en) | 1991-09-24 | 1991-09-24 | Manufacturing method of semiconductor device storage package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0582692A true JPH0582692A (en) | 1993-04-02 |
| JP2685158B2 JP2685158B2 (en) | 1997-12-03 |
Family
ID=17102591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3243354A Expired - Fee Related JP2685158B2 (en) | 1991-09-24 | 1991-09-24 | Manufacturing method of semiconductor device storage package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2685158B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100218319B1 (en) * | 1996-10-04 | 1999-09-01 | 구본준 | Semiconductor package and socket |
-
1991
- 1991-09-24 JP JP3243354A patent/JP2685158B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100218319B1 (en) * | 1996-10-04 | 1999-09-01 | 구본준 | Semiconductor package and socket |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2685158B2 (en) | 1997-12-03 |
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