JP2002170908A - Semiconductor device accommodation substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device accommodation substrate that can inhibit damage due to thermal stress caused by difference in the coefficient of thermal expansion between a lid body and an insulating board. SOLUTION: This semiconductor device accommodation substrate has the insulating board 2, a semiconductor device 7 accommodated into a cavity 5 on the insulating board 2, a lid body 11 joined to the insulating board 2 for sealing the semiconductor device 7, and a plurality of terminal electrodes 13 that are formed on a surface at a side opposite to the mounting surface of the semiconductor device 7 on the insulating board 2 and whose electric continuity is cancelled by an insulating groove 15. In this case, the insulating groove 15 is formed at the outside as compared with a junction section 21 between the lid body 11 and insulating board 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing substrate, and more particularly to a semiconductor device housing substrate in which a plurality of terminal electrodes are electrically disconnected by an insulating groove.

[0002]

2. Description of the Related Art Conventionally, an insulating substrate used for a semiconductor element housing substrate such as a semiconductor element housing package or a hybrid integrated circuit device is generally made of an electrically insulating ceramic sintered body such as an alumina sintered body. And disposing a plurality of wiring conductor layers made of a refractory metal such as tungsten (W), molybdenum (Mo), and manganese (Mn) on the surface, and providing each wiring conductor layer in an insulating substrate. It has a structure connected by through-hole conductors made of a similar high-melting point metal.

Further, a terminal electrode for connection to an external circuit is formed on a lower surface of the insulating substrate, and a surface thereof has a plating layer formed by an electrolytic plating method or the like.

When the insulating substrate is applied to, for example, a package for accommodating a semiconductor element, as shown in FIG. 5, a semiconductor element 55 is formed on a bottom surface of a cavity 53 of the insulating substrate 51 by using glass, resin, brazing material or the like. Each electrode of the semiconductor element 55 is electrically connected to a wiring conductor layer located around the cavity 53 through a bonding wire 57, and a cover 59 made of metal or ceramic is attached to the cavity by an adhesive. The semiconductor element 55 is bonded to the insulating substrate 51 via a sealing material similar to the adhesive so as to cover the semiconductor element 55 in the cavity 53 of the insulating substrate 51.
Was kept airtight.

On the lower surface of the insulating substrate 51, there are provided a plurality of terminal electrodes 61 comprising a base electrode layer formed by metallization or sputtering and a plating layer formed on the surface of the base electrode layer by electrolytic plating. These terminal electrodes 61 are electrically disconnected from each other by insulating grooves 63 formed in the insulating substrate 51. These terminal electrodes 61 are electrically connected to the wiring conductor layer formed around the cavity 53 by via-hole conductors 65.

An external lead terminal (not shown) made of an iron-nickel (Fe-Ni) alloy or the like is electrically connected to these terminal electrodes 61 via a brazing material such as a silver brazing. By connecting these external lead terminals to an external circuit, each electrode of the semiconductor element is electrically connected to the external circuit via a bonding wire, a wiring conductor layer, a via-hole conductor, and the external lead terminal.

Conventionally, a plurality of terminal electrodes are formed on the lower surface of an insulating substrate by forming a continuous base electrode layer by metallization or sputtering in order to more efficiently perform an electrolytic plating method described later. Then, a plating layer is formed by an electrolytic plating method. In this state, the plurality of terminal electrodes are electrically short-circuited.

[0008] Thereafter, a portion inside the junction between the lid and the insulating substrate, which is a conduction portion where a plurality of terminal electrodes are conducted, is removed by polishing using a luter, and each terminal electrode is electrically connected. Was insulated.

[0009]

However, in the above-mentioned conventional method, since the conductive portions of the plurality of terminal electrodes are removed by polishing using a router, an insulating groove is formed on the lower surface of the insulating substrate by the polishing. This insulating groove is formed in a semiconductor element housing substrate mounting step,
In a subsequent bonding step of the lid to the semiconductor element housing substrate, or for mounting the semiconductor element, and conducting a temperature cycle test to confirm the reliability of the semiconductor element housing substrate after the bonding of the lid is completed, etc. In the reliability test of
There has been a problem that the thermal stress of the insulating substrate caused mainly by the difference in thermal expansion coefficient between the lid and the insulating substrate causes the insulating substrate to break down from the insulating groove.

[0010] More specifically, as shown in FIG. 5, conventionally, a portion inside a joint portion 67 between the lid 59 and the insulating substrate 51 is removed by polishing using a luter, and each terminal electrode 6 is removed.
1 is electrically insulated, so that the lid 59 and the insulating substrate 5
An insulating groove 63 is formed on the inner side of the junction 67 with the first groove 1.

By the way, the present inventors have found that the thermal stress generated due to the difference in the coefficient of thermal expansion between the lid 59 and the insulating substrate 51 is large inside the joint 67 between the lid 59 and the insulating substrate 51, It has been found that if it is outside the portion 67, it becomes a free end, so that almost no thermal stress is generated. Therefore, conventionally, the insulating groove 63 that electrically insulates each terminal electrode 61 is
Since it was present inside the joint 67, thermal stress was large, and stress was concentrated on the insulating groove 63 structurally.
There was a problem that damages such as cracks occur from No. 3.

That is, as shown in FIG. 5 and FIG.
3 is formed inside the joint 67 of the lid 59 to the insulating substrate 51, so that when a thermal load is applied to the semiconductor element housing substrate, a difference in thermal expansion coefficient between the insulating substrate 51 and the lid 59 is caused. Thermal deformation mainly occurs, and the thermal deformation causes a bending stress in the insulating substrate 51.

When the bending stress is deformed as shown in FIG. 6, the area of the joint 67 between the insulating substrate 51 and the lid 59 is large, and if the insulating groove 63 exists in this area, the insulating groove 63 There was a problem that it became a starting point of destruction and was damaged.

Accordingly, it is an object of the present invention to provide a semiconductor element housing substrate capable of suppressing damage due to thermal stress caused by a difference in thermal expansion coefficient between a lid and an insulating substrate.

[0015]

According to the present invention, there is provided a semiconductor element housing substrate comprising: an insulating substrate; a semiconductor element housed in a cavity of the insulating substrate; and a lid joined to the insulating substrate to seal the semiconductor element. A plurality of terminal electrodes formed on a surface of the insulating substrate opposite to a surface on which the semiconductor element is mounted, and having a plurality of terminal electrodes released from electrical continuity by an insulating groove; Groove
It is formed outside the joint between the lid and the insulating substrate.

The thermal stress generated due to the difference in thermal expansion coefficient between the lid and the insulating substrate is large inside the joint between the lid and the insulating substrate, and hardly occurs outside the joint between the lid and the insulating substrate. However, in the semiconductor element housing substrate of the present invention, the insulating groove
Since it is formed outside the joint between the lid and the insulating substrate, thermal stress acting on the insulating groove is small, and damage from the insulating groove can be suppressed.

In the present invention, it is desirable that the insulating groove is formed in a zigzag shape. By forming the insulating grooves in a zigzag shape in this manner, the thermal stress acting on the insulating grooves can be dispersed and further reduced, and the reliability can be further improved.

Further, in the present invention, it is desirable that the insulating groove is formed at least 500 μm inside the end face of the insulating substrate. Thereby, the via-hole conductor formed in the insulating substrate can be reliably connected to the terminal electrode.

In the present invention, the lid is made of metal,
This is effective when the insulating substrate is made of ceramics.

That is, in order to effectively dissipate the heat generated from the semiconductor element, the lid body to be joined to the semiconductor element housing substrate is preferably made of a metal material such as copper, aluminum, or Kovar. When the insulating substrate is made of a ceramic material, the difference in thermal expansion coefficient between the lid and the insulating substrate becomes large.
Breakage from the insulating groove of the insulating substrate can be more effectively suppressed.

[0021]

1 and 2 are schematic views of a semiconductor device housing substrate according to the present invention.
FIG. 1 is a plan view, and FIG. 2 is a cross-sectional view taken along line AA of FIG.

In FIGS. 1 and 2, reference numeral 2 indicates an insulating substrate having a square main surface. The insulating substrate 2 is made of alumina, aluminum nitride, silicon nitride, sialon (Si, A
It is preferable to use a ceramic mainly containing mullite or silicon carbide.

The insulating substrate 2 is formed with a cavity 5 having an opening having a step 3 and a square shape, and a semiconductor element 7 is accommodated in the cavity 5. The wires 9 are connected to wiring conductor layers (not shown) formed on the three surfaces.

The semiconductor element 7 includes a lid 1 joined to the surface of the insulating substrate 2 so as to surround the outer periphery of the cavity 5 of the insulating substrate 2.
1 is hermetically sealed.

A large number of terminal electrodes 13 for electrically connecting to an external circuit are formed in the center of each side of the outer peripheral portion of the lower surface of the insulating substrate 2.
The electrical conduction is prevented by the insulating groove 15. That is, many terminal electrodes 13 are electrically conductive at the time of manufacturing the terminal electrodes, and are separated into the terminal electrodes 13 and the electrically conductive portions 17 by the insulating grooves 15 formed by polishing with a router. ing. The insulating groove 15
Is a concept that includes such things as slightly dented abrasions.

The electrical conduction portion 17 is formed, for example, on the insulating substrate 2
This is provided to short-circuit each terminal electrode 13 in order to apply a current to many terminal electrodes 13 at the same time when plating the metallized layer (base layer) formed by electroplating on the metallized layer.

The insulating groove 15 is formed substantially parallel to each side of the insulating substrate 2, and only in the portion where the terminal electrode 13 is formed, that is, in the four corners of the insulating substrate 2, the insulating groove 15 is formed.
Is not formed.

The terminal electrode 13 is provided with a wiring conductor layer formed on the surface of the step portion 3 of the cavity 5 by a via-hole conductor 19.
, Whereby the terminal electrode 13 and the semiconductor element 7 are electrically connected. That is, the via-hole conductor 19 is formed outside the insulating groove 15. From the viewpoint that the via-hole conductor 19 is reliably formed in the insulating substrate 2, the insulating groove 15 is 500 μm from the end surface of the insulating substrate 2.
It is desirable to be formed at least m inward.

The terminal electrode 13 is formed by sequentially laminating a base electrode layer and a plating layer on the surface of the insulating substrate 2. In FIG. 1, for easy understanding, the semiconductor elements 7 and
The step 3 is indicated by a solid line.

In the semiconductor element housing substrate of the present invention, the above-described insulating groove 15 is provided at the joint 21 between the lid 11 and the insulating substrate 2.
It is formed outside.

In the semiconductor element housing substrate formed as described above, as shown in FIG. 3, the thermal stress generated due to the difference in thermal expansion coefficient between the lid 11 and the insulating substrate 2 is different from that of the lid 11 and the insulating substrate. 2 in the region of the junction 21 with
However, in the semiconductor device housing substrate of the present invention, the insulating groove 15 is
1 is formed outside the joint 21 between the insulating substrate 1 and the insulating substrate 2, the thermal stress acting on the insulating groove 15 is reduced,
Damage from the insulating groove 15 can be suppressed.

In the present invention, as shown in FIG. 4, it is desirable to form the insulating groove 35 in a zigzag shape. As described above, by forming the insulating groove 35 in a zigzag shape, the thermal stress acting on the insulating groove 35 is dispersed and the insulating groove 3 is formed.
5 can be further reduced, breakage from the insulating groove 35 can be more reliably prevented, and reliability can be further improved.

It should be noted that the present invention is not limited to the above-described example, and various changes can be made without departing from the gist of the present invention.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, Al ₂ O ₃ , SiO ₂ , MgO, CaO
An appropriate organic binder, a plasticizer and a solvent were added to and mixed with the raw material powder to prepare a slurry, and the slurry was formed into a ceramic green sheet having a thickness of about 300 μm by a well-known doctor blade method.

Thereafter, in order to form a cavity for accommodating a semiconductor element, a green sheet having a thickness of 300 μm was punched at a predetermined position. In addition, punching was performed at a desired position of the ceramic green sheet to form a via hole provided for establishing electrical conduction between the wiring layers.

Thereafter, a metal paste obtained by adding alumina particles to a powder containing W as a main component, and adding and mixing an organic binder, a plasticizer, and a solvent is punched into a via hole formed in the ceramic green sheet. The holes were filled by screen printing. At the same time, a desired pattern was screen-printed.

In order to form terminal electrodes provided on the back surface of the semiconductor element housing substrate, a conductive metallization pattern for short-circuiting each terminal electrode required when performing electrolytic plating in a subsequent step on a green sheet. Was also formed by screen printing.

Thereafter, a desired number of green sheets, each having a desired pattern formed thereon and a metal paste filled in the via hole, are stacked on the green sheet on which the conductive metallized pattern is formed, and the green sheets are further stacked thereon. Then, green sheets that had been subjected to a punching process for cavities were laminated thereon to produce a laminated molded body.

After that, the laminated molded body was placed in a reducing atmosphere comprising a mixed gas of hydrogen (H ₂ ) and nitrogen (N ₂ ) for about 160
Sintered at a temperature of 0 ° C, the main surface is square and one side is 30m
An insulating substrate having a thickness of 1 mm and a thickness of 1 mm was prepared. The cavity had a square shape with a side of 14 mm on the surface of the insulating substrate, and a square shape with a side of 8 mm on the bottom surface to which the semiconductor element was fixed. The via-hole conductor is 0.75 mm from the end face of the insulating substrate.
mm.

In order to confirm the effect of the present invention due to the difference in the size of the insulating substrate, the main surface was square and the side was 20 m.
An insulating substrate having a thickness of 1 mm and a thickness of 1 mm was also prepared. Thereafter, in order to form a nickel (Ni) plating layer on the entire surface of the conductive metallization, the wiring conductor layer formed in the cavity of the insulating substrate and the conductive metallization formed on the bottom surface of the insulating substrate are electrically short-circuited. Then, a plating layer was formed by an electrolytic plating method.

Thereafter, the side of the insulating substrate for evaluation was 3
In the case of a 0 mm insulating substrate, a lid made of square Kovar having a side of 20 mm was joined using a brazing material. When the size of the insulating substrate was 20 mm on one side, a lid made of square Kovar having a side of 16 mm was bonded in the same manner. In addition, since the present semiconductor element housing substrate was for evaluation, no semiconductor element was mounted.

Thereafter, portions of the semiconductor element housing substrates of the present invention and the comparative example, in which each terminal electrode is short-circuited, are deleted by a router (small grinder).
As shown in FIG. 5, in the comparative example, as shown in FIG. 5, the conductive portion was cut to form an insulating groove. As shown in Table 1, the distance L from the outer edge of the joining portion is indicated by a plus sign on the inner side (comparative example) and a minus sign on the outer side (the present invention).

A test for heating the lower surface of the semiconductor element housing substrate was conducted in order to confirm whether the obtained semiconductor element housing substrate for evaluation did not impair the reliability in an actual use environment or the like. Specifically, the semiconductor element housing substrate is 3
After placing on a heater block heated to 00 ° C. and holding for 1 hour, it was confirmed whether or not cracks occurred in the insulating substrate.
The cracks were confirmed by penetrant testing using a penetrant solution.

Further, assuming the actual use condition of the semiconductor element housing board for evaluation, in order to confirm long-term reliability, the semiconductor element housing board is set at a high temperature setting temperature of 125 ° C. and a low temperature setting temperature of −40 ° C. A thermal shock test was performed in which a thermal shock was applied for 1000 cycles. At each of 500 cycles and 1000 cycles, the presence or absence of breakage of the insulating substrate was confirmed by the same cross-sectional observation as described above. Table 1 shows the results.

[0045]

[Table 1]

As is evident from Table 1, the sample Nos. 3, 4, 7, and 8, the sample Nos. In Nos. 1, 2, 5, and 6, cracks did not occur in the insulating substrate in the heater block heating test, and no cracks occurred even after 1000 cycles of the thermal shock test. The sample No. of the comparative example formed inside the sample No. In 3, 4, 7, and 8, cracks occur starting from the insulating groove, and as the number of times of application of the thermal shock test increases, cracks occur, and the reliability decreases.

[0047]

According to the semiconductor device housing substrate of the present invention, the thermal stress generated due to the difference in thermal expansion coefficient between the lid and the insulating substrate is large inside the joint between the lid and the insulating substrate, and is larger than that at the joint. , The thermal stress hardly occurs when it is also outside, but since the insulating groove is formed outside the joint between the lid and the insulating substrate, the thermal stress acting on the insulating groove is small. Damage can be suppressed. Thereby, even in an environment where the semiconductor element housing substrate is used, high reliability can be ensured without destruction of the insulating substrate. For this reason, electrical connection with an external electronic circuit can be secured with high reliability.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor element housing substrate of the present invention.

FIG. 2 is a sectional view of FIG.

FIG. 3 is an explanatory diagram showing thermal stress acting on a semiconductor element housing substrate of the present invention.

FIG. 4 is a plan view showing a state in which zigzag insulating grooves are formed.

FIG. 5 is a sectional view showing a conventional semiconductor element housing substrate.

FIG. 6 is an explanatory view showing thermal stress acting on the semiconductor element housing substrate of FIG. 5;

[Explanation of symbols]

 2 ... insulating substrate 5 ... cavity 7 ... semiconductor element 11 ... lid 13 ... terminal electrode 15, 35 ... insulating groove 21 ... joining part

Claims (3)

[Claims] 1. An insulating substrate, a semiconductor element housed in a cavity of the insulating substrate, a lid joined to the insulating substrate to seal the semiconductor element, and a surface opposite to the mounting surface of the semiconductor element on the insulating substrate. And a plurality of terminal electrodes formed on the side surface and electrically disconnected from each other by the insulating groove, wherein the insulating groove is formed by bonding the lid and the insulating substrate. A semiconductor element housing substrate formed outside a portion. 2. The semiconductor element housing substrate according to claim 1, wherein the insulating groove is formed in a zigzag shape. 3. The semiconductor element housing substrate according to claim 1, wherein the lid is made of a metal, and the insulating substrate is made of a ceramic.