JPH0581229A - Signal processing circuit network - Google Patents

Abstract

PURPOSE:To improve the general use and processing performance of a signal processing circuit network without restricting a digital signal obtained from each neuron only to pulse density expression by providing the network with a selection output circuit. CONSTITUTION:A unit output 26 from each nerve cell simulation unit is outputted as a pulse string, a count-off output is regarded as a network output until a count value of pulse strings reaches a previously set value N, and after reaching the prescribed value N, a count-on output is regarded as the network output. A counter 37 counts the number of pulses in the unit output 26 and sends the counted result to a comparator 38 as a binary value. The comparator 38 compares the prescribed value N set up in a memory 40 with the count value (n) of the counter 37, '0' is outputted as a comparison output in the case of n<=N, or '1' is outputted in the case of n>N. A selection circuit 42 selects and outputs a memory 43 storing the count-off output or a memory 44 storing the count-on output in accordance with the output 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit network for a neural computer which imitates a nerve cell.

[0002]

2. Description of the Related Art The aim of parallel processing of information is to imitate the function of nerve cells (neurons), which are the basic units of information processing in the living body, and to use this "nerve cell mimicking element" as a network to process information in parallel. This is a so-called neural network. Although it is easy to perform character recognition, associative memory, and interlocking control in a living body, there are many things that conventional Neumann computers cannot easily achieve. Many attempts have been made to solve these problems by imitating the nervous system of the living body, particularly the functions peculiar to the living body, that is, parallel processing, self-learning, and the like. Many of these attempts are carried out by computer simulation, and parallel processing is necessary to realize the original function, and for that purpose, the neural network needs to be implemented as hardware.

Among them, an example realized by an electric circuit is shown in FIG. This is disclosed in Japanese Patent Application Laid-Open No. 62-295188, and basically, a plurality of amplifiers 1 having an S-shaped transfer function,
A resistive feedback network 2 is provided which connects the output of each amplifier 1 to the input of the amplifier of the other layer, as indicated by the dashed line. A CR time constant circuit 3 composed of a grounded capacitor and a grounded resistor is individually connected to the input side of each amplifier 1. Then, the input currents I ₁ , I ₂ ,
, _IN are fed to the input of each amplifier 1 and the output is obtained from the set of output voltages of these amplifiers 1.

Here, the strength of the connection between nerve cells is represented by the resistance value of the resistance 4 (the grid point in the resistance feedback network 2) connecting the input / output lines between the cells, and the nerve cell response function Is represented by the transfer function of each amplifier 1. Also, as is well known, the coupling between nerve cells has excitability and inhibitory properties, and is mathematically represented by the sign of the coupling coefficient. However, since it is difficult to realize positive and negative with a constant on the circuit, here, the output of the amplifier 1 is divided into two, and one output is inverted to generate two positive and negative signals. Is properly selected.

Further, FIG. 18 is a diagram of Japanese Patent Laid-Open No. 62-295188.
FIG. 17 shows the contents of the proposal of Japanese Patent Publication, which is an improvement of that of FIG. This is a simplification of the circuit based on mathematical analysis. Instead of the amplifier 1, a negative gain amplifier 5 having a single output is used, and instead of the resistive feedback network 2, a clipped T matrix circuit 6 is used. It is configured by using.

In any case, these circuits are basically of analog type. That is, the input / output amount is represented by a current value or a voltage value, and the internal arithmetic processing is also performed in an analog manner. However, in the case of the analog method, it is difficult to perform stable operation with high accuracy due to, for example, the temperature characteristics of the amplifier and the like, the drift after the power is turned on, and the like. Particularly, in the case of a neural network, the number of amplifiers is required to be at least several hundreds, and nonlinear operation is performed, so that stability of operation is important. Further, it is not easy to change the circuit constant such as the resistance value, and the versatility is poor.

[0007]

From the above,
A digital representation of the neural network is described in, for example, Technical Report of IEICE, ICD88-130.
Reported in "Complete Digital NeuroChip Configuration". However, this is an emulation of the conventional analog type, and the circuit is slightly complicated, such as using an up-down counter.

In order to solve such a drawback, a digital type neuron model was filed by the present applicant in Japanese Patent Application No. 1-1.
No. 79629 has already been proposed, and further, in such a neuron model, a digital signal obtained from the final output layer is converted into a pulse density and appropriately converted into an analog output. But,
According to such a proposal example, it is limited to handling a digital signal as a pulse density, and lacks versatility or processing capability.

[0009]

According to a first aspect of the present invention, in a signal processing circuit network adapted to simultaneously process a plurality of binarized information sequences, at least two or more inputs and each input are provided. And a read means for sequentially reading the memory contents from these memories, a logical product circuit for calculating a logical product of the memory contents sequentially read from the memory and the input information, and a logical product circuit. With respect to the obtained logical product results, a logical sum circuit for calculating logical sums of all inputs by two groups preset for each input, and two groups of logical sum results obtained by these logical sum circuits An output circuit for logically calculating and outputting, a count comparison circuit having a counter for counting the output obtained from this output circuit and comparing it with a preset predetermined value, and outputting different information depending on the comparison result Do It provided a plurality of circuit units and a 択出 force circuit, and the outputs of these circuit units coupled to the input side of the circuit unit of the other circuit units or self connected to hierarchical network.

According to the second aspect of the invention, the first value is set for each input.
A memory and a second memory are provided, and the logical product circuit calculates the logical product of the memory contents sequentially read from the first memory and the input information for each input, and the logical sum circuit obtains the logical product. Regarding the result of these logical products, the second
The logical sum of all inputs is calculated according to the contents of the memory, and the output circuit logically calculates and outputs the logical sum results of the contents obtained by these logical sum circuits. Similar to the described invention, a count comparison circuit and a selection output circuit are provided for the output circuit.

According to the third aspect of the invention, the first value is set for each input.
In addition to providing a memory and a second memory, a first AND circuit for calculating a logical product of the memory contents sequentially read from the first memory and input information for each input, and these obtained by the first AND circuit A first logical sum circuit that calculates logical sums of all inputs with respect to the logical product result of, and a second logical product circuit that calculates the logical product of the memory contents sequentially read from the second memory and the input information for each input , A second logical sum circuit for calculating a logical sum of all inputs with respect to these logical product results obtained by the second logical product circuit, and further to the output circuit as in the invention according to claim 1. A count comparison circuit and a selection output circuit are provided.

According to the inventions of claims 4 to 6, in the inventions of claims 1 to 3, when the two sets of logical sum results obtained by the logical sum circuit of the output circuits do not match, the predetermined set is obtained. And outputs the logical product result of the external input different from the input or another memory content provided accompanying the external input and the external input when they coincide with each other.

Further, in the invention described in claim 7, in these inventions, an output changing circuit for changing the own output by comparing the output of its own circuit unit with the output of another circuit unit is provided.

[0014]

According to the invention described in claims 1 to 6, the output obtained from the output circuit of each unit circuit is counted by the counting comparison circuit and compared with a preset predetermined value, and selected according to the comparison result. Since different information is output by the output circuit, the output is proportional to the number of pulses, that is, the intensity of the pulse, and depends on the time because it depends on the count. Therefore, a digital signal output with high performance and processing capability can be obtained. Further, since the reset signal of the counter can be selected as appropriate, various operations can be performed when the network is configured. In addition, as in the invention described in claim 7, the output changing circuit changes its own output by comparing its own output with the output of another circuit unit, so that various operations are performed in the case of a network configuration. You will get it.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. First, as a basic, input / output signals, intermediate signals, coupling coefficients for the circuit unit forming each neuron,
All the teacher signals and the like are represented by a pulse train binarized by "0" and "1". All these signals are synchronized. Now, if the i-th input is y _i , the input y
The signal intensity of _i is represented by a pulse density, and is represented by the number of states of "1" within a certain fixed time, for example, as in the pulse train shown in FIG. That is, the example of FIG. 2 represents 4/6, and the signal is 4 "1" and 6 "0" in 6 sync pulses.
Is two. At this time, the arrangement of "1" and "0" is
It is desirable to be random.

On the other hand, the coupling coefficient T _ij indicating the degree of coupling between neurons is similarly expressed by the pulse density, and is prepared in advance in the memory as a pulse train of "0" and "1". The example shown in FIG. 3 represents “101010” = 3/6. Also in this case, it is desirable that the arrangement of "1" and "0" is random.

Then, this pulse train is sequentially read from the memory in response to the synchronous clock, and the logical product with each input signal pulse train is taken (y _i ∩ T _ij ). This is the neuron j
Input to. In the case of the above example, when an input signal is input as "101101", a pulse train is called from the memory in synchronization with this and "101000" as shown in FIG. It is obtained, which shows that the input y _i is transformed by the coupling coefficient T _ij and the pulse density becomes 2/6.

The pulse density resulting from the logical product is approximately the product of the pulse density of the input signal and the pulse density of the coupling coefficient, and has the same function as the analog coupling coefficient. This is because the longer the signal train is, the more "1"
The more random the arrangement of "0" and "0", the closer to the product. When the pulse train of the coupling coefficient is shorter than the input pulse train and there is no data to be read, the head of the data may be returned to and the reading may be repeated.

Since one nerve cell unit has multiple inputs, there are many "logical product results of input signals and coupling coefficients", and the OR circuit takes the logical sum of these.
Since the inputs are synchronized, for example, the first data is "101000" and the second data is "010000".
In the case of, the OR of both results in “111000”. This is simultaneously calculated by multiple inputs (the number of inputs is m) and output. That is, it becomes as shown in FIG. This corresponds to the sum calculation and the non-linear function (sigmoid function) part in the analog calculation.

When the pulse density is low, the pulse density of the logical sum thereof approximately matches the sum of the pulse densities. As the pulse density increases, the output of the OR circuit gradually becomes saturated, and the output does not match the sum of the pulse densities, resulting in non-linearity. In the case of the logical sum, the pulse density does not become larger than 1 and does not become smaller than 0, and is a monotonically increasing function, which is approximately the same as the sigmoid function.

By the way, the coupling has excitability and inhibition, and in the case of numerical calculation, it is represented by the sign of the coupling coefficient, and in the case of an analog circuit, T _ij becomes negative as described above (inhibition coupling). Uses an amplifier to invert the output and couple it to other nerve cells with a resistance value corresponding to T _ij . In this respect, in this embodiment of the digital system, the pulse density is always positive, but if any one of the following three methods is used, even if the coupling coefficient is represented by the pulse density, the excitement of the coupling will occur. It is possible to deal with the problem and restraint.

First, FIG. 6 shows a structure corresponding to the inventions of claims 1 and 4. Here, whether excitatory or inhibitory is set for each connection in advance, and the above-described logical sum is separately calculated for the excitatory connective group and the inhibitory connective group. Or
For each input, set excitatory or inhibitory in advance,
The excitatory input group and the inhibitory input group are ORed separately. For example, as shown in FIG. 6, excitatory coupling group 11a and inhibitory coupling group 11b are grouped in advance at the input stage, and memories 13a and 13b storing coupling coefficients T _ij are provided for each input 12. Just do it. The logical product of the input signal and the pulse train of the coupling coefficient T _ij is AN
It is taken by the D gates (logical product circuits) 14a and 14b. Then, the OR gates (OR circuits) 15a and 15b perform OR operation for each of the groups 11a and 11b,
Result of logical sum of excitability group 11a (OR gate 15a
Output) 16a and inhibitory group 11b ORed result (O
R gate 15b output) 16b.

On the other hand, FIG. 7 shows a structure corresponding to the inventions of claims 2 and 5. In this method, each connection has a memory (second memory) 17 indicating whether the connection is excitatory or inhibitory, and the excitability or inhibitory property of the bond is arbitrarily set by a gate circuit 18 depending on the content. Allow setting. By passing through such a gate circuit 18, the OR gates 15a, 1 are formed by the excitatory coupling group and the inhibitory coupling group determined by the contents of the memory 17.
5b is used to take the logical OR separately to obtain logical OR results 16a and 16b for each group.

Further, FIG. 8 shows a structure corresponding to the invention of claims 3 and 6. In this method, an excitatory coupling coefficient and an inhibitory coupling coefficient are provided for each coupling, and as shown in FIG. 8, both are stored in a memory (first memory) 19 and a memory (second memory) 20, respectively. Put. This is equivalent to expressing the coupling coefficient in the form of the sum of positive and negative quantities. Then, the logical product of all the input signals and the excitatory coupling coefficient stored in the memory 19 is calculated by the AND gate (first logical product circuit) 21, and the logical sum of the outputs of these AND gates 21 is OR gate. (First OR circuit) 15a. On the other hand, the logical product of all the input signals and the inhibitory coupling coefficient stored in the memory 20 is AND gate (second gate).
AND gate 2 and these AND gates 2
The OR gate of the two outputs is OR gate (second OR circuit)
Take by 15b. In this way, excitatory / inhibitory sex OR results 16a, 16b are obtained.

Then, the logical sum result 1 thus obtained
6a and 16b are output after undergoing logical operation processing by the output circuit 23. Here, as the processing by the output circuit 23, if the result of the OR of the excitatory group and the result of the OR of the inhibitory group do not match, the result of the OR of the excitatory group is output (that is, the logic of the excitatory group). If the sum result is "0" and the OR result of the inhibitory group is "1", "0" is output, and conversely, the OR result of the excitatory group is "1" and the OR of the inhibitory group is output. If the result is "0", "1" is output). Further, when the logical sum results of both groups match, "0" or "1" is output.

For this purpose, the output circuit 23 according to the present invention as defined in claims 1, 2 and 3 is constructed, for example, as shown in FIG. 9 or 10. FIG. 9 shows the OR result 16b of the inhibitory group.
Is passed through an inverter 24, and the OR result 16a of the excitatory group is directly input to the AND gate 25 to perform a logical product and form a unit output 26.
In FIG. 10, an OR gate 27 is used in place of the AND gate 25 to take a logical sum.

The output circuit 23 according to the present invention is constructed as shown in FIG. 11, for example.
In this method, first, an input 28 set separately from the input 12 and a memory 29 are also provided in association with this input, and the logical product of the input 28 and the contents of the memory 29 is AND gate 3
Take by 0. Then, both OR results 16a, 16
b is input to the exclusive OR gate 31, and when the two do not match, the predetermined result 16a side is output as the unit output 26 through the processing by the AND gate 32 and the OR gate 33. On the other hand, when both match, exclusive O
The AND product of the output of the R gate 31 inverted by the inverter 34 and the output of the AND gate 30 is taken by the AND gate 35 and output as the unit output 26 via the OR gate 33. Alternatively, when they match, the input 28 may be directly output as the unit output 26.

The above description is for the nerve cell mimicking unit (circuit unit) 36 alone, but it is necessary to provide a plurality of nerve cell mimicking units 36 to form a network in order to actually function. To this end, for example, as shown in FIG. 12, a hierarchical network structure is formed such as an input layer, an intermediate layer, and an output layer (final output layer), and the output of a neuron mimicking unit 36 is imitated by each neuron of the next layer. Coupled to the input of unit 36. And if the whole network is synchronized, it is possible to calculate with the same function one after another.

Here, since the data of the input 12 is generally an analog value in many cases, in order to convert this into a pulse train, a random number is generated by a random number generator, this is compared with the input, and its magnitude is judged. By generating "1" or "0", the desired value can be obtained. On the other hand, the unit output 26 is also output as a pulse train, and its value can be obtained by using a counter or the like. However, depending on the application, it is possible to use the pulse train as it is.

In the present embodiment, however, the processing of the unit output 26 from each nerve cell mimicking unit 36 is devised in such a premise structure. As described above, the unit output 26 is output as a pulse train,
In this embodiment, this pulse train is counted, and the count OFF output is used as the output of this network until it reaches a preset predetermined value N, and after reaching the preset value N, the count O is counted.
The N output is used as the output of the network. For example, assuming that N = 8 and the count value for the pulse train is n, as shown in FIG. 1B, the count OFF output is set as the network output until n = 1 to 8, and when n = 8 (= N), The count-ON output is used as the network output from the reference clock of. In this example, two types of output states are realized by comparing N and n. However, by increasing the values to be compared,
For example, N ₁ and N ₂ may be used to realize three or more different output states.

FIG. 1 (a) shows a circuit configuration for processing the unit output 26 of each nerve cell mimicking unit 36 for this purpose. First, a count comparing circuit 39 having a counter 37 and a comparator 38 is provided. There is. Counter 37
Is to count the number of pulses in the pulse train of the unit output 26 and send the result as a binary value to the comparator 38. Further, the comparator 38 compares the predetermined value N preset and registered in the memory 40 with the count value n obtained from the counter 37, and outputs an output according to the magnitude. The comparison output 41 is "0" if n≤N, and "1" is output if n> N.

A selection output circuit 42 is connected to the output side of the comparator 38. Here, the selection output circuit 4
In FIG. 2, first, a memory 43 storing a count OFF output and a memory 44 storing a count ON output are prepared. The memory 43 side is input to the AND gate 46 together with the inverter 45 so that the output of the comparator 38 is selected when the output of the comparator 38 is "0", and the memory 44 side is selected so that the output of the comparator 38 is selected when the output of the comparator 38 is "1".
Input to the D gate 47, these AND gates 46,
The output of 47 is input to the OR gate 48. This O
The output 49 from the R gate 48 corresponds to the output in FIG. The output of the OR gate 48 may be the final output 50 of the neuron mimicking unit 36. Alternatively, as shown in the figure, the logical product of the output 49 from the OR gate 48 and the unit output 26 is obtained by the AND gate 51 (or the logical sum may be obtained by the OR gate), and the result is the final output. It may be set to 50. Alternatively, the memories 43 and 44 may be omitted, and the output 41 of the comparator 38 and the unit output 26 may be logically operated to obtain the final output 50. Furthermore, the comparator 38
The output 41 may be used as it is as the final output 50.

When the reset signal 52 is input to the counter 37, the nerve cell mimicking unit 36 in the count ON output state is in the output OFF state and a new count is started. Therefore, various operations can be performed by selecting the reset signal 52.

An example thereof will be described with reference to FIG. Here, a sustaining circuit 59 for sustaining the count ON output within a fixed time is added as shown in FIG.
First, a counter 53 for counting the pulses of the comparison output 41 from the comparator 38 is provided, which is converted into a binary value 54 of n ₂ and output to the comparator 55. The comparator 55 compares a predetermined value N ₂ preset in the memory 56 with the binary value 54 n ₂ .
If N ₂ ≧ n ₂ , “0” is output, and if N ₂ <n ₂ , “1” is output. This is input to the counters 37 and 53 as the reset signal 52.

As a reset signal for the counters 37 and 53, an OR gate 57 is used to output an arbitrary reset signal 58 from the outside and an output from the comparator 55.
R may be taken.

This enables operation control as shown in FIG. 13 (b). First, as described above, the pulse train that is the unit output 26 of the nerve cell mimicking unit 36 is counted, and the count value n ₁ (corresponding to n in the case shown) is set to a predetermined value N ₁ (in FIG. 1). The count OFF output is used as the output of this network until the value reaches the predetermined value N _1, and the count ON output is used as the output of the network after reaching the predetermined value N ₁ . For example, N ₁ = 5, when the count value for the pulse sequence and n _1, to n ₁ = 1 to 5 as shown in FIG. 13 (b) and network output count OFF _{output, n 1 = 5 (= N} 1 ), The count-on output is used as the network output from the next reference clock. Here, this count ON output state is maintained within the time when the reference clock for the preset pulse N ₂ is generated. FIG. 1B shows an operation example in the case of N ₂ = 5, and after the count ON output is completed, the count n ₁ from the output layer is reset and starts counting again.

By the way, the above description is for the output of one nerve cell mimicking unit 36,
The mutual output relationship when the network is configured as illustrated in FIG. 12 in order to exert the function will be described.
In this case, various operations can be performed by using a signal depending on the output from the other nerve cell mimicking unit 36 as the reset signal 52.

Basically, as shown in FIG.
This is because each output (count ON / OFF output) is independent. Further, the resetting of each counter 37 is performed by an external signal to all counters 37.
Alternatively, it is performed only for the grouped counters 37. FIG. 14 shows, for example, three outputs A, B, C of a layer.
The relationship (corresponding to the output 26) is shown. First, the timing T
From 1, the number of pulses of each output A, B, C is started to be counted, and when the count value n _A of the output A first reaches the predetermined value N, a count ON output is output. Then, the count value n _C is the predetermined value N of the output C
When it reaches, the count ON output is output. Further, the count value n _B output B issues a count ON output reaches a predetermined value N. In such an operation, since the outputs are independent, the count ON output state remains. Counter 37
Is reset at a certain time interval or by an arbitrary input from the outside of the network, the timing T in FIG.
2. As shown by T3, this is performed for all the nerve cell mimicking units 36 in a certain layer or the nerve cell mimicking units 36 grouped in the output layer. That is, the count value is set to a certain value by the reset signal 52 input to the reset terminal of the counter 37. An example of using the reset signal 52 depending on the output from another nerve cell mimicking unit 36 in FIG. Indicates. First, the output relationship between the output layers will be described. FIG. 15B shows the relationship between, for example, three outputs A, B, C (corresponding to the output 26) of a certain layer. First, at timing T4, the number of pulses of each output A, B, C is started to be counted, and when the count value n _A of the output A reaches the predetermined value N for the first time, the count ON output is output. Then, the count value n _C of the output C at the same time issues a count ON output reaches a predetermined value N, the output A is allowed to reset its counters 37 to count OFF output and n _A = 0. next,
When the count value n _B of the output B reaches the predetermined value N, the output B is set to the count ON output, and at the same time, the output C is set to the count OFF output to reset the counter 37 to n _C = 0.
Thus, the unit output 26 from all the nerve cell mimicking units 36 of a certain output layer or the unit output 26 from the grouped nerve cell mimicking units 36 of the output layers has a count value of a predetermined value N. Only the output that has reached the count ON output state is set, and those that were in the count output ON state until then are reset to the count OFF state.

The reset circuit 62 shown in FIG. 15A is an output changing circuit for this purpose. First, the comparator 3 in another nerve cell mimicking unit 36 located in the output layer
An OR gate 63 that receives the output group 41 _ALL from 8 is provided (for this reason, the output 41 from its own comparator 38 is output to the OR gate in another reset circuit by the output group 41).
_(Which is input as one of _ALL ), is input to the exclusive OR gate 64 together with the output 41 from the own comparator 38, and is further input to the AND gate 65. The output of the AND gate 65 is connected to the reset terminal of the counter 37.

Thus, first, when the count value n reaches the predetermined value N in the self unit and the output 41 is generated from the comparator 38, the standby state for waiting the AND gate 65 is set, and in such a state, in another unit. When the count value n reaches the predetermined value N and any one of the output groups 41 _ALL becomes “1”, it coincides with this output 41, and the exclusive O
The output from the R gate 64 to the AND gate 65 becomes "1", the AND gate 65 is opened, and the reset signal 52 resets the counter 37.

As described above, the reset shown at timing T5 in FIG. 15 (b) is performed by, for example, an arbitrary input 58 from the outside of the network for all nerve cell mimicking units 36 of an output layer or its output layer. An example of resetting the grouped nerve cell mimicking units 36 is shown.

Another example of using the reset signal 52 depending on the output from another nerve cell mimicking unit 36 is shown in FIG. In this example, regarding the output relationship among a plurality of nerve cell mimicking units 36 in a certain output layer, the nerves whose count value n first reaches a predetermined value N in all or grouped output layers of the output layer. Only the cell mimicking unit 36 is set to the count ON output, and the remaining nerve cell mimicking units 36 are all set to the count OFF output. This is maintained within a certain period of time or until the reset signal 52 is input from the outside. FIG. 16 (b) shows the situation. At timing T6, the number of pulses of each output A, B, C is started to be counted, and the count value n of the output A is
_{When A} reaches the predetermined value N for the first time (timing T6), the count ON output is output. This state is maintained at a certain fixed time interval or until the timing T8 when the reset signal 52 is input from the outside. When the reset signal 52 is input, each counter 37 is reset and starts counting anew.

FIG. 16A shows a circuit configuration for realizing such a function. In a certain output layer, an output group 41 from a comparator 38 attached to all or grouped nerve cell mimicking units 36. O with _ALL as input
At least one gate circuit 67 having an R gate 66 is provided for all or grouped gate circuits.
An exclusive OR having the output 68 from the gate circuit 67 and the output 41 from its own comparator 38 as inputs
A gate circuit 70 serving as an output changing circuit is provided by the gate 69 and the OR gate 57 which receives the output of the exclusive OR gate 69 and the reset signal 58.

In such a configuration, the comparator 3
When the output 41 from 8 and the output 68 from the gate circuit 67 both match with "1" or "0", the exclusive OR
Since the output of the gate 69 is "0", the counter 37 is not reset and the counting is continued. For this reason,
When the output 41 of the comparator 38 is "1", the count ON output is continuously output. On the other hand, the output 41 of the comparator 38 is "0", and even if one of the other nerve cell mimicking units 36 has a count ON output, the outputs do not match and the output of the exclusive OR gate 56 becomes "1". , The counter 37 is forcibly reset and the count OFF output continues to be output, and this state is maintained until the reset signal 58 is input.

By the way, the method of expressing and processing a signal with a pulse density as described above is useful not only for actual circuits but also for simulation on a computer. That is,
Although the calculation is performed serially on the computer, the calculation speed is remarkably improved as compared with the calculation using the analog value, since only the binary logical calculation of "0" and "1" is performed. Further, in general, real number arithmetic operations require a large number of machine cycles for one calculation, but the number of arithmetic operations is small. Furthermore, if only logical operations are performed, there is an advantage that a low-level language for high-speed processing is easy to use.

It is not necessary that all of the above-mentioned processes be implemented as a circuit, and some or all of them be performed by software. Further, the circuit configuration is not limited to the illustrated one, and may be replaced with another circuit having an equivalent logic, or the above logic may be replaced with a negative logic.

[0047]

Since the present invention is configured as described above, according to the invention described in claims 1 to 6, the output obtained from the output circuit of each unit circuit is counted by the count comparison circuit and set in advance. The selected output circuit outputs different information according to the comparison result, and the output is proportional to the number of pulses, that is, the intensity of the pulse. Therefore, it is not limited to the one handled as the pulse density, and a digital signal output having higher versatility and processing capability can be obtained. Moreover, since the reset signal of the counter can be appropriately selected, it is possible to use various signals in a network configuration. In the same manner, the output changing circuit as in the invention described in claim 7 can be used to perform the operation so that the ratio between its own output and the output of another circuit unit can be increased. By also by changing its own output, and as it can perform various operations when the network configuration.

[Brief description of drawings]

1A and 1B show the gist of the invention described in claims 1 to 6, wherein FIG. 1A is a circuit diagram and FIG. 1B is a timing chart.

FIG. 2 is a timing chart showing a pulse train for explaining a basic operation.

FIG. 3 is a timing chart showing a pulse train for explaining a basic operation.

FIG. 4 is a timing chart showing a pulse train for explaining a basic operation.

FIG. 5 is a timing chart showing a pulse train for explaining a basic operation.

FIG. 6 is a circuit diagram showing a configuration corresponding to the invention of claims 1 and 4.

FIG. 7 is a circuit diagram showing a configuration corresponding to the invention of claims 2 and 5.

FIG. 8 is a circuit diagram showing a configuration corresponding to the invention of claims 3 and 6.

FIG. 9 is a circuit diagram showing an example of the configuration of an output circuit according to the invention described in claims 1, 2 and 3.

FIG. 10 is a circuit diagram showing another example of the configuration of the output circuit according to the invention described in claims 1, 2 and 3.

FIG. 11 is a circuit diagram showing an example of a configuration of an output circuit according to the invention described in claims 4, 5, and 6.

FIG. 12 is a conceptual diagram showing a network configuration.

13A and 13B show modified examples, in which FIG. 13A is a circuit diagram and FIG. 13B is a timing chart.

FIG. 14 is a timing chart.

FIG. 15 shows an example of the invention according to claim 7,
(a) is a circuit diagram and (b) is a timing chart.

FIG. 16 shows another example of the invention according to claim 7,
(a) is a circuit diagram and (b) is a timing chart.

FIG. 17 is a circuit diagram showing a conventional example.

FIG. 18 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 12 inputs 13 memory 14 logical product circuit 15 logical sum circuit 16 logical sum output 17 second memory 19 first memory 20 second memory 21 first logical product circuit 22 second logical product circuit 23 output circuit 28 external input 29 memory 36 circuit Unit 39 Count comparison circuit 42 Selection output circuit 62, 70 Output change circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Furuta 1-3-3 Nakamagome, Ota-ku, Tokyo Stock company Ricoh Co., Ltd. (72) Takashi Kitaguchi 1-3-6 Nakamagome, Ota-ku, Tokyo Shares Company Ricoh

Claims (7)

[Claims] 1. A signal processing circuit network for simultaneously processing a plurality of binarized information sequences, wherein at least 2
One or more inputs, a memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and a logical product of the memory contents sequentially read from the memory and the input information is calculated for each input. An AND circuit, an OR circuit that calculates the logical OR of all the inputs for each of the two sets preset for each input of these AND results obtained by the AND circuit, and the OR circuit An output circuit that performs a logical operation of the two sets of logical sum results and outputs the result, and a count comparison circuit that has a counter that counts the output obtained from the output circuit and that compares the output with the predetermined value. A plurality of circuit units having a selection output circuit that outputs different information according to the comparison result are provided, and the outputs of these circuit units are connected to the input side of another circuit unit or its own circuit unit to form a hierarchy. Signal processing circuitry, characterized in that connected to the network. 2. In a signal processing circuit network adapted to simultaneously process a plurality of binarized information sequences, at least 2
One or more inputs, a first memory and a second memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and memory contents and input information sequentially read from the first memory. A logical product circuit that calculates a logical product for each input, a logical sum circuit that calculates a logical sum of all inputs for each logical product result obtained by the logical product circuit according to the contents of the second memory, and these logical circuits An output circuit for performing a logical operation of the contents of the logical sum obtained by the sum circuit and outputting the result, and a counter for counting the output obtained from the output circuit and comparing with a preset predetermined value A plurality of circuit units each having a comparison circuit and a selection output circuit that outputs different information depending on the comparison result are provided, and the outputs of these circuit units are connected to the input side of another circuit unit or its own circuit unit. By the signal processing circuitry, characterized in that connected to the hierarchical network. 3. A signal processing circuit network for simultaneously processing a plurality of binarized information sequences, wherein at least 2
One or more inputs, a first memory and a second memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and memory contents and input information sequentially read from the first memory. From a first logical product circuit that calculates a logical product for each input, a first logical product circuit that calculates a logical sum of all logical inputs of these logical product results obtained by the first logical product circuit, and a second memory A second AND circuit that calculates the logical product of the sequentially read memory contents and input information for each input, and the logical sum of all inputs of these logical product results obtained by the second AND circuit A second OR circuit, an output circuit for performing a logical operation of two sets of OR results obtained by these OR circuits, and outputting the result; and a counter for counting the output obtained from this output circuit. Compare with a preset value A plurality of circuit units each having a number comparison circuit and a selection output circuit that outputs different information according to the comparison result are provided, and the outputs of these circuit units are coupled to the input side of another circuit unit or its own circuit unit. A signal processing circuit network characterized by being connected in a hierarchical network. 4. A signal processing circuit network for simultaneously processing a plurality of binarized information sequences, wherein at least 2
One or more inputs, a memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and a logical product of the memory contents sequentially read from the memory and the input information is calculated for each input. An AND circuit, an OR circuit that calculates the logical OR of all the inputs for each of the two sets preset for each input of these AND results obtained by the AND circuit, and the OR circuit When the two sets of logical OR results do not match, a predetermined set of logical OR results is output, and when they match, the input and another external input or another memory provided in association with this external input An output circuit that outputs the logical product result of the contents and this external input, a count comparison circuit that has a counter that counts the output obtained from this output circuit and compares it with a predetermined value, and a comparison result Depending on A plurality of circuit units having a selective output circuit for outputting information are provided, and the outputs of these circuit units are connected to the input side of another circuit unit or its own circuit unit and connected in a hierarchical net-like structure. Signal processing network. 5. A signal processing circuit network for simultaneously processing a plurality of binarized information sequences, wherein at least 2
One or more inputs, a first memory and a second memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and memory contents and input information sequentially read from the first memory. A logical product circuit that calculates a logical product for each input, a logical sum circuit that calculates a logical sum of all inputs for each logical product result obtained by the logical product circuit according to the contents of the second memory, and these logical circuits When these logical sum results obtained by the sum circuit do not match, the predetermined logical sum result is output, and when they match, the input and another external input or another external input provided in association with this external input. An output circuit that outputs a logical product result of the memory contents and this external input, a count comparison circuit that has a counter that counts the output obtained from this output circuit and compares the output with the predetermined value, and a comparison result In response A plurality of circuit units each having a selective output circuit for outputting different information and connecting the outputs of these circuit units to the input side of another circuit unit or its own circuit unit and connecting them in a hierarchical net-shape. Characteristic signal processing network. 6. A signal processing circuit network for simultaneously processing a plurality of binarized information sequences, wherein at least 2
One or more inputs, a first memory and a second memory provided for each input, a reading means for sequentially reading the memory contents from these memories, and memory contents and input information sequentially read from the first memory. From a first logical product circuit that calculates a logical product for each input, a first logical product circuit that calculates a logical sum of all logical inputs of these logical product results obtained by the first logical product circuit, and a second memory A second AND circuit that calculates the logical product of the sequentially read memory contents and input information for each input, and the logical sum of all inputs of these logical product results obtained by the second AND circuit When the logical sum results of the second logical sum circuit and the two sets of logical sum results obtained by these logical sum circuits do not match, a predetermined logical sum result is output, and when they match, the input and another external Input or this external input An output circuit that outputs a logical product result of the other memory contents and this external input, and a count comparison circuit that has a counter that counts the output obtained from this output circuit and that compares it with a preset predetermined value , A plurality of circuit units each having a selection output circuit that outputs different information according to the comparison result are provided, and the outputs of these circuit units are connected to the input side of another circuit unit or its own circuit unit to form a hierarchical net shape. A signal processing circuit network characterized by being connected to. 7. An output changing circuit for changing its own output by comparing the output of its own circuit unit with the output of another circuit unit.
The signal processing circuit network according to 3, 4, 5 or 6.